Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5

[lts 3.1.x] format codes

11 files changed, 3698 insertions, 3698 deletions

diff --git a/bsp/dm365/drivers/davinci_emac.c b/bsp/dm365/drivers/davinci_emac.c
index 9043493290..7ad539fb09 100644
--- a/bsp/dm365/drivers/davinci_emac.c
+++ b/bsp/dm365/drivers/davinci_emac.c
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 
@@ -15,8 +15,8 @@
 #include <dm36x.h>
 #include "davinci_emac.h"
 
-#define MMU_NOCACHE_ADDR(a)      	((rt_uint32_t)a | (1UL<<29))
-#define CACHE_LINE_SIZE	32
+#define MMU_NOCACHE_ADDR(a)         ((rt_uint32_t)a | (1UL<<29))
+#define CACHE_LINE_SIZE 32
 
 extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
 extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
@@ -24,22 +24,22 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
 /* EMAC internal utility function */
 static inline rt_uint32_t emac_virt_to_phys(void *addr)
 {
-	return (rt_uint32_t)addr;
+    return (rt_uint32_t)addr;
 }
 
 static inline rt_uint32_t virt_to_phys(void *addr)
 {
-	return (rt_uint32_t)addr;
+    return (rt_uint32_t)addr;
 }
 
 /* Cache macros - Packet buffers would be from pbuf pool which is cached */
 #define EMAC_VIRT_NOCACHE(addr) (addr)
 #define EMAC_CACHE_INVALIDATE(addr, size) \
-	mmu_invalidate_dcache(addr, size)
+    mmu_invalidate_dcache(addr, size)
 #define EMAC_CACHE_WRITEBACK(addr, size) \
-	mmu_clean_dcache(addr, size)
+    mmu_clean_dcache(addr, size)
 #define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \
-	mmu_clean_invalidated_dcache(addr, size)
+    mmu_clean_invalidated_dcache(addr, size)
 
 /* DM644x does not have BD's in cached memory - so no cache functions */
 #define BD_CACHE_INVALIDATE(addr, size)
@@ -53,34 +53,34 @@ static struct emac_priv davinci_emac_device;
 static unsigned long emac_bus_frequency;
 static unsigned long mdio_max_freq;
 
-#define EMAC_AUTONEG_TIMEOUT	5000000	
-#define EMAC_LINK_TIMEOUT	        500000  
+#define EMAC_AUTONEG_TIMEOUT    5000000
+#define EMAC_LINK_TIMEOUT           500000
 
 
 /* EMAC TX Host Error description strings */
 static char *emac_txhost_errcodes[16] = {
-	"No error", "SOP error", "Ownership bit not set in SOP buffer",
-	"Zero Next Buffer Descriptor Pointer Without EOP",
-	"Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
-	"Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
-	"Reserved", "Reserved", "Reserved", "Reserved"
+    "No error", "SOP error", "Ownership bit not set in SOP buffer",
+    "Zero Next Buffer Descriptor Pointer Without EOP",
+    "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error",
+    "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
+    "Reserved", "Reserved", "Reserved", "Reserved"
 };
 
 /* EMAC RX Host Error description strings */
 static char *emac_rxhost_errcodes[16] = {
-	"No error", "Reserved", "Ownership bit not set in input buffer",
-	"Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
-	"Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
-	"Reserved", "Reserved", "Reserved", "Reserved"
+    "No error", "Reserved", "Ownership bit not set in input buffer",
+    "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved",
+    "Reserved", "Reserved", "Reserved", "Reserved", "Reserved",
+    "Reserved", "Reserved", "Reserved", "Reserved"
 };
 
-#define emac_read(reg)		  davinci_readl(priv->emac_base + (reg))
+#define emac_read(reg)        davinci_readl(priv->emac_base + (reg))
 #define emac_write(reg, val)      davinci_writel(val, priv->emac_base + (reg))
 
-#define emac_ctrl_read(reg)	  davinci_readl((priv->ctrl_base + (reg)))
+#define emac_ctrl_read(reg)   davinci_readl((priv->ctrl_base + (reg)))
 #define emac_ctrl_write(reg, val) davinci_writel(val, (priv->ctrl_base + (reg)))
 
-#define emac_mdio_read(reg)	  davinci_readl(priv->mdio_base + (reg))
+#define emac_mdio_read(reg)   davinci_readl(priv->mdio_base + (reg))
 #define emac_mdio_write(reg, val) davinci_writel(val, (priv->mdio_base + (reg)))
 
 static void emac_int_enable(struct emac_priv *priv);
@@ -91,74 +91,74 @@ static int emac_init_txch(struct emac_priv *priv, rt_uint32_t ch);
 
 /* Wait until mdio is ready for next command */
 #define MDIO_WAIT_FOR_USER_ACCESS\
-		while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
-			MDIO_USERACCESS_GO) != 0)
+        while ((emac_mdio_read((MDIO_USERACCESS(0))) &\
+            MDIO_USERACCESS_GO) != 0)
 
 static int emac_mii_read(struct emac_priv *priv, int phy_id, int phy_reg)
 {
-	unsigned int phy_data = 0;
-	unsigned int phy_control;
+    unsigned int phy_data = 0;
+    unsigned int phy_control;
 
-	/* Wait until mdio is ready for next command */
-	MDIO_WAIT_FOR_USER_ACCESS;
+    /* Wait until mdio is ready for next command */
+    MDIO_WAIT_FOR_USER_ACCESS;
 
-	phy_control = (MDIO_USERACCESS_GO |
-		       MDIO_USERACCESS_READ |
-		       ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
-		       ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
-		       (phy_data & MDIO_USERACCESS_DATA));
-	emac_mdio_write(MDIO_USERACCESS(0), phy_control);
+    phy_control = (MDIO_USERACCESS_GO |
+               MDIO_USERACCESS_READ |
+               ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
+               ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
+               (phy_data & MDIO_USERACCESS_DATA));
+    emac_mdio_write(MDIO_USERACCESS(0), phy_control);
 
-	/* Wait until mdio is ready for next command */
-	MDIO_WAIT_FOR_USER_ACCESS;
+    /* Wait until mdio is ready for next command */
+    MDIO_WAIT_FOR_USER_ACCESS;
 
-	return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
+    return emac_mdio_read(MDIO_USERACCESS(0)) & MDIO_USERACCESS_DATA;
 
 }
 
 static int emac_mii_write(struct emac_priv *priv, int phy_id,
-			  int phy_reg, rt_uint16_t phy_data)
+              int phy_reg, rt_uint16_t phy_data)
 {
 
-	unsigned int control;
+    unsigned int control;
 
-	/*  until mdio is ready for next command */
-	MDIO_WAIT_FOR_USER_ACCESS;
+    /*  until mdio is ready for next command */
+    MDIO_WAIT_FOR_USER_ACCESS;
 
-	control = (MDIO_USERACCESS_GO |
-		   MDIO_USERACCESS_WRITE |
-		   ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
-		   ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
-		   (phy_data & MDIO_USERACCESS_DATA));
-	emac_mdio_write(MDIO_USERACCESS(0), control);
+    control = (MDIO_USERACCESS_GO |
+           MDIO_USERACCESS_WRITE |
+           ((phy_reg << 21) & MDIO_USERACCESS_REGADR) |
+           ((phy_id << 16) & MDIO_USERACCESS_PHYADR) |
+           (phy_data & MDIO_USERACCESS_DATA));
+    emac_mdio_write(MDIO_USERACCESS(0), control);
 
-	return 0;
+    return 0;
 }
 
 static int emac_mii_reset(struct emac_priv *priv)
 {
-	unsigned int clk_div;
-	int mdio_bus_freq = emac_bus_frequency;
+    unsigned int clk_div;
+    int mdio_bus_freq = emac_bus_frequency;
 
-	if (mdio_max_freq && mdio_bus_freq)
-		clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
-	else
-		clk_div = 0xFF;
+    if (mdio_max_freq && mdio_bus_freq)
+        clk_div = ((mdio_bus_freq / mdio_max_freq) - 1);
+    else
+        clk_div = 0xFF;
 
-	clk_div &= MDIO_CONTROL_CLKDIV;
+    clk_div &= MDIO_CONTROL_CLKDIV;
 
-	/* Set enable and clock divider in MDIOControl */
-	emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE));
+    /* Set enable and clock divider in MDIOControl */
+    emac_mdio_write(MDIO_CONTROL, (clk_div | MDIO_CONTROL_ENABLE));
 
-	return 0;
+    return 0;
 
 }
 
 
 
 /* Duplex, half or full. */
-#define DUPLEX_HALF		0x00
-#define DUPLEX_FULL		0x01
+#define DUPLEX_HALF     0x00
+#define DUPLEX_FULL     0x01
 
 static void udelay(rt_uint32_t us)
 {
@@ -169,83 +169,83 @@ static void udelay(rt_uint32_t us)
 
 static void davinci_emac_phy_reset(rt_device_t dev)
 {
-	int i;
-	rt_uint16_t status, adv;
-	struct emac_priv *priv = dev->user_data;;
+    int i;
+    rt_uint16_t status, adv;
+    struct emac_priv *priv = dev->user_data;;
 
-	adv = ADVERTISE_CSMA | ADVERTISE_ALL;
-	emac_mii_write(priv, priv->phy_addr, MII_ADVERTISE, adv);
-	rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name);
-	emac_mii_write(priv, priv->phy_addr, MII_BMCR, (BMCR_ANENABLE
-					 | BMCR_ANRESTART));
+    adv = ADVERTISE_CSMA | ADVERTISE_ALL;
+    emac_mii_write(priv, priv->phy_addr, MII_ADVERTISE, adv);
+    rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name);
+    emac_mii_write(priv, priv->phy_addr, MII_BMCR, (BMCR_ANENABLE
+                     | BMCR_ANRESTART));
 
-	for (i = 0; i < EMAC_AUTONEG_TIMEOUT / 100; i++) {
-		status = emac_mii_read(priv, priv->phy_addr, MII_BMSR);
-		if (status & BMSR_ANEGCOMPLETE)
-			break;
-		udelay(100);
-	}
+    for (i = 0; i < EMAC_AUTONEG_TIMEOUT / 100; i++) {
+        status = emac_mii_read(priv, priv->phy_addr, MII_BMSR);
+        if (status & BMSR_ANEGCOMPLETE)
+            break;
+        udelay(100);
+    }
 
-	if (status & BMSR_ANEGCOMPLETE)
-		rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name);
-	else
-		rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n",
-		       dev->parent.name, status);
+    if (status & BMSR_ANEGCOMPLETE)
+        rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name);
+    else
+        rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n",
+               dev->parent.name, status);
 }
 
 
 static int davinci_emac_phy_init(rt_device_t dev)
 {
-	struct emac_priv *priv = dev->user_data;
-	rt_uint16_t phy_id, status, adv, lpa;
-	int media, speed, duplex;
-	int i;
+    struct emac_priv *priv = dev->user_data;
+    rt_uint16_t phy_id, status, adv, lpa;
+    int media, speed, duplex;
+    int i;
 
-	/* Check if the PHY is up to snuff... */
-	phy_id = emac_mii_read(priv, priv->phy_addr, MII_PHYSID1);
-	if (phy_id == 0xffff) {
-		rt_kprintf("%s: No PHY present\n", dev->parent.name);
-		return 0;
-	}
+    /* Check if the PHY is up to snuff... */
+    phy_id = emac_mii_read(priv, priv->phy_addr, MII_PHYSID1);
+    if (phy_id == 0xffff) {
+        rt_kprintf("%s: No PHY present\n", dev->parent.name);
+        return 0;
+    }
 
-	status = emac_mii_read(priv, priv->phy_addr, MII_BMSR);
-	if (!(status & BMSR_LSTATUS)) {
-		/* Try to re-negotiate if we don't have link already. */
-		davinci_emac_phy_reset(dev);
+    status = emac_mii_read(priv, priv->phy_addr, MII_BMSR);
+    if (!(status & BMSR_LSTATUS)) {
+        /* Try to re-negotiate if we don't have link already. */
+        davinci_emac_phy_reset(dev);
 
-		for (i = 0; i < EMAC_LINK_TIMEOUT / 100; i++) {
-			status = emac_mii_read(priv, priv->phy_addr, MII_BMSR);
-			if (status & BMSR_LSTATUS)
-				break;
-			udelay(100);
-		}
-	}
+        for (i = 0; i < EMAC_LINK_TIMEOUT / 100; i++) {
+            status = emac_mii_read(priv, priv->phy_addr, MII_BMSR);
+            if (status & BMSR_LSTATUS)
+                break;
+            udelay(100);
+        }
+    }
 
-	if (!(status & BMSR_LSTATUS)) {
-		rt_kprintf("%s: link down (status: 0x%04x)\n",
-		       dev->parent.name, status);
-		priv->link = 0;
-		eth_device_linkchange(&priv->parent, RT_FALSE);
-		return 0;
-	} else {
-		adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE);
-		lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA);
-		media = mii_nway_result(lpa & adv);
-		speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
-			 ? 1 : 0);
-		duplex = (media & ADVERTISE_FULL) ? 1 : 0;
-		rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
-		       dev->parent.name,
-		       speed ? "100" : "10",
-		       duplex ? "full" : "half",
-		       lpa);
-		priv->speed = speed;
-		priv->duplex = duplex;
-		priv->link = 1;
-		eth_device_linkchange(&priv->parent, RT_TRUE);
+    if (!(status & BMSR_LSTATUS)) {
+        rt_kprintf("%s: link down (status: 0x%04x)\n",
+               dev->parent.name, status);
+        priv->link = 0;
+        eth_device_linkchange(&priv->parent, RT_FALSE);
+        return 0;
+    } else {
+        adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE);
+        lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA);
+        media = mii_nway_result(lpa & adv);
+        speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
+             ? 1 : 0);
+        duplex = (media & ADVERTISE_FULL) ? 1 : 0;
+        rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n",
+               dev->parent.name,
+               speed ? "100" : "10",
+               duplex ? "full" : "half",
+               lpa);
+        priv->speed = speed;
+        priv->duplex = duplex;
+        priv->link = 1;
+        eth_device_linkchange(&priv->parent, RT_TRUE);
 
-		return 1;
-	}
+        return 1;
+    }
 }
 
 /**
@@ -258,94 +258,94 @@ static int davinci_emac_phy_init(rt_device_t dev)
  */
 static void emac_update_phystatus(struct emac_priv *priv)
 {
-	rt_uint32_t mac_control;
-	rt_uint32_t new_duplex;
-	rt_uint32_t cur_duplex;
+    rt_uint32_t mac_control;
+    rt_uint32_t new_duplex;
+    rt_uint32_t cur_duplex;
 
-	mac_control = emac_read(EMAC_MACCONTROL);
-	cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
-			DUPLEX_FULL : DUPLEX_HALF;
-	if (priv->phy_mask)
-		new_duplex = priv->duplex;
-	else
-		new_duplex = DUPLEX_FULL;
+    mac_control = emac_read(EMAC_MACCONTROL);
+    cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ?
+            DUPLEX_FULL : DUPLEX_HALF;
+    if (priv->phy_mask)
+        new_duplex = priv->duplex;
+    else
+        new_duplex = DUPLEX_FULL;
 
-	/* We get called only if link has changed (speed/duplex/status) */
-	if ((priv->link) && (new_duplex != cur_duplex)) {
-		priv->duplex = new_duplex;
-		if (DUPLEX_FULL == priv->duplex)
-			mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
-		else
-			mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
-	}
+    /* We get called only if link has changed (speed/duplex/status) */
+    if ((priv->link) && (new_duplex != cur_duplex)) {
+        priv->duplex = new_duplex;
+        if (DUPLEX_FULL == priv->duplex)
+            mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN);
+        else
+            mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN);
+    }
 
-	if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
-		mac_control = emac_read(EMAC_MACCONTROL);
-		mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
-				EMAC_DM646X_MACCONTORL_GIGFORCE);
-	} else {
-		/* Clear the GIG bit and GIGFORCE bit */
-		mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
-					EMAC_DM646X_MACCONTORL_GIG);
+    if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) {
+        mac_control = emac_read(EMAC_MACCONTROL);
+        mac_control |= (EMAC_DM646X_MACCONTORL_GIG |
+                EMAC_DM646X_MACCONTORL_GIGFORCE);
+    } else {
+        /* Clear the GIG bit and GIGFORCE bit */
+        mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE |
+                    EMAC_DM646X_MACCONTORL_GIG);
 
-		if (priv->rmii_en && (priv->speed == SPEED_100))
-			mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
-		else
-			mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
-	}
+        if (priv->rmii_en && (priv->speed == SPEED_100))
+            mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK;
+        else
+            mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK;
+    }
 
-	/* Update mac_control if changed */
-	emac_write(EMAC_MACCONTROL, mac_control);
+    /* Update mac_control if changed */
+    emac_write(EMAC_MACCONTROL, mac_control);
 #if 0
-	if (priv->link) {
-		/* link ON */
-	/* reactivate the transmit queue if it is stopped */
-	} else {
-		/* link OFF */
-	}
+    if (priv->link) {
+        /* link ON */
+    /* reactivate the transmit queue if it is stopped */
+    } else {
+        /* link OFF */
+    }
 #endif
 }
 
 
 void davinci_emac_update_link(void *param)
 {
-	struct emac_priv *priv = param;
-	rt_device_t dev = &(priv->parent.parent);
-	rt_uint32_t status, status_change = 0;
-	rt_uint32_t link;
-	rt_uint32_t media;
-	rt_uint16_t adv, lpa;
+    struct emac_priv *priv = param;
+    rt_device_t dev = &(priv->parent.parent);
+    rt_uint32_t status, status_change = 0;
+    rt_uint32_t link;
+    rt_uint32_t media;
+    rt_uint16_t adv, lpa;
 
-	status = emac_mii_read(priv, priv->phy_addr, MII_BMSR);
-	if ((status & BMSR_LSTATUS) == 0)
-		link = 0;
-	else
-		link = 1;
+    status = emac_mii_read(priv, priv->phy_addr, MII_BMSR);
+    if ((status & BMSR_LSTATUS) == 0)
+        link = 0;
+    else
+        link = 1;
 
-	if (link != priv->link) {
-		priv->link = link;
-		status_change = 1;
-	}
+    if (link != priv->link) {
+        priv->link = link;
+        status_change = 1;
+    }
 
-	if (status_change) {
-		if (priv->link) {
-			adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE);
-			lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA);
-			media = mii_nway_result(lpa & adv);
-			priv->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
-				 ? 100 : 10);
-			priv->duplex = (media & ADVERTISE_FULL) ? 1 : 0;
-			rt_kprintf("%s: link up (%dMbps/%s-duplex)\n",
-					dev->parent.name, priv->speed,
-					DUPLEX_FULL == priv->duplex ? "Full":"Half");
-			eth_device_linkchange(&priv->parent, RT_TRUE);
-		} else {
-			rt_kprintf("%s: link down\n", dev->parent.name);
-			eth_device_linkchange(&priv->parent, RT_FALSE);
-		}
-		emac_update_phystatus(priv);
+    if (status_change) {
+        if (priv->link) {
+            adv = emac_mii_read(priv, priv->phy_addr, MII_ADVERTISE);
+            lpa = emac_mii_read(priv, priv->phy_addr, MII_LPA);
+            media = mii_nway_result(lpa & adv);
+            priv->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)
+                 ? 100 : 10);
+            priv->duplex = (media & ADVERTISE_FULL) ? 1 : 0;
+            rt_kprintf("%s: link up (%dMbps/%s-duplex)\n",
+                    dev->parent.name, priv->speed,
+                    DUPLEX_FULL == priv->duplex ? "Full":"Half");
+            eth_device_linkchange(&priv->parent, RT_TRUE);
+        } else {
+            rt_kprintf("%s: link down\n", dev->parent.name);
+            eth_device_linkchange(&priv->parent, RT_FALSE);
+        }
+        emac_update_phystatus(priv);
 
-	}
+    }
 
 }
 
@@ -361,21 +361,21 @@ void davinci_emac_update_link(void *param)
  *
  */
 static int emac_net_tx_complete(struct emac_priv *priv,
-				void **net_data_tokens,
-				int num_tokens, rt_uint32_t ch)
+                void **net_data_tokens,
+                int num_tokens, rt_uint32_t ch)
 {
-	rt_uint32_t cnt;
+    rt_uint32_t cnt;
 
-	for (cnt = 0; cnt < num_tokens; cnt++) {
-		struct pbuf *p = (struct pbuf *)net_data_tokens[cnt];
-		if (p == RT_NULL)
-			continue;
-		priv->net_dev_stats.tx_packets++;
-		priv->net_dev_stats.tx_bytes += p->len;
-		//free pbuf
-	}
+    for (cnt = 0; cnt < num_tokens; cnt++) {
+        struct pbuf *p = (struct pbuf *)net_data_tokens[cnt];
+        if (p == RT_NULL)
+            continue;
+        priv->net_dev_stats.tx_packets++;
+        priv->net_dev_stats.tx_bytes += p->len;
+        //free pbuf
+    }
 
-	return 0;
+    return 0;
 }
 
 /**
@@ -388,36 +388,36 @@ static int emac_net_tx_complete(struct emac_priv *priv,
  */
 static void emac_txch_teardown(struct emac_priv *priv, rt_uint32_t ch)
 {
-	rt_uint32_t teardown_cnt = 0xFFFFFFF0; /* Some high value */
-	struct emac_txch *txch = priv->txch[ch];
-	struct emac_tx_bd __iomem *curr_bd;
+    rt_uint32_t teardown_cnt = 0xFFFFFFF0; /* Some high value */
+    struct emac_txch *txch = priv->txch[ch];
+    struct emac_tx_bd __iomem *curr_bd;
 
-	while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
-	       EMAC_TEARDOWN_VALUE) {
-		/* wait till tx teardown complete */
-		--teardown_cnt;
-		if (0 == teardown_cnt) {
-			rt_kprintf("EMAC: TX teardown aborted\n");
-			break;
-		}
-	}
-	emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
+    while ((emac_read(EMAC_TXCP(ch)) & EMAC_TEARDOWN_VALUE) !=
+           EMAC_TEARDOWN_VALUE) {
+        /* wait till tx teardown complete */
+        --teardown_cnt;
+        if (0 == teardown_cnt) {
+            rt_kprintf("EMAC: TX teardown aborted\n");
+            break;
+        }
+    }
+    emac_write(EMAC_TXCP(ch), EMAC_TEARDOWN_VALUE);
 
-	/* process sent packets and return pbuf's to upper layer */
-	if (1 == txch->queue_active) {
-		curr_bd = txch->active_queue_head;
-		while (curr_bd != RT_NULL) {
-			emac_net_tx_complete(priv, (void *)
-					&curr_bd->buf_token, 1, ch);
-			if (curr_bd != txch->active_queue_tail)
-				curr_bd = curr_bd->next;
-			else
-				break;
-		}
-		txch->bd_pool_head = txch->active_queue_head;
-		txch->active_queue_head =
-		txch->active_queue_tail = RT_NULL;
-	}
+    /* process sent packets and return pbuf's to upper layer */
+    if (1 == txch->queue_active) {
+        curr_bd = txch->active_queue_head;
+        while (curr_bd != RT_NULL) {
+            emac_net_tx_complete(priv, (void *)
+                    &curr_bd->buf_token, 1, ch);
+            if (curr_bd != txch->active_queue_tail)
+                curr_bd = curr_bd->next;
+            else
+                break;
+        }
+        txch->bd_pool_head = txch->active_queue_head;
+        txch->active_queue_head =
+        txch->active_queue_tail = RT_NULL;
+    }
 }
 
 
@@ -431,15 +431,15 @@ static void emac_txch_teardown(struct emac_priv *priv, rt_uint32_t ch)
  */
 static void emac_stop_txch(struct emac_priv *priv, rt_uint32_t ch)
 {
-	struct emac_txch *txch = priv->txch[ch];
+    struct emac_txch *txch = priv->txch[ch];
 
-	if (txch) {
-		txch->teardown_pending = 1;
-		emac_write(EMAC_TXTEARDOWN, 0);
-		emac_txch_teardown(priv, ch);
-		txch->teardown_pending = 0;
-		emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
-	}
+    if (txch) {
+        txch->teardown_pending = 1;
+        emac_write(EMAC_TXTEARDOWN, 0);
+        emac_txch_teardown(priv, ch);
+        txch->teardown_pending = 0;
+        emac_write(EMAC_TXINTMASKCLEAR, BIT(ch));
+    }
 }
 
 
@@ -460,65 +460,65 @@ static void emac_stop_txch(struct emac_priv *priv, rt_uint32_t ch)
  */
 static int emac_tx_bdproc(struct emac_priv *priv, rt_uint32_t ch, rt_uint32_t budget)
 {
-	unsigned long flags;
-	rt_uint32_t frame_status;
-	rt_uint32_t pkts_processed = 0;
-	rt_uint32_t tx_complete_cnt = 0;
-	struct emac_tx_bd __iomem *curr_bd;
-	struct emac_txch *txch = priv->txch[ch];
-	rt_uint32_t *tx_complete_ptr = txch->tx_complete;
+    unsigned long flags;
+    rt_uint32_t frame_status;
+    rt_uint32_t pkts_processed = 0;
+    rt_uint32_t tx_complete_cnt = 0;
+    struct emac_tx_bd __iomem *curr_bd;
+    struct emac_txch *txch = priv->txch[ch];
+    rt_uint32_t *tx_complete_ptr = txch->tx_complete;
 
-	if (1 == txch->teardown_pending) {
-		rt_kprintf("DaVinci EMAC:emac_tx_bdproc: "\
-				"teardown pending\n");
-		return 0;  /* dont handle any pkt completions */
-	}
+    if (1 == txch->teardown_pending) {
+        rt_kprintf("DaVinci EMAC:emac_tx_bdproc: "\
+                "teardown pending\n");
+        return 0;  /* dont handle any pkt completions */
+    }
 
-	++txch->proc_count;
-	rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER);
-	curr_bd = txch->active_queue_head;
-	if (RT_NULL == curr_bd) {
-		emac_write(EMAC_TXCP(ch),
-			   emac_virt_to_phys(txch->last_hw_bdprocessed));
-		txch->no_active_pkts++;
-		rt_sem_release(&priv->tx_lock);
-		return 0;
-	}
-	BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
-	frame_status = curr_bd->mode;
-	while ((curr_bd) &&
-	      ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
-	      (pkts_processed < budget)) {
-		emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd));
-		txch->active_queue_head = curr_bd->next;
-		if (frame_status & EMAC_CPPI_EOQ_BIT) {
-			if (curr_bd->next) {	/* misqueued packet */
-				emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
-				++txch->mis_queued_packets;
-			} else {
-				txch->queue_active = 0; /* end of queue */
-			}
-		}
-		*tx_complete_ptr = (rt_uint32_t) curr_bd->buf_token;
-		++tx_complete_ptr;
-		++tx_complete_cnt;
-		curr_bd->next = txch->bd_pool_head;
-		txch->bd_pool_head = curr_bd;
-		--txch->active_queue_count;
-		pkts_processed++;
-		txch->last_hw_bdprocessed = curr_bd;
-		curr_bd = txch->active_queue_head;
-		if (curr_bd) {
-			BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
-			frame_status = curr_bd->mode;
-		}
-	} /* end of pkt processing loop */
+    ++txch->proc_count;
+    rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER);
+    curr_bd = txch->active_queue_head;
+    if (RT_NULL == curr_bd) {
+        emac_write(EMAC_TXCP(ch),
+               emac_virt_to_phys(txch->last_hw_bdprocessed));
+        txch->no_active_pkts++;
+        rt_sem_release(&priv->tx_lock);
+        return 0;
+    }
+    BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
+    frame_status = curr_bd->mode;
+    while ((curr_bd) &&
+          ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
+          (pkts_processed < budget)) {
+        emac_write(EMAC_TXCP(ch), emac_virt_to_phys(curr_bd));
+        txch->active_queue_head = curr_bd->next;
+        if (frame_status & EMAC_CPPI_EOQ_BIT) {
+            if (curr_bd->next) {    /* misqueued packet */
+                emac_write(EMAC_TXHDP(ch), curr_bd->h_next);
+                ++txch->mis_queued_packets;
+            } else {
+                txch->queue_active = 0; /* end of queue */
+            }
+        }
+        *tx_complete_ptr = (rt_uint32_t) curr_bd->buf_token;
+        ++tx_complete_ptr;
+        ++tx_complete_cnt;
+        curr_bd->next = txch->bd_pool_head;
+        txch->bd_pool_head = curr_bd;
+        --txch->active_queue_count;
+        pkts_processed++;
+        txch->last_hw_bdprocessed = curr_bd;
+        curr_bd = txch->active_queue_head;
+        if (curr_bd) {
+            BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
+            frame_status = curr_bd->mode;
+        }
+    } /* end of pkt processing loop */
 
-	emac_net_tx_complete(priv,
-			     (void *)&txch->tx_complete[0],
-			     tx_complete_cnt, ch);
-	rt_sem_release(&priv->tx_lock);
-	return pkts_processed;
+    emac_net_tx_complete(priv,
+                 (void *)&txch->tx_complete[0],
+                 tx_complete_cnt, ch);
+    rt_sem_release(&priv->tx_lock);
+    return pkts_processed;
 }
 
 
@@ -536,81 +536,81 @@ static int emac_tx_bdproc(struct emac_priv *priv, rt_uint32_t ch, rt_uint32_t bu
  */
 static int emac_send(struct emac_priv *priv, struct emac_netpktobj *pkt, rt_uint32_t ch)
 {
-	unsigned long flags;
-	struct emac_tx_bd __iomem *curr_bd;
-	struct emac_txch *txch;
-	struct emac_netbufobj *buf_list;
-	rt_uint32_t num_pkts = 0;
-	int retry = 0;
+    unsigned long flags;
+    struct emac_tx_bd __iomem *curr_bd;
+    struct emac_txch *txch;
+    struct emac_netbufobj *buf_list;
+    rt_uint32_t num_pkts = 0;
+    int retry = 0;
 
-	txch = priv->txch[ch];
-	buf_list = pkt->buf_list;   /* get handle to the buffer array */
+    txch = priv->txch[ch];
+    buf_list = pkt->buf_list;   /* get handle to the buffer array */
 
-	/* check packet size and pad if short */
-	if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) {
-		buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length);
-		pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE;
-	}
+    /* check packet size and pad if short */
+    if (pkt->pkt_length < EMAC_DEF_MIN_ETHPKTSIZE) {
+        buf_list->length += (EMAC_DEF_MIN_ETHPKTSIZE - pkt->pkt_length);
+        pkt->pkt_length = EMAC_DEF_MIN_ETHPKTSIZE;
+    }
 
 try:
-	rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER);
-	curr_bd = txch->bd_pool_head;
-	if (curr_bd == RT_NULL) {
-		txch->out_of_tx_bd++;
-		rt_sem_release(&priv->tx_lock);
-		num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
-					  EMAC_DEF_TX_MAX_SERVICE);
-		if (!num_pkts) {
-			retry++;
-			if (retry > 5)
-				return EMAC_ERR_TX_OUT_OF_BD;
-			rt_thread_delay(1);
-		}
-		goto try;
-	}
+    rt_sem_take(&priv->tx_lock, RT_WAITING_FOREVER);
+    curr_bd = txch->bd_pool_head;
+    if (curr_bd == RT_NULL) {
+        txch->out_of_tx_bd++;
+        rt_sem_release(&priv->tx_lock);
+        num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
+                      EMAC_DEF_TX_MAX_SERVICE);
+        if (!num_pkts) {
+            retry++;
+            if (retry > 5)
+                return EMAC_ERR_TX_OUT_OF_BD;
+            rt_thread_delay(1);
+        }
+        goto try;
+    }
 
-	txch->bd_pool_head = curr_bd->next;
-	curr_bd->buf_token = buf_list->buf_token;
-	curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr);
-	curr_bd->off_b_len = buf_list->length;
-	curr_bd->h_next = 0;
-	curr_bd->next = RT_NULL;
-	curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT |
-			 EMAC_CPPI_EOP_BIT | pkt->pkt_length);
+    txch->bd_pool_head = curr_bd->next;
+    curr_bd->buf_token = buf_list->buf_token;
+    curr_bd->buff_ptr = virt_to_phys(buf_list->data_ptr);
+    curr_bd->off_b_len = buf_list->length;
+    curr_bd->h_next = 0;
+    curr_bd->next = RT_NULL;
+    curr_bd->mode = (EMAC_CPPI_SOP_BIT | EMAC_CPPI_OWNERSHIP_BIT |
+             EMAC_CPPI_EOP_BIT | pkt->pkt_length);
 
-	/* flush the packet from cache if write back cache is present */
-	BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
+    /* flush the packet from cache if write back cache is present */
+    BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
 
-	/* send the packet */
-	if (txch->active_queue_head == RT_NULL) {
-		txch->active_queue_head = curr_bd;
-		txch->active_queue_tail = curr_bd;
-		if (1 != txch->queue_active) {
-			emac_write(EMAC_TXHDP(ch),
-					emac_virt_to_phys(curr_bd));
-			txch->queue_active = 1;
-		}
-		++txch->queue_reinit;
-	} else {
-		register struct emac_tx_bd __iomem *tail_bd;
-		register rt_uint32_t frame_status;
+    /* send the packet */
+    if (txch->active_queue_head == RT_NULL) {
+        txch->active_queue_head = curr_bd;
+        txch->active_queue_tail = curr_bd;
+        if (1 != txch->queue_active) {
+            emac_write(EMAC_TXHDP(ch),
+                    emac_virt_to_phys(curr_bd));
+            txch->queue_active = 1;
+        }
+        ++txch->queue_reinit;
+    } else {
+        register struct emac_tx_bd __iomem *tail_bd;
+        register rt_uint32_t frame_status;
 
-		tail_bd = txch->active_queue_tail;
-		tail_bd->next = curr_bd;
-		txch->active_queue_tail = curr_bd;
-		tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
-		tail_bd->h_next = (int)emac_virt_to_phys(curr_bd);
-		frame_status = tail_bd->mode;
-		if (frame_status & EMAC_CPPI_EOQ_BIT) {
-			emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd));
-			frame_status &= ~(EMAC_CPPI_EOQ_BIT);
-			tail_bd->mode = frame_status;
-			++txch->end_of_queue_add;
-		}
-	}
-	txch->active_queue_count++;
-	rt_sem_release(&priv->tx_lock);
-	return 0;
+        tail_bd = txch->active_queue_tail;
+        tail_bd->next = curr_bd;
+        txch->active_queue_tail = curr_bd;
+        tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
+        tail_bd->h_next = (int)emac_virt_to_phys(curr_bd);
+        frame_status = tail_bd->mode;
+        if (frame_status & EMAC_CPPI_EOQ_BIT) {
+            emac_write(EMAC_TXHDP(ch), emac_virt_to_phys(curr_bd));
+            frame_status &= ~(EMAC_CPPI_EOQ_BIT);
+            tail_bd->mode = frame_status;
+            ++txch->end_of_queue_add;
+        }
+    }
+    txch->active_queue_count++;
+    rt_sem_release(&priv->tx_lock);
+    return 0;
 }
 
 /**
@@ -625,40 +625,40 @@ try:
  */
 static int emac_dev_xmit(struct pbuf *p, struct emac_priv *priv)
 {
-	int ret_code;
-	struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
-	struct emac_netpktobj tx_packet;  /* packet object */
+    int ret_code;
+    struct emac_netbufobj tx_buf; /* buffer obj-only single frame support */
+    struct emac_netpktobj tx_packet;  /* packet object */
 
-	/* If no link, return */
-	if (!priv->link) {
-			rt_kprintf("DaVinci EMAC: No link to transmit\n");
-		return -RT_EBUSY;
-	}
+    /* If no link, return */
+    if (!priv->link) {
+            rt_kprintf("DaVinci EMAC: No link to transmit\n");
+        return -RT_EBUSY;
+    }
 
-	/* Build the buffer and packet objects - Since only single fragment is
-	 * supported, need not set length and token in both packet & object.
-	 * Doing so for completeness sake & to show that this needs to be done
-	 * in multifragment case
-	 */
-	tx_packet.buf_list = &tx_buf;
-	tx_packet.num_bufs = 1; /* only single fragment supported */
-	tx_packet.pkt_length = p->len;
-	tx_packet.pkt_token = (void *)p;
-	tx_buf.length = p->len;
-	tx_buf.buf_token = (void *)p;
-	tx_buf.data_ptr = p->payload;
-	EMAC_CACHE_WRITEBACK((unsigned long)p->payload, p->len);
-	ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
-	if (ret_code != 0) {
-		if (ret_code == EMAC_ERR_TX_OUT_OF_BD) {
-			rt_kprintf("DaVinci EMAC: xmit() fatal"\
-					" err. Out of TX BD's\n");
-		}
-		priv->net_dev_stats.tx_dropped++;
-		return -RT_EBUSY;
-	}
+    /* Build the buffer and packet objects - Since only single fragment is
+     * supported, need not set length and token in both packet & object.
+     * Doing so for completeness sake & to show that this needs to be done
+     * in multifragment case
+     */
+    tx_packet.buf_list = &tx_buf;
+    tx_packet.num_bufs = 1; /* only single fragment supported */
+    tx_packet.pkt_length = p->len;
+    tx_packet.pkt_token = (void *)p;
+    tx_buf.length = p->len;
+    tx_buf.buf_token = (void *)p;
+    tx_buf.data_ptr = p->payload;
+    EMAC_CACHE_WRITEBACK((unsigned long)p->payload, p->len);
+    ret_code = emac_send(priv, &tx_packet, EMAC_DEF_TX_CH);
+    if (ret_code != 0) {
+        if (ret_code == EMAC_ERR_TX_OUT_OF_BD) {
+            rt_kprintf("DaVinci EMAC: xmit() fatal"\
+                    " err. Out of TX BD's\n");
+        }
+        priv->net_dev_stats.tx_dropped++;
+        return -RT_EBUSY;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /**
@@ -671,15 +671,15 @@ static int emac_dev_xmit(struct pbuf *p, struct emac_priv *priv)
  */
 static void emac_cleanup_txch(struct emac_priv *priv, rt_uint32_t ch)
 {
-	struct emac_txch *txch = priv->txch[ch];
+    struct emac_txch *txch = priv->txch[ch];
 
-	if (txch) {
-		if (txch->bd_mem)
-			txch->bd_mem = NULL;
-		rt_free(txch->tx_complete);
-		rt_free(txch);
-		priv->txch[ch] = NULL;
-	}
+    if (txch) {
+        if (txch->bd_mem)
+            txch->bd_mem = NULL;
+        rt_free(txch->tx_complete);
+        rt_free(txch);
+        priv->txch[ch] = NULL;
+    }
 }
 
 
@@ -695,15 +695,15 @@ static void emac_cleanup_txch(struct emac_priv *priv, rt_uint32_t ch)
  */
 static void emac_dev_tx_timeout(struct emac_priv *priv)
 {
-	rt_kprintf("emac tx timeout.\n");
-	priv->net_dev_stats.tx_errors++;
-	emac_int_disable(priv);
-	emac_stop_txch(priv, EMAC_DEF_TX_CH);
-	emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
-	emac_init_txch(priv, EMAC_DEF_TX_CH);
-	emac_write(EMAC_TXHDP(0), 0);
-	emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
-	emac_int_enable(priv);
+    rt_kprintf("emac tx timeout.\n");
+    priv->net_dev_stats.tx_errors++;
+    emac_int_disable(priv);
+    emac_stop_txch(priv, EMAC_DEF_TX_CH);
+    emac_cleanup_txch(priv, EMAC_DEF_TX_CH);
+    emac_init_txch(priv, EMAC_DEF_TX_CH);
+    emac_write(EMAC_TXHDP(0), 0);
+    emac_write(EMAC_TXINTMASKSET, BIT(EMAC_DEF_TX_CH));
+    emac_int_enable(priv);
 }
 
 
@@ -711,16 +711,16 @@ static void emac_dev_tx_timeout(struct emac_priv *priv)
 /* transmit packet. */
 rt_err_t rt_davinci_emac_tx( rt_device_t dev, struct pbuf* p)
 {
-	rt_err_t err;
-	struct emac_priv *priv = dev->user_data;
+    rt_err_t err;
+    struct emac_priv *priv = dev->user_data;
 
-	err = emac_dev_xmit(p, priv);
-	if (err != RT_EOK)
-	{
-		emac_dev_tx_timeout(priv);
-	}
+    err = emac_dev_xmit(p, priv);
+    if (err != RT_EOK)
+    {
+        emac_dev_tx_timeout(priv);
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /**
@@ -737,49 +737,49 @@ rt_err_t rt_davinci_emac_tx( rt_device_t dev, struct pbuf* p)
  *
  */
 static void emac_addbd_to_rx_queue(struct emac_priv *priv, rt_uint32_t ch,
-		struct emac_rx_bd __iomem *curr_bd,
-		char *buffer, void *buf_token)
+        struct emac_rx_bd __iomem *curr_bd,
+        char *buffer, void *buf_token)
 {
-	struct emac_rxch *rxch = priv->rxch[ch];
+    struct emac_rxch *rxch = priv->rxch[ch];
 
-	/* populate the hardware descriptor */
-	curr_bd->h_next = 0;
-	curr_bd->buff_ptr = virt_to_phys(buffer);
-	curr_bd->off_b_len = rxch->buf_size;
-	curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
-	curr_bd->next = RT_NULL;
-	curr_bd->data_ptr = buffer;
-	curr_bd->buf_token = buf_token;
+    /* populate the hardware descriptor */
+    curr_bd->h_next = 0;
+    curr_bd->buff_ptr = virt_to_phys(buffer);
+    curr_bd->off_b_len = rxch->buf_size;
+    curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
+    curr_bd->next = RT_NULL;
+    curr_bd->data_ptr = buffer;
+    curr_bd->buf_token = buf_token;
 
-	/* write back  */
-	BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
-	if (rxch->active_queue_head == RT_NULL) {
-		rxch->active_queue_head = curr_bd;
-		rxch->active_queue_tail = curr_bd;
-		if (0 != rxch->queue_active) {
-			emac_write(EMAC_RXHDP(ch),
-				   emac_virt_to_phys(rxch->active_queue_head));
-			rxch->queue_active = 1;
-		}
-	} else {
-		struct emac_rx_bd __iomem *tail_bd;
-		rt_uint32_t frame_status;
+    /* write back  */
+    BD_CACHE_WRITEBACK_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
+    if (rxch->active_queue_head == RT_NULL) {
+        rxch->active_queue_head = curr_bd;
+        rxch->active_queue_tail = curr_bd;
+        if (0 != rxch->queue_active) {
+            emac_write(EMAC_RXHDP(ch),
+                   emac_virt_to_phys(rxch->active_queue_head));
+            rxch->queue_active = 1;
+        }
+    } else {
+        struct emac_rx_bd __iomem *tail_bd;
+        rt_uint32_t frame_status;
 
-		tail_bd = rxch->active_queue_tail;
-		rxch->active_queue_tail = curr_bd;
-		tail_bd->next = curr_bd;
-		tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
-		tail_bd->h_next = emac_virt_to_phys(curr_bd);
-		frame_status = tail_bd->mode;
-		if (frame_status & EMAC_CPPI_EOQ_BIT) {
-			emac_write(EMAC_RXHDP(ch),
-					emac_virt_to_phys(curr_bd));
-			frame_status &= ~(EMAC_CPPI_EOQ_BIT);
-			tail_bd->mode = frame_status;
-			++rxch->end_of_queue_add;
-		}
-	}
-	++rxch->recycled_bd;
+        tail_bd = rxch->active_queue_tail;
+        rxch->active_queue_tail = curr_bd;
+        tail_bd->next = curr_bd;
+        tail_bd = EMAC_VIRT_NOCACHE(tail_bd);
+        tail_bd->h_next = emac_virt_to_phys(curr_bd);
+        frame_status = tail_bd->mode;
+        if (frame_status & EMAC_CPPI_EOQ_BIT) {
+            emac_write(EMAC_RXHDP(ch),
+                    emac_virt_to_phys(curr_bd));
+            frame_status &= ~(EMAC_CPPI_EOQ_BIT);
+            tail_bd->mode = frame_status;
+            ++rxch->end_of_queue_add;
+        }
+    }
+    ++rxch->recycled_bd;
 }
 
 /**
@@ -793,22 +793,22 @@ static void emac_addbd_to_rx_queue(struct emac_priv *priv, rt_uint32_t ch,
  * Returns success or appropriate error code (none as of now)
  */
 static int emac_net_rx_cb(struct emac_priv *priv,
-			  struct emac_netpktobj *net_pkt_list)
+              struct emac_netpktobj *net_pkt_list)
 {
-	struct eth_device *device = &priv->parent;
-	struct pbuf *p;
-	p = (struct pbuf *)net_pkt_list->pkt_token;
-	/* set length of packet */
-	p->tot_len = net_pkt_list->pkt_length;
-	p->len = net_pkt_list->pkt_length;
-	EMAC_CACHE_INVALIDATE((unsigned long)p->payload, p->len);
-	if (device->netif->input(p, device->netif) != RT_EOK)
-	{
-		pbuf_free(p);
-	}
-	priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length;
-	priv->net_dev_stats.rx_packets++;
-	return 0;
+    struct eth_device *device = &priv->parent;
+    struct pbuf *p;
+    p = (struct pbuf *)net_pkt_list->pkt_token;
+    /* set length of packet */
+    p->tot_len = net_pkt_list->pkt_length;
+    p->len = net_pkt_list->pkt_length;
+    EMAC_CACHE_INVALIDATE((unsigned long)p->payload, p->len);
+    if (device->netif->input(p, device->netif) != RT_EOK)
+    {
+        pbuf_free(p);
+    }
+    priv->net_dev_stats.rx_bytes += net_pkt_list->pkt_length;
+    priv->net_dev_stats.rx_packets++;
+    return 0;
 }
 
 /**
@@ -824,20 +824,20 @@ static int emac_net_rx_cb(struct emac_priv *priv,
  * Returns pbuf data pointer or 0 on failure to alloc pbuf
  */
 static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
-		void **data_token, rt_uint32_t ch)
+        void **data_token, rt_uint32_t ch)
 {
-	struct pbuf* p;
+    struct pbuf* p;
 
-	p = pbuf_alloc(PBUF_LINK, buf_size, PBUF_RAM);
-	if (RT_NULL == p) {
-		rt_kprintf("DaVinci EMAC: failed to alloc pbuf\n");
-		return RT_NULL;
-	}
+    p = pbuf_alloc(PBUF_LINK, buf_size, PBUF_RAM);
+    if (RT_NULL == p) {
+        rt_kprintf("DaVinci EMAC: failed to alloc pbuf\n");
+        return RT_NULL;
+    }
 
-	/* set device pointer in p and reserve space for extra bytes */
-	*data_token = (void *) p;
-	EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p->payload, buf_size);
-	return p->payload;
+    /* set device pointer in p and reserve space for extra bytes */
+    *data_token = (void *) p;
+    EMAC_CACHE_WRITEBACK_INVALIDATE((unsigned long)p->payload, buf_size);
+    return p->payload;
 }
 
 
@@ -857,160 +857,160 @@ static void *emac_net_alloc_rx_buf(struct emac_priv *priv, int buf_size,
  */
 static int emac_rx_bdproc(struct emac_priv *priv, rt_uint32_t ch, rt_uint32_t budget)
 {
-	unsigned long flags;
-	rt_uint32_t frame_status;
-	rt_uint32_t pkts_processed = 0;
-	char *new_buffer;
-	struct emac_rx_bd __iomem *curr_bd;
-	struct emac_rx_bd __iomem *last_bd;
-	struct emac_netpktobj *curr_pkt, pkt_obj;
-	struct emac_netbufobj buf_obj;
-	struct emac_netbufobj *rx_buf_obj;
-	void *new_buf_token;
-	struct emac_rxch *rxch = priv->rxch[ch];
+    unsigned long flags;
+    rt_uint32_t frame_status;
+    rt_uint32_t pkts_processed = 0;
+    char *new_buffer;
+    struct emac_rx_bd __iomem *curr_bd;
+    struct emac_rx_bd __iomem *last_bd;
+    struct emac_netpktobj *curr_pkt, pkt_obj;
+    struct emac_netbufobj buf_obj;
+    struct emac_netbufobj *rx_buf_obj;
+    void *new_buf_token;
+    struct emac_rxch *rxch = priv->rxch[ch];
 
-	if (1 == rxch->teardown_pending)
-		return 0;
-	++rxch->proc_count;
-	rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER);
-	pkt_obj.buf_list = &buf_obj;
-	curr_pkt = &pkt_obj;
-	curr_bd = rxch->active_queue_head;
-	BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
-	frame_status = curr_bd->mode;
+    if (1 == rxch->teardown_pending)
+        return 0;
+    ++rxch->proc_count;
+    rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER);
+    pkt_obj.buf_list = &buf_obj;
+    curr_pkt = &pkt_obj;
+    curr_bd = rxch->active_queue_head;
+    BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
+    frame_status = curr_bd->mode;
 
-	while ((curr_bd) &&
-	       ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
-	       (pkts_processed < budget)) {
+    while ((curr_bd) &&
+           ((frame_status & EMAC_CPPI_OWNERSHIP_BIT) == 0) &&
+           (pkts_processed < budget)) {
 
-		new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
-					&new_buf_token, EMAC_DEF_RX_CH);
-		if (RT_NULL == new_buffer) {
-			++rxch->out_of_rx_buffers;
-			goto end_emac_rx_bdproc;
-		}
+        new_buffer = emac_net_alloc_rx_buf(priv, rxch->buf_size,
+                    &new_buf_token, EMAC_DEF_RX_CH);
+        if (RT_NULL == new_buffer) {
+            ++rxch->out_of_rx_buffers;
+            goto end_emac_rx_bdproc;
+        }
 
-		/* populate received packet data structure */
-		rx_buf_obj = &curr_pkt->buf_list[0];
-		rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
-		rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
-		rx_buf_obj->buf_token = curr_bd->buf_token;
-		curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
-		curr_pkt->num_bufs = 1;
-		curr_pkt->pkt_length =
-			(frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
-		emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd));
-		++rxch->processed_bd;
-		last_bd = curr_bd;
-		curr_bd = last_bd->next;
-		rxch->active_queue_head = curr_bd;
+        /* populate received packet data structure */
+        rx_buf_obj = &curr_pkt->buf_list[0];
+        rx_buf_obj->data_ptr = (char *)curr_bd->data_ptr;
+        rx_buf_obj->length = curr_bd->off_b_len & EMAC_RX_BD_BUF_SIZE;
+        rx_buf_obj->buf_token = curr_bd->buf_token;
+        curr_pkt->pkt_token = curr_pkt->buf_list->buf_token;
+        curr_pkt->num_bufs = 1;
+        curr_pkt->pkt_length =
+            (frame_status & EMAC_RX_BD_PKT_LENGTH_MASK);
+        emac_write(EMAC_RXCP(ch), emac_virt_to_phys(curr_bd));
+        ++rxch->processed_bd;
+        last_bd = curr_bd;
+        curr_bd = last_bd->next;
+        rxch->active_queue_head = curr_bd;
 
-		/* check if end of RX queue ? */
-		if (frame_status & EMAC_CPPI_EOQ_BIT) {
-			if (curr_bd) {
-				++rxch->mis_queued_packets;
-				emac_write(EMAC_RXHDP(ch),
-					   emac_virt_to_phys(curr_bd));
-			} else {
-				++rxch->end_of_queue;
-				rxch->queue_active = 0;
-			}
-		}
+        /* check if end of RX queue ? */
+        if (frame_status & EMAC_CPPI_EOQ_BIT) {
+            if (curr_bd) {
+                ++rxch->mis_queued_packets;
+                emac_write(EMAC_RXHDP(ch),
+                       emac_virt_to_phys(curr_bd));
+            } else {
+                ++rxch->end_of_queue;
+                rxch->queue_active = 0;
+            }
+        }
 
-		/* recycle BD */
-		emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
-				       new_buf_token);
+        /* recycle BD */
+        emac_addbd_to_rx_queue(priv, ch, last_bd, new_buffer,
+                       new_buf_token);
 
-		/* return the packet to the user - BD ptr passed in
-		 * last parameter for potential *future* use */
-		rt_sem_release(&priv->rx_lock);
-		emac_net_rx_cb(priv, curr_pkt);//???
-		rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER);
-		curr_bd = rxch->active_queue_head;
-		if (curr_bd) {
-			BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
-			frame_status = curr_bd->mode;
-		}
-		++pkts_processed;
-	}
+        /* return the packet to the user - BD ptr passed in
+         * last parameter for potential *future* use */
+        rt_sem_release(&priv->rx_lock);
+        emac_net_rx_cb(priv, curr_pkt);//???
+        rt_sem_take(&priv->rx_lock, RT_WAITING_FOREVER);
+        curr_bd = rxch->active_queue_head;
+        if (curr_bd) {
+            BD_CACHE_INVALIDATE(curr_bd, EMAC_BD_LENGTH_FOR_CACHE);
+            frame_status = curr_bd->mode;
+        }
+        ++pkts_processed;
+    }
 
 end_emac_rx_bdproc:
-	rt_sem_release(&priv->rx_lock);
-	return pkts_processed;
+    rt_sem_release(&priv->rx_lock);
+    return pkts_processed;
 }
 
 
 /* reception packet. */
 struct pbuf *rt_davinci_emac_rx(rt_device_t dev)
 {
-	struct emac_priv *priv = dev->user_data;
-	struct pbuf* p = RT_NULL;
-	rt_uint32_t len;
-	void *buffer;
+    struct emac_priv *priv = dev->user_data;
+    struct pbuf* p = RT_NULL;
+    rt_uint32_t len;
+    void *buffer;
 
-	struct pbuf* q;
-	rt_uint8_t *buf = RT_NULL;
-	unsigned int mask;
-	rt_uint32_t status = 0;
-	rt_uint32_t num_pkts = 0;
+    struct pbuf* q;
+    rt_uint8_t *buf = RT_NULL;
+    unsigned int mask;
+    rt_uint32_t status = 0;
+    rt_uint32_t num_pkts = 0;
 
-	/* Check interrupt vectors and call packet processing */
-	status = emac_read(EMAC_MACINVECTOR);
+    /* Check interrupt vectors and call packet processing */
+    status = emac_read(EMAC_MACINVECTOR);
 
-	mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
+    mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC;
 
-	if (priv->version == EMAC_VERSION_2)
-		mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
+    if (priv->version == EMAC_VERSION_2)
+        mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC;
 
-	if (status & mask) {
-		num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
-					  EMAC_DEF_TX_MAX_SERVICE);
-	} /* TX processing */
+    if (status & mask) {
+        num_pkts = emac_tx_bdproc(priv, EMAC_DEF_TX_CH,
+                      EMAC_DEF_TX_MAX_SERVICE);
+    } /* TX processing */
 
-	/*if (num_pkts)
-		//return budget;
-		return RT_NULL;*/
+    /*if (num_pkts)
+        //return budget;
+        return RT_NULL;*/
 
-	mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
+    mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC;
 
-	if (priv->version == EMAC_VERSION_2)
-		mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
+    if (priv->version == EMAC_VERSION_2)
+        mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC;
 
-	if (status & mask) {
-		num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, EMAC_DEF_RX_MAX_SERVICE);
-	} /* RX processing */
+    if (status & mask) {
+        num_pkts = emac_rx_bdproc(priv, EMAC_DEF_RX_CH, EMAC_DEF_RX_MAX_SERVICE);
+    } /* RX processing */
 
-	/*if (num_pkts < EMAC_DEF_RX_MAX_SERVICE) {
-		emac_int_enable(priv);
-	}*/
+    /*if (num_pkts < EMAC_DEF_RX_MAX_SERVICE) {
+        emac_int_enable(priv);
+    }*/
 
-	mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
-	if (priv->version == EMAC_VERSION_2)
-		mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
+    mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT;
+    if (priv->version == EMAC_VERSION_2)
+        mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT;
 
-	if (status & mask) {
-		rt_uint32_t ch, cause;
-		rt_kprintf("DaVinci EMAC: Fatal Hardware Error\n");
+    if (status & mask) {
+        rt_uint32_t ch, cause;
+        rt_kprintf("DaVinci EMAC: Fatal Hardware Error\n");
 
-		status = emac_read(EMAC_MACSTATUS);
-		cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
-			 EMAC_MACSTATUS_TXERRCODE_SHIFT);
-		if (cause) {
-			ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
-			      EMAC_MACSTATUS_TXERRCH_SHIFT);
-		}
-		cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
-			 EMAC_MACSTATUS_RXERRCODE_SHIFT);
-		if (cause) {
-			ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
-			      EMAC_MACSTATUS_RXERRCH_SHIFT);
-		}
-	} /* Host error processing */
+        status = emac_read(EMAC_MACSTATUS);
+        cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >>
+             EMAC_MACSTATUS_TXERRCODE_SHIFT);
+        if (cause) {
+            ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >>
+                  EMAC_MACSTATUS_TXERRCH_SHIFT);
+        }
+        cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >>
+             EMAC_MACSTATUS_RXERRCODE_SHIFT);
+        if (cause) {
+            ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >>
+                  EMAC_MACSTATUS_RXERRCH_SHIFT);
+        }
+    } /* Host error processing */
 
-	//return num_pkts;
-	//return p;
-	emac_int_enable(priv);
-	return RT_NULL;
+    //return num_pkts;
+    //return p;
+    emac_int_enable(priv);
+    return RT_NULL;
 }
 
 
@@ -1026,19 +1026,19 @@ struct pbuf *rt_davinci_emac_rx(rt_device_t dev)
  */
 static void emac_set_type0addr(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr)
 {
-	rt_uint32_t val;
-	val = ((mac_addr[5] << 8) | (mac_addr[4]));
-	emac_write(EMAC_MACSRCADDRLO, val);
+    rt_uint32_t val;
+    val = ((mac_addr[5] << 8) | (mac_addr[4]));
+    emac_write(EMAC_MACSRCADDRLO, val);
 
-	val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
-	       (mac_addr[1] << 8) | (mac_addr[0]));
-	emac_write(EMAC_MACSRCADDRHI, val);
-	val = emac_read(EMAC_RXUNICASTSET);
-	val |= BIT(ch);
-	emac_write(EMAC_RXUNICASTSET, val);
-	val = emac_read(EMAC_RXUNICASTCLEAR);
-	val &= ~BIT(ch);
-	emac_write(EMAC_RXUNICASTCLEAR, val);
+    val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
+           (mac_addr[1] << 8) | (mac_addr[0]));
+    emac_write(EMAC_MACSRCADDRHI, val);
+    val = emac_read(EMAC_RXUNICASTSET);
+    val |= BIT(ch);
+    emac_write(EMAC_RXUNICASTSET, val);
+    val = emac_read(EMAC_RXUNICASTCLEAR);
+    val &= ~BIT(ch);
+    emac_write(EMAC_RXUNICASTCLEAR, val);
 }
 
 /**
@@ -1053,14 +1053,14 @@ static void emac_set_type0addr(struct emac_priv *priv, rt_uint32_t ch, char *mac
  */
 static void emac_set_type1addr(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr)
 {
-	rt_uint32_t val;
-	emac_write(EMAC_MACINDEX, ch);
-	val = ((mac_addr[5] << 8) | mac_addr[4]);
-	emac_write(EMAC_MACADDRLO, val);
-	val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
-	       (mac_addr[1] << 8) | (mac_addr[0]));
-	emac_write(EMAC_MACADDRHI, val);
-	emac_set_type0addr(priv, ch, mac_addr);
+    rt_uint32_t val;
+    emac_write(EMAC_MACINDEX, ch);
+    val = ((mac_addr[5] << 8) | mac_addr[4]);
+    emac_write(EMAC_MACADDRLO, val);
+    val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
+           (mac_addr[1] << 8) | (mac_addr[0]));
+    emac_write(EMAC_MACADDRHI, val);
+    emac_set_type0addr(priv, ch, mac_addr);
 }
 
 /**
@@ -1076,17 +1076,17 @@ static void emac_set_type1addr(struct emac_priv *priv, rt_uint32_t ch, char *mac
  * Returns success (0) or appropriate error code (none as of now)
  */
 static void emac_set_type2addr(struct emac_priv *priv, rt_uint32_t ch,
-			       char *mac_addr, int index, int match)
+                   char *mac_addr, int index, int match)
 {
-	rt_uint32_t val;
-	emac_write(EMAC_MACINDEX, index);
-	val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
-	       (mac_addr[1] << 8) | (mac_addr[0]));
-	emac_write(EMAC_MACADDRHI, val);
-	val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
-	       (match << 19) | BIT(20));
-	emac_write(EMAC_MACADDRLO, val);
-	emac_set_type0addr(priv, ch, mac_addr);
+    rt_uint32_t val;
+    emac_write(EMAC_MACINDEX, index);
+    val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \
+           (mac_addr[1] << 8) | (mac_addr[0]));
+    emac_write(EMAC_MACADDRHI, val);
+    val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \
+           (match << 19) | BIT(20));
+    emac_write(EMAC_MACADDRLO, val);
+    emac_set_type0addr(priv, ch, mac_addr);
 }
 
 /**
@@ -1101,18 +1101,18 @@ static void emac_set_type2addr(struct emac_priv *priv, rt_uint32_t ch,
  */
 static void emac_setmac(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr)
 {
-	if (priv->rx_addr_type == 0) {
-		emac_set_type0addr(priv, ch, mac_addr);
-	} else if (priv->rx_addr_type == 1) {
-		rt_uint32_t cnt;
-		for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
-			emac_set_type1addr(priv, ch, mac_addr);
-	} else if (priv->rx_addr_type == 2) {
-		emac_set_type2addr(priv, ch, mac_addr, ch, 1);
-		emac_set_type0addr(priv, ch, mac_addr);
-	} else {
-		rt_kprintf("DaVinci EMAC: Wrong addressing\n");
-	}
+    if (priv->rx_addr_type == 0) {
+        emac_set_type0addr(priv, ch, mac_addr);
+    } else if (priv->rx_addr_type == 1) {
+        rt_uint32_t cnt;
+        for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++)
+            emac_set_type1addr(priv, ch, mac_addr);
+    } else if (priv->rx_addr_type == 2) {
+        emac_set_type2addr(priv, ch, mac_addr, ch, 1);
+        emac_set_type0addr(priv, ch, mac_addr);
+    } else {
+        rt_kprintf("DaVinci EMAC: Wrong addressing\n");
+    }
 }
 
 
@@ -1125,9 +1125,9 @@ static void emac_setmac(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr)
  * pointer to the memory
  *
  */
-#define EMAC_TX_BD_MEM(priv)	((priv)->emac_ctrl_ram)
-#define EMAC_RX_BD_MEM(priv)	((priv)->emac_ctrl_ram + \
-				(((priv)->ctrl_ram_size) >> 1))
+#define EMAC_TX_BD_MEM(priv)    ((priv)->emac_ctrl_ram)
+#define EMAC_RX_BD_MEM(priv)    ((priv)->emac_ctrl_ram + \
+                (((priv)->ctrl_ram_size) >> 1))
 
 /**
  * emac_init_txch: TX channel initialization
@@ -1141,59 +1141,59 @@ static void emac_setmac(struct emac_priv *priv, rt_uint32_t ch, char *mac_addr)
  */
 static int emac_init_txch(struct emac_priv *priv, rt_uint32_t ch)
 {
-	rt_uint32_t cnt, bd_size;
-	void __iomem *mem;
-	struct emac_tx_bd __iomem *curr_bd;
-	struct emac_txch *txch = RT_NULL;
+    rt_uint32_t cnt, bd_size;
+    void __iomem *mem;
+    struct emac_tx_bd __iomem *curr_bd;
+    struct emac_txch *txch = RT_NULL;
 
-	txch = rt_malloc(sizeof(struct emac_txch));
-	if (RT_NULL == txch) {
-		rt_kprintf("DaVinci EMAC: TX Ch mem alloc failed");
-		return -RT_ENOMEM;
-	}
-	rt_memset(txch, 0, sizeof(struct emac_txch));
-	priv->txch[ch] = txch;
-	txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
-	txch->active_queue_head = RT_NULL;
-	txch->active_queue_tail = RT_NULL;
-	txch->queue_active = 0;
-	txch->teardown_pending = 0;
+    txch = rt_malloc(sizeof(struct emac_txch));
+    if (RT_NULL == txch) {
+        rt_kprintf("DaVinci EMAC: TX Ch mem alloc failed");
+        return -RT_ENOMEM;
+    }
+    rt_memset(txch, 0, sizeof(struct emac_txch));
+    priv->txch[ch] = txch;
+    txch->service_max = EMAC_DEF_TX_MAX_SERVICE;
+    txch->active_queue_head = RT_NULL;
+    txch->active_queue_tail = RT_NULL;
+    txch->queue_active = 0;
+    txch->teardown_pending = 0;
 
-	/* allocate memory for TX CPPI channel on a 4 byte boundry */
-	txch->tx_complete = rt_malloc(txch->service_max * sizeof(rt_uint32_t));
-	if (RT_NULL == txch->tx_complete) {
-		rt_kprintf("DaVinci EMAC: Tx service mem alloc failed");
-		rt_free(txch);
-		return -RT_ENOMEM;
-	}
-	memset(txch->tx_complete, 0, txch->service_max * sizeof(rt_uint32_t));
+    /* allocate memory for TX CPPI channel on a 4 byte boundry */
+    txch->tx_complete = rt_malloc(txch->service_max * sizeof(rt_uint32_t));
+    if (RT_NULL == txch->tx_complete) {
+        rt_kprintf("DaVinci EMAC: Tx service mem alloc failed");
+        rt_free(txch);
+        return -RT_ENOMEM;
+    }
+    memset(txch->tx_complete, 0, txch->service_max * sizeof(rt_uint32_t));
 
-	/* allocate buffer descriptor pool align every BD on four word
-	 * boundry for future requirements */
-	bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
-	txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
-	txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
+    /* allocate buffer descriptor pool align every BD on four word
+     * boundry for future requirements */
+    bd_size = (sizeof(struct emac_tx_bd) + 0xF) & ~0xF;
+    txch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
+    txch->alloc_size = (((bd_size * txch->num_bd) + 0xF) & ~0xF);
 
-	/* alloc TX BD memory */
-	txch->bd_mem = EMAC_TX_BD_MEM(priv);
-	rt_memset((void *)txch->bd_mem, 0, txch->alloc_size);
+    /* alloc TX BD memory */
+    txch->bd_mem = EMAC_TX_BD_MEM(priv);
+    rt_memset((void *)txch->bd_mem, 0, txch->alloc_size);
 
-	/* initialize the BD linked list */
-	mem = (void __iomem *)
-			(((rt_uint32_t) txch->bd_mem + 0xF) & ~0xF);
-	txch->bd_pool_head = RT_NULL;
-	for (cnt = 0; cnt < txch->num_bd; cnt++) {
-		curr_bd = mem + (cnt * bd_size);
-		curr_bd->next = txch->bd_pool_head;
-		txch->bd_pool_head = curr_bd;
-	}
+    /* initialize the BD linked list */
+    mem = (void __iomem *)
+            (((rt_uint32_t) txch->bd_mem + 0xF) & ~0xF);
+    txch->bd_pool_head = RT_NULL;
+    for (cnt = 0; cnt < txch->num_bd; cnt++) {
+        curr_bd = mem + (cnt * bd_size);
+        curr_bd->next = txch->bd_pool_head;
+        txch->bd_pool_head = curr_bd;
+    }
 
-	/* reset statistics counters */
-	txch->out_of_tx_bd = 0;
-	txch->no_active_pkts = 0;
-	txch->active_queue_count = 0;
+    /* reset statistics counters */
+    txch->out_of_tx_bd = 0;
+    txch->no_active_pkts = 0;
+    txch->active_queue_count = 0;
 
-	return 0;
+    return 0;
 }
 
 /**
@@ -1209,74 +1209,74 @@ static int emac_init_txch(struct emac_priv *priv, rt_uint32_t ch)
  */
 static int emac_init_rxch(struct emac_priv *priv, rt_uint32_t ch, char *param)
 {
-	rt_uint32_t cnt, bd_size;
-	void __iomem *mem;
-	struct emac_rx_bd __iomem *curr_bd;
-	struct emac_rxch *rxch = RT_NULL;
+    rt_uint32_t cnt, bd_size;
+    void __iomem *mem;
+    struct emac_rx_bd __iomem *curr_bd;
+    struct emac_rxch *rxch = RT_NULL;
 
-	rxch = rt_malloc(sizeof(struct emac_rxch));
-	if (RT_NULL == rxch) {
-		rt_kprintf("DaVinci EMAC: RX Ch mem alloc failed");
-		return -ENOMEM;
-	}
-	rt_memset(rxch, 0, sizeof(struct emac_rxch));
-	priv->rxch[ch] = rxch;
-	rxch->buf_size = priv->rx_buf_size;
-	rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
-	rxch->queue_active = 0;
-	rxch->teardown_pending = 0;
+    rxch = rt_malloc(sizeof(struct emac_rxch));
+    if (RT_NULL == rxch) {
+        rt_kprintf("DaVinci EMAC: RX Ch mem alloc failed");
+        return -ENOMEM;
+    }
+    rt_memset(rxch, 0, sizeof(struct emac_rxch));
+    priv->rxch[ch] = rxch;
+    rxch->buf_size = priv->rx_buf_size;
+    rxch->service_max = EMAC_DEF_RX_MAX_SERVICE;
+    rxch->queue_active = 0;
+    rxch->teardown_pending = 0;
 
-	/* save mac address */
-	for (cnt = 0; cnt < 6; cnt++)
-		rxch->mac_addr[cnt] = param[cnt];
+    /* save mac address */
+    for (cnt = 0; cnt < 6; cnt++)
+        rxch->mac_addr[cnt] = param[cnt];
 
-	/* allocate buffer descriptor pool align every BD on four word
-	 * boundry for future requirements */
-	bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
-	rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
-	rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
-	rxch->bd_mem = EMAC_RX_BD_MEM(priv);
+    /* allocate buffer descriptor pool align every BD on four word
+     * boundry for future requirements */
+    bd_size = (sizeof(struct emac_rx_bd) + 0xF) & ~0xF;
+    rxch->num_bd = (priv->ctrl_ram_size >> 1) / bd_size;
+    rxch->alloc_size = (((bd_size * rxch->num_bd) + 0xF) & ~0xF);
+    rxch->bd_mem = EMAC_RX_BD_MEM(priv);
 
-	rt_memset((void *)rxch->bd_mem, 0, rxch->alloc_size);
-	rxch->pkt_queue.buf_list = &rxch->buf_queue;
+    rt_memset((void *)rxch->bd_mem, 0, rxch->alloc_size);
+    rxch->pkt_queue.buf_list = &rxch->buf_queue;
 
-	/* allocate RX buffer and initialize the BD linked list */
-	mem = (void __iomem *)
-			(((rt_uint32_t) rxch->bd_mem + 0xF) & ~0xF);
-	rxch->active_queue_head = RT_NULL;
-	rxch->active_queue_tail = mem;
-	for (cnt = 0; cnt < rxch->num_bd; cnt++) {
-		curr_bd = mem + (cnt * bd_size);
-		/* for future use the last parameter contains the BD ptr */
-		curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
-				    rxch->buf_size,
-				    (void **)&curr_bd->buf_token,
-				    EMAC_DEF_RX_CH);
-		if (curr_bd->data_ptr == RT_NULL) {
-			rt_kprintf("DaVinci EMAC: RX buf mem alloc " \
-				"failed for ch %d\n", ch);
-			rt_free(rxch);
-			return -RT_ENOMEM;
-		}
+    /* allocate RX buffer and initialize the BD linked list */
+    mem = (void __iomem *)
+            (((rt_uint32_t) rxch->bd_mem + 0xF) & ~0xF);
+    rxch->active_queue_head = RT_NULL;
+    rxch->active_queue_tail = mem;
+    for (cnt = 0; cnt < rxch->num_bd; cnt++) {
+        curr_bd = mem + (cnt * bd_size);
+        /* for future use the last parameter contains the BD ptr */
+        curr_bd->data_ptr = emac_net_alloc_rx_buf(priv,
+                    rxch->buf_size,
+                    (void **)&curr_bd->buf_token,
+                    EMAC_DEF_RX_CH);
+        if (curr_bd->data_ptr == RT_NULL) {
+            rt_kprintf("DaVinci EMAC: RX buf mem alloc " \
+                "failed for ch %d\n", ch);
+            rt_free(rxch);
+            return -RT_ENOMEM;
+        }
 
-		/* populate the hardware descriptor */
-		curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head);
-		curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr);
-		curr_bd->off_b_len = rxch->buf_size;
-		curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
+        /* populate the hardware descriptor */
+        curr_bd->h_next = emac_virt_to_phys(rxch->active_queue_head);
+        curr_bd->buff_ptr = virt_to_phys(curr_bd->data_ptr);
+        curr_bd->off_b_len = rxch->buf_size;
+        curr_bd->mode = EMAC_CPPI_OWNERSHIP_BIT;
 
-		/* write back to hardware memory */
-		BD_CACHE_WRITEBACK_INVALIDATE((rt_uint32_t) curr_bd,
-					      EMAC_BD_LENGTH_FOR_CACHE);
-		curr_bd->next = rxch->active_queue_head;
-		rxch->active_queue_head = curr_bd;
-	}
+        /* write back to hardware memory */
+        BD_CACHE_WRITEBACK_INVALIDATE((rt_uint32_t) curr_bd,
+                          EMAC_BD_LENGTH_FOR_CACHE);
+        curr_bd->next = rxch->active_queue_head;
+        rxch->active_queue_head = curr_bd;
+    }
 
-	/* At this point rxCppi->activeQueueHead points to the first
-	   RX BD ready to be given to RX HDP and rxch->active_queue_tail
-	   points to the last RX BD
-	 */
-	return 0;
+    /* At this point rxCppi->activeQueueHead points to the first
+       RX BD ready to be given to RX HDP and rxch->active_queue_tail
+       points to the last RX BD
+     */
+    return 0;
 }
 
 
@@ -1289,23 +1289,23 @@ static int emac_init_rxch(struct emac_priv *priv, rt_uint32_t ch, char *param)
  */
 static void emac_int_disable(struct emac_priv *priv)
 {
-	if (priv->version == EMAC_VERSION_2) {
-		unsigned long flags;
+    if (priv->version == EMAC_VERSION_2) {
+        unsigned long flags;
 
-		rt_interrupt_enter();
+        rt_interrupt_enter();
 
-		/* Program C0_Int_En to zero to turn off
-		* interrupts to the CPU */
-		emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
-		emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
-		/* NOTE: Rx Threshold and Misc interrupts are not disabled */
+        /* Program C0_Int_En to zero to turn off
+        * interrupts to the CPU */
+        emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0);
+        emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0);
+        /* NOTE: Rx Threshold and Misc interrupts are not disabled */
 
-		rt_interrupt_leave();
+        rt_interrupt_leave();
 
-	} else {
-		/* Set DM644x control registers for interrupt control */
-		emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
-	}
+    } else {
+        /* Set DM644x control registers for interrupt control */
+        emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0);
+    }
 }
 
 
@@ -1318,31 +1318,31 @@ static void emac_int_disable(struct emac_priv *priv)
  */
 static void emac_int_enable(struct emac_priv *priv)
 {
-	if (priv->version == EMAC_VERSION_2) {
-		/*if (priv->int_enable)
-			priv->int_enable();*/
+    if (priv->version == EMAC_VERSION_2) {
+        /*if (priv->int_enable)
+            priv->int_enable();*/
 
-		emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
-		emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
+        emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff);
+        emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff);
 
-		/* In addition to turning on interrupt Enable, we need
-		 * ack by writing appropriate values to the EOI
-		 * register */
+        /* In addition to turning on interrupt Enable, we need
+         * ack by writing appropriate values to the EOI
+         * register */
 
-		/* NOTE: Rx Threshold and Misc interrupts are not enabled */
+        /* NOTE: Rx Threshold and Misc interrupts are not enabled */
 
-		/* ack rxen only then a new pulse will be generated */
-		emac_write(EMAC_DM646X_MACEOIVECTOR,
-			EMAC_DM646X_MAC_EOI_C0_RXEN);
+        /* ack rxen only then a new pulse will be generated */
+        emac_write(EMAC_DM646X_MACEOIVECTOR,
+            EMAC_DM646X_MAC_EOI_C0_RXEN);
 
-		/* ack txen- only then a new pulse will be generated */
-		emac_write(EMAC_DM646X_MACEOIVECTOR,
-			EMAC_DM646X_MAC_EOI_C0_TXEN);
+        /* ack txen- only then a new pulse will be generated */
+        emac_write(EMAC_DM646X_MACEOIVECTOR,
+            EMAC_DM646X_MAC_EOI_C0_TXEN);
 
-	} else {
-		/* Set DM644x control registers for interrupt control */
-		emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
-	}
+    } else {
+        /* Set DM644x control registers for interrupt control */
+        emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1);
+    }
 }
 
 
@@ -1354,11 +1354,11 @@ static void emac_int_enable(struct emac_priv *priv)
  */
 static void emac_irq(int irq, void *param)
 {
-	struct emac_priv *priv = param;
+    struct emac_priv *priv = param;
 
-	++priv->isr_count;
-	emac_int_disable(priv);
-	eth_device_ready(&priv->parent);
+    ++priv->isr_count;
+    emac_int_disable(priv);
+    eth_device_ready(&priv->parent);
 }
 
 
@@ -1374,77 +1374,77 @@ static void emac_irq(int irq, void *param)
  */
 static int emac_hw_enable(struct emac_priv *priv)
 {
-	rt_uint32_t ch, val, mbp_enable, mac_control;
+    rt_uint32_t ch, val, mbp_enable, mac_control;
 
-	/* Soft reset */
-	emac_write(EMAC_SOFTRESET, 1);
-	while (emac_read(EMAC_SOFTRESET));
+    /* Soft reset */
+    emac_write(EMAC_SOFTRESET, 1);
+    while (emac_read(EMAC_SOFTRESET));
 
-	/* Disable interrupt & Set pacing for more interrupts initially */
-	emac_int_disable(priv);
+    /* Disable interrupt & Set pacing for more interrupts initially */
+    emac_int_disable(priv);
 
-	/* Full duplex enable bit set when auto negotiation happens */
-	mac_control =
-		(((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
-		((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
-		((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
-		((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
-	emac_write(EMAC_MACCONTROL, mac_control);
+    /* Full duplex enable bit set when auto negotiation happens */
+    mac_control =
+        (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) |
+        ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) |
+        ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) |
+        ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0));
+    emac_write(EMAC_MACCONTROL, mac_control);
 
-	mbp_enable =
-		(((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
-		((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
-		 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
-		 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
-		 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
-		 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
-		 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
-		 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
-			EMAC_RXMBP_PROMCH_SHIFT) |
-		 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
-		 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
-			EMAC_RXMBP_BROADCH_SHIFT) |
-		 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
-		 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
-			EMAC_RXMBP_MULTICH_SHIFT));
-	emac_write(EMAC_RXMBPENABLE, mbp_enable);
-	emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
-				   EMAC_RX_MAX_LEN_MASK));
-	emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
-					 EMAC_RX_BUFFER_OFFSET_MASK));
-	emac_write(EMAC_RXFILTERLOWTHRESH, 0);
-	emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
-	priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
+    mbp_enable =
+        (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) |
+        ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) |
+         ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) |
+         ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) |
+         ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) |
+         ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) |
+         ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) |
+         ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \
+            EMAC_RXMBP_PROMCH_SHIFT) |
+         ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) |
+         ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \
+            EMAC_RXMBP_BROADCH_SHIFT) |
+         ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) |
+         ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \
+            EMAC_RXMBP_MULTICH_SHIFT));
+    emac_write(EMAC_RXMBPENABLE, mbp_enable);
+    emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE &
+                   EMAC_RX_MAX_LEN_MASK));
+    emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET &
+                     EMAC_RX_BUFFER_OFFSET_MASK));
+    emac_write(EMAC_RXFILTERLOWTHRESH, 0);
+    emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL);
+    priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF;
 
-	val = emac_read(EMAC_TXCONTROL);
-	val |= EMAC_TX_CONTROL_TX_ENABLE_VAL;
-	emac_write(EMAC_TXCONTROL, val);
-	val = emac_read(EMAC_RXCONTROL);
-	val |= EMAC_RX_CONTROL_RX_ENABLE_VAL;
-	emac_write(EMAC_RXCONTROL, val);
-	emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
+    val = emac_read(EMAC_TXCONTROL);
+    val |= EMAC_TX_CONTROL_TX_ENABLE_VAL;
+    emac_write(EMAC_TXCONTROL, val);
+    val = emac_read(EMAC_RXCONTROL);
+    val |= EMAC_RX_CONTROL_RX_ENABLE_VAL;
+    emac_write(EMAC_RXCONTROL, val);
+    emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL);
 
-	for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) {
-		emac_write(EMAC_TXHDP(ch), 0);
-		emac_write(EMAC_TXINTMASKSET, BIT(ch));
-	}
-	for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
-		struct emac_rxch *rxch = priv->rxch[ch];
-		emac_setmac(priv, ch, rxch->mac_addr);
-		emac_write(EMAC_RXINTMASKSET, BIT(ch));
-		rxch->queue_active = 1;
-		emac_write(EMAC_RXHDP(ch),
-			   (unsigned int)(rxch->active_queue_head)); /* physcal addr */
-	}
+    for (ch = 0; ch < EMAC_DEF_MAX_TX_CH; ch++) {
+        emac_write(EMAC_TXHDP(ch), 0);
+        emac_write(EMAC_TXINTMASKSET, BIT(ch));
+    }
+    for (ch = 0; ch < EMAC_DEF_MAX_RX_CH; ch++) {
+        struct emac_rxch *rxch = priv->rxch[ch];
+        emac_setmac(priv, ch, rxch->mac_addr);
+        emac_write(EMAC_RXINTMASKSET, BIT(ch));
+        rxch->queue_active = 1;
+        emac_write(EMAC_RXHDP(ch),
+               (unsigned int)(rxch->active_queue_head)); /* physcal addr */
+    }
 
-	/* Enable MII */
-	val = emac_read(EMAC_MACCONTROL);
-	val |= (EMAC_MACCONTROL_GMIIEN);
-	emac_write(EMAC_MACCONTROL, val);
+    /* Enable MII */
+    val = emac_read(EMAC_MACCONTROL);
+    val |= (EMAC_MACCONTROL_GMIIEN);
+    emac_write(EMAC_MACCONTROL, val);
 
-	/* Enable interrupts */
-	emac_int_enable(priv);
-	return 0;
+    /* Enable interrupts */
+    emac_int_enable(priv);
+    return 0;
 
 }
 
@@ -1458,51 +1458,51 @@ static int emac_hw_enable(struct emac_priv *priv)
  */
 static struct net_device_stats *emac_dev_getnetstats(struct emac_priv *priv)
 {
-	rt_uint32_t mac_control;
-	rt_uint32_t stats_clear_mask;
+    rt_uint32_t mac_control;
+    rt_uint32_t stats_clear_mask;
 
-	/* update emac hardware stats and reset the registers*/
+    /* update emac hardware stats and reset the registers*/
 
-	mac_control = emac_read(EMAC_MACCONTROL);
+    mac_control = emac_read(EMAC_MACCONTROL);
 
-	if (mac_control & EMAC_MACCONTROL_GMIIEN)
-		stats_clear_mask = EMAC_STATS_CLR_MASK;
-	else
-		stats_clear_mask = 0;
+    if (mac_control & EMAC_MACCONTROL_GMIIEN)
+        stats_clear_mask = EMAC_STATS_CLR_MASK;
+    else
+        stats_clear_mask = 0;
 
-	priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
-	emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
+    priv->net_dev_stats.multicast += emac_read(EMAC_RXMCASTFRAMES);
+    emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask);
 
-	priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) +
-					   emac_read(EMAC_TXSINGLECOLL) +
-					   emac_read(EMAC_TXMULTICOLL));
-	emac_write(EMAC_TXCOLLISION, stats_clear_mask);
-	emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
-	emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
+    priv->net_dev_stats.collisions += (emac_read(EMAC_TXCOLLISION) +
+                       emac_read(EMAC_TXSINGLECOLL) +
+                       emac_read(EMAC_TXMULTICOLL));
+    emac_write(EMAC_TXCOLLISION, stats_clear_mask);
+    emac_write(EMAC_TXSINGLECOLL, stats_clear_mask);
+    emac_write(EMAC_TXMULTICOLL, stats_clear_mask);
 
-	priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
-						emac_read(EMAC_RXJABBER) +
-						emac_read(EMAC_RXUNDERSIZED));
-	emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
-	emac_write(EMAC_RXJABBER, stats_clear_mask);
-	emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
+    priv->net_dev_stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) +
+                        emac_read(EMAC_RXJABBER) +
+                        emac_read(EMAC_RXUNDERSIZED));
+    emac_write(EMAC_RXOVERSIZED, stats_clear_mask);
+    emac_write(EMAC_RXJABBER, stats_clear_mask);
+    emac_write(EMAC_RXUNDERSIZED, stats_clear_mask);
 
-	priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
-					       emac_read(EMAC_RXMOFOVERRUNS));
-	emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
-	emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
+    priv->net_dev_stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) +
+                           emac_read(EMAC_RXMOFOVERRUNS));
+    emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask);
+    emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask);
 
-	priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
-	emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
+    priv->net_dev_stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS);
+    emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask);
 
-	priv->net_dev_stats.tx_carrier_errors +=
-		emac_read(EMAC_TXCARRIERSENSE);
-	emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
+    priv->net_dev_stats.tx_carrier_errors +=
+        emac_read(EMAC_TXCARRIERSENSE);
+    emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask);
 
-	priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
-	emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
+    priv->net_dev_stats.tx_fifo_errors = emac_read(EMAC_TXUNDERRUN);
+    emac_write(EMAC_TXUNDERRUN, stats_clear_mask);
 
-	return &priv->net_dev_stats;
+    return &priv->net_dev_stats;
 }
 
 
@@ -1511,164 +1511,164 @@ static struct net_device_stats *emac_dev_getnetstats(struct emac_priv *priv)
 
 static rt_err_t rt_davinci_emac_init(rt_device_t dev)
 {
-	struct emac_priv *priv = dev->user_data;
-	unsigned long paddr;
-	rt_uint32_t ch, rc;
-	int i;
+    struct emac_priv *priv = dev->user_data;
+    unsigned long paddr;
+    rt_uint32_t ch, rc;
+    int i;
+
+    /* Configuration items */
+    priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
 
-	/* Configuration items */
-	priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN;
+    /* Clear basic hardware */
+    for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
+        emac_write(EMAC_TXHDP(ch), 0);
+        emac_write(EMAC_RXHDP(ch), 0);
+        emac_write(EMAC_RXHDP(ch), 0);
+        emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
+        emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
+    }
+    priv->mac_hash1 = 0;
+    priv->mac_hash2 = 0;
+    emac_write(EMAC_MACHASH1, 0);
+    emac_write(EMAC_MACHASH2, 0);
 
-	/* Clear basic hardware */
-	for (ch = 0; ch < EMAC_MAX_TXRX_CHANNELS; ch++) {
-		emac_write(EMAC_TXHDP(ch), 0);
-		emac_write(EMAC_RXHDP(ch), 0);
-		emac_write(EMAC_RXHDP(ch), 0);
-		emac_write(EMAC_RXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
-		emac_write(EMAC_TXINTMASKCLEAR, EMAC_INT_MASK_CLEAR);
-	}
-	priv->mac_hash1 = 0;
-	priv->mac_hash2 = 0;
-	emac_write(EMAC_MACHASH1, 0);
-	emac_write(EMAC_MACHASH2, 0);
+    /* multi ch not supported - open 1 TX, 1RX ch by default */
+    rc = emac_init_txch(priv, EMAC_DEF_TX_CH);
+    if (0 != rc) {
+        rt_kprintf("DaVinci EMAC: emac_init_txch() failed");
+        return rc;
+    }
+    rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr);
+    if (0 != rc) {
+        rt_kprintf("DaVinci EMAC: emac_init_rxch() failed");
+        return rc;
+    }
 
-	/* multi ch not supported - open 1 TX, 1RX ch by default */
-	rc = emac_init_txch(priv, EMAC_DEF_TX_CH);
-	if (0 != rc) {
-		rt_kprintf("DaVinci EMAC: emac_init_txch() failed");
-		return rc;
-	}
-	rc = emac_init_rxch(priv, EMAC_DEF_RX_CH, priv->mac_addr);
-	if (0 != rc) {
-		rt_kprintf("DaVinci EMAC: emac_init_rxch() failed");
-		return rc;
-	}
+    rt_hw_interrupt_install(IRQ_DM365_EMAC_RXPULSE, emac_irq,
+                            (void *)priv, "EMAC_RXPULSE");
+    rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXPULSE);
+    rt_hw_interrupt_install(IRQ_DM365_EMAC_TXPULSE, emac_irq,
+                            (void *)priv, "EMAC_TXPULSE");
+    rt_hw_interrupt_umask(IRQ_DM365_EMAC_TXPULSE);
+    rt_hw_interrupt_install(IRQ_DM365_EMAC_RXTHRESH, emac_irq,
+                            (void *)priv, "EMAC_RXTHRESH");
+    rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXTHRESH);
+    rt_hw_interrupt_install(IRQ_DM365_EMAC_MISCPULSE, emac_irq,
+                            (void *)priv, "EMAC_MISCPULSE");
+    rt_hw_interrupt_umask(IRQ_DM365_EMAC_MISCPULSE);
 
-	rt_hw_interrupt_install(IRQ_DM365_EMAC_RXPULSE, emac_irq, 
-							(void *)priv, "EMAC_RXPULSE");
-	rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXPULSE);
-	rt_hw_interrupt_install(IRQ_DM365_EMAC_TXPULSE, emac_irq, 
-							(void *)priv, "EMAC_TXPULSE");
-	rt_hw_interrupt_umask(IRQ_DM365_EMAC_TXPULSE);
-	rt_hw_interrupt_install(IRQ_DM365_EMAC_RXTHRESH, emac_irq, 
-							(void *)priv, "EMAC_RXTHRESH");
-	rt_hw_interrupt_umask(IRQ_DM365_EMAC_RXTHRESH);
-	rt_hw_interrupt_install(IRQ_DM365_EMAC_MISCPULSE, emac_irq, 
-							(void *)priv, "EMAC_MISCPULSE");
-	rt_hw_interrupt_umask(IRQ_DM365_EMAC_MISCPULSE);
+    emac_mii_reset(priv);
+    davinci_emac_phy_init(dev);
 
-	emac_mii_reset(priv);
-	davinci_emac_phy_init(dev);
+    /* Start/Enable EMAC hardware */
+    emac_hw_enable(priv);
 
-	/* Start/Enable EMAC hardware */
-	emac_hw_enable(priv);
+    rt_timer_init(&priv->timer, "link_timer",
+        davinci_emac_update_link,
+        (void *)priv,
+        RT_TICK_PER_SECOND,
+        RT_TIMER_FLAG_PERIODIC);
 
-	rt_timer_init(&priv->timer, "link_timer", 
-		davinci_emac_update_link, 
-		(void *)priv, 
-		RT_TICK_PER_SECOND, 
-		RT_TIMER_FLAG_PERIODIC);
+    rt_timer_start(&priv->timer);
+    rt_kprintf("davinci emac initialized\n");
 
-	rt_timer_start(&priv->timer);
-	rt_kprintf("davinci emac initialized\n");
-	
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_davinci_emac_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_davinci_emac_close(rt_device_t dev)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_davinci_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_size_t rt_davinci_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_err_t rt_davinci_emac_control(rt_device_t dev, int cmd, void *args)
 {
-	struct emac_priv *priv = dev->user_data;
-	switch(cmd)
-	{
-	case NIOCTL_GADDR:
-		/* get mac address */
-		if(args) rt_memcpy(args, priv->mac_addr, 6);
-		else return -RT_ERROR;
-		break;
+    struct emac_priv *priv = dev->user_data;
+    switch(cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if(args) rt_memcpy(args, priv->mac_addr, 6);
+        else return -RT_ERROR;
+        break;
 
-	default :
-		break;
-	}
+    default :
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 void dm365_emac_gpio_init(void)
 {
-	rt_uint32_t arm_intmux;
+    rt_uint32_t arm_intmux;
 
-	/*
-	 * EMAC interrupts are multiplexed with GPIO interrupts
-	 * Details are available at the DM365 ARM
-	 * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
-	 */
-	arm_intmux = davinci_readl(DM365_ARM_INTMUX);
-	arm_intmux |= (1 << 14)|(1 << 15)|(1 << 16)|(1 << 17);
-	davinci_writel(arm_intmux, DM365_ARM_INTMUX);
+    /*
+     * EMAC interrupts are multiplexed with GPIO interrupts
+     * Details are available at the DM365 ARM
+     * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134
+     */
+    arm_intmux = davinci_readl(DM365_ARM_INTMUX);
+    arm_intmux |= (1 << 14)|(1 << 15)|(1 << 16)|(1 << 17);
+    davinci_writel(arm_intmux, DM365_ARM_INTMUX);
 }
 
 int rt_hw_davinci_emac_init()
 {
-	struct emac_priv *priv = &davinci_emac_device;
-	struct clk  *emac_clk;
-	emac_clk = clk_get("EMACCLK");
-	emac_bus_frequency = clk_get_rate(emac_clk);
-	psc_change_state(DAVINCI_DM365_LPSC_CPGMAC, PSC_ENABLE);
-	dm365_emac_gpio_init();
-	rt_memset(&davinci_emac_device, 0, sizeof(davinci_emac_device));
-	davinci_emac_device.emac_base = (void __iomem *)DM365_EMAC_CNTRL_BASE;
-	davinci_emac_device.ctrl_base = (void __iomem *)DM365_EMAC_WRAP_CNTRL_BASE;
-	davinci_emac_device.ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE;
-	davinci_emac_device.emac_ctrl_ram = (void __iomem *)DM365_EMAC_WRAP_RAM_BASE;
-	davinci_emac_device.mdio_base = (void __iomem *)DM365_EMAC_MDIO_BASE;
-	davinci_emac_device.version = EMAC_VERSION_2;
-	davinci_emac_device.rmii_en = 0;
-	davinci_emac_device.phy_addr = 0x09;
-	rt_sem_init(&priv->tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO);
-	rt_sem_init(&priv->rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO);
+    struct emac_priv *priv = &davinci_emac_device;
+    struct clk  *emac_clk;
+    emac_clk = clk_get("EMACCLK");
+    emac_bus_frequency = clk_get_rate(emac_clk);
+    psc_change_state(DAVINCI_DM365_LPSC_CPGMAC, PSC_ENABLE);
+    dm365_emac_gpio_init();
+    rt_memset(&davinci_emac_device, 0, sizeof(davinci_emac_device));
+    davinci_emac_device.emac_base = (void __iomem *)DM365_EMAC_CNTRL_BASE;
+    davinci_emac_device.ctrl_base = (void __iomem *)DM365_EMAC_WRAP_CNTRL_BASE;
+    davinci_emac_device.ctrl_ram_size = DM365_EMAC_CNTRL_RAM_SIZE;
+    davinci_emac_device.emac_ctrl_ram = (void __iomem *)DM365_EMAC_WRAP_RAM_BASE;
+    davinci_emac_device.mdio_base = (void __iomem *)DM365_EMAC_MDIO_BASE;
+    davinci_emac_device.version = EMAC_VERSION_2;
+    davinci_emac_device.rmii_en = 0;
+    davinci_emac_device.phy_addr = 0x09;
+    rt_sem_init(&priv->tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO);
+    rt_sem_init(&priv->rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO);
+
+    davinci_emac_device.mac_addr[0] = 0x00;
+    davinci_emac_device.mac_addr[1] = 0x60;
+    davinci_emac_device.mac_addr[2] = 0x6E;
+    davinci_emac_device.mac_addr[3] = 0x11;
+    davinci_emac_device.mac_addr[4] = 0x22;
+    davinci_emac_device.mac_addr[5] = 0x33;
+
+    davinci_emac_device.parent.parent.init       = rt_davinci_emac_init;
+    davinci_emac_device.parent.parent.open       = rt_davinci_emac_open;
+    davinci_emac_device.parent.parent.close      = rt_davinci_emac_close;
+    davinci_emac_device.parent.parent.read       = rt_davinci_emac_read;
+    davinci_emac_device.parent.parent.write      = rt_davinci_emac_write;
+    davinci_emac_device.parent.parent.control    = rt_davinci_emac_control;
+    davinci_emac_device.parent.parent.user_data  = &davinci_emac_device;
 
-	davinci_emac_device.mac_addr[0] = 0x00;
-	davinci_emac_device.mac_addr[1] = 0x60;
-	davinci_emac_device.mac_addr[2] = 0x6E;
-	davinci_emac_device.mac_addr[3] = 0x11;
-	davinci_emac_device.mac_addr[4] = 0x22;
-	davinci_emac_device.mac_addr[5] = 0x33;
-	
-	davinci_emac_device.parent.parent.init       = rt_davinci_emac_init;
-	davinci_emac_device.parent.parent.open       = rt_davinci_emac_open;
-	davinci_emac_device.parent.parent.close      = rt_davinci_emac_close;
-	davinci_emac_device.parent.parent.read       = rt_davinci_emac_read;
-	davinci_emac_device.parent.parent.write      = rt_davinci_emac_write;
-	davinci_emac_device.parent.parent.control    = rt_davinci_emac_control;
-	davinci_emac_device.parent.parent.user_data  = &davinci_emac_device;
+    davinci_emac_device.parent.eth_rx     = rt_davinci_emac_rx;
+    davinci_emac_device.parent.eth_tx     = rt_davinci_emac_tx;
 
-	davinci_emac_device.parent.eth_rx     = rt_davinci_emac_rx;
-	davinci_emac_device.parent.eth_tx     = rt_davinci_emac_tx;
+    eth_device_init(&(davinci_emac_device.parent), "e0");
 
-	eth_device_init(&(davinci_emac_device.parent), "e0");
-	
 }
 
 INIT_DEVICE_EXPORT(rt_hw_davinci_emac_init);
@@ -1679,68 +1679,68 @@ INIT_DEVICE_EXPORT(rt_hw_davinci_emac_init);
 
 void dump_emac_stats(void)
 {
-	int i;
-	struct emac_priv *emac;
-	struct net_device_stats *stats;
-	rt_device_t dev = rt_device_find("e0");
+    int i;
+    struct emac_priv *emac;
+    struct net_device_stats *stats;
+    rt_device_t dev = rt_device_find("e0");
 
-	if(dev == RT_NULL)
-		return;
+    if(dev == RT_NULL)
+        return;
 
-	emac = (struct emac_priv *)dev->user_data;
+    emac = (struct emac_priv *)dev->user_data;
 
-	stats = emac_dev_getnetstats(emac);
-	rt_kprintf("rx_packets      = %d\n"
-				"tx_packets      = %d\n"
-				"rx_bytes        = %d\n"
-				"tx_bytes        = %d\n"
-				"rx_errors       = %d\n"
-				"tx_errors       = %d\n"
-				"rx_dropped      = %d\n"
-				"tx_dropped      = %d\n"
-				"multicast       = %d\n"
-				"collisions      = %d\n",
-		stats->rx_packets,
-		stats->tx_packets,
-		stats->rx_bytes,
-		stats->tx_bytes,
-		stats->rx_errors,
-		stats->tx_errors,
-		stats->rx_dropped,
-		stats->tx_dropped,
-		stats->multicast,
-		stats->collisions);
+    stats = emac_dev_getnetstats(emac);
+    rt_kprintf("rx_packets      = %d\n"
+                "tx_packets      = %d\n"
+                "rx_bytes        = %d\n"
+                "tx_bytes        = %d\n"
+                "rx_errors       = %d\n"
+                "tx_errors       = %d\n"
+                "rx_dropped      = %d\n"
+                "tx_dropped      = %d\n"
+                "multicast       = %d\n"
+                "collisions      = %d\n",
+        stats->rx_packets,
+        stats->tx_packets,
+        stats->rx_bytes,
+        stats->tx_bytes,
+        stats->rx_errors,
+        stats->tx_errors,
+        stats->rx_dropped,
+        stats->tx_dropped,
+        stats->multicast,
+        stats->collisions);
 
-	rt_kprintf("rx_length_errors = %d\n"
-				"rx_over_errors   = %d\n"
-				"rx_crc_errors    = %d\n"
-				"rx_frame_errors  = %d\n"
-				"rx_fifo_errors   = %d\n"
-				"rx_missed_errors = %d\n",
-		stats->rx_length_errors,
-		stats->rx_over_errors,
-		stats->rx_crc_errors,
-		stats->rx_frame_errors,
-		stats->rx_fifo_errors,
-		stats->rx_missed_errors);
+    rt_kprintf("rx_length_errors = %d\n"
+                "rx_over_errors   = %d\n"
+                "rx_crc_errors    = %d\n"
+                "rx_frame_errors  = %d\n"
+                "rx_fifo_errors   = %d\n"
+                "rx_missed_errors = %d\n",
+        stats->rx_length_errors,
+        stats->rx_over_errors,
+        stats->rx_crc_errors,
+        stats->rx_frame_errors,
+        stats->rx_fifo_errors,
+        stats->rx_missed_errors);
 
-	rt_kprintf("tx_aborted_errors   = %d\n"
-				"tx_carrier_errors   = %d\n"
-				"tx_fifo_errors      = %d\n"
-				"tx_heartbeat_errors = %d\n"
-				"tx_window_errors    = %d\n",
-		stats->tx_aborted_errors,
-		stats->tx_carrier_errors,
-		stats->tx_fifo_errors,
-		stats->tx_heartbeat_errors,
-		stats->tx_window_errors);
+    rt_kprintf("tx_aborted_errors   = %d\n"
+                "tx_carrier_errors   = %d\n"
+                "tx_fifo_errors      = %d\n"
+                "tx_heartbeat_errors = %d\n"
+                "tx_window_errors    = %d\n",
+        stats->tx_aborted_errors,
+        stats->tx_carrier_errors,
+        stats->tx_fifo_errors,
+        stats->tx_heartbeat_errors,
+        stats->tx_window_errors);
 
-	rt_kprintf("rx_compressed  = %d\n"
-				"tx_compressed  = %d\n",
-		stats->rx_compressed,
-		stats->tx_compressed);
+    rt_kprintf("rx_compressed  = %d\n"
+                "tx_compressed  = %d\n",
+        stats->rx_compressed,
+        stats->tx_compressed);
 
-	rt_kprintf("\n");
+    rt_kprintf("\n");
 }
 
 FINSH_FUNCTION_EXPORT(dump_emac_stats, dump emac statistics);
@@ -1748,8 +1748,8 @@ FINSH_FUNCTION_EXPORT(dump_emac_stats, dump emac statistics);
 #ifdef FINSH_USING_MSH
 int cmd_dump_emac_stats(int argc, char** argv)
 {
-	dump_emac_stats();
-	return 0;
+    dump_emac_stats();
+    return 0;
 }
 FINSH_FUNCTION_EXPORT_ALIAS(cmd_dump_emac_stats, __cmd_dump_emac_stats, dump emac statistics.);
 #endif
diff --git a/bsp/dm365/drivers/davinci_emac.h b/bsp/dm365/drivers/davinci_emac.h
index 2b07834583..1d80c754c9 100644
--- a/bsp/dm365/drivers/davinci_emac.h
+++ b/bsp/dm365/drivers/davinci_emac.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2013-01-30     weety		first version
+ * Date           Author        Notes
+ * 2013-01-30     weety     first version
  */
 
 #ifndef _DAVINCI_EMAC_H
@@ -17,249 +17,249 @@
 #endif
 
 enum {
-	EMAC_VERSION_1,	/* DM644x */
-	EMAC_VERSION_2,	/* DM646x */
+    EMAC_VERSION_1, /* DM644x */
+    EMAC_VERSION_2, /* DM646x */
 };
 
 
 #define __iomem
 
-#define BIT(nr)			(1UL << (nr))
+#define BIT(nr)         (1UL << (nr))
 
 
 /* Configuration items */
-#define EMAC_DEF_PASS_CRC		(0) /* Do not pass CRC upto frames */
-#define EMAC_DEF_QOS_EN			(0) /* EMAC proprietary QoS disabled */
-#define EMAC_DEF_NO_BUFF_CHAIN		(0) /* No buffer chain */
-#define EMAC_DEF_MACCTRL_FRAME_EN	(0) /* Discard Maccontrol frames */
-#define EMAC_DEF_SHORT_FRAME_EN		(0) /* Discard short frames */
-#define EMAC_DEF_ERROR_FRAME_EN		(0) /* Discard error frames */
-#define EMAC_DEF_PROM_EN		(0) /* Promiscous disabled */
-#define EMAC_DEF_PROM_CH		(0) /* Promiscous channel is 0 */
-#define EMAC_DEF_BCAST_EN		(1) /* Broadcast enabled */
-#define EMAC_DEF_BCAST_CH		(0) /* Broadcast channel is 0 */
-#define EMAC_DEF_MCAST_EN		(1) /* Multicast enabled */
-#define EMAC_DEF_MCAST_CH		(0) /* Multicast channel is 0 */
+#define EMAC_DEF_PASS_CRC       (0) /* Do not pass CRC upto frames */
+#define EMAC_DEF_QOS_EN         (0) /* EMAC proprietary QoS disabled */
+#define EMAC_DEF_NO_BUFF_CHAIN      (0) /* No buffer chain */
+#define EMAC_DEF_MACCTRL_FRAME_EN   (0) /* Discard Maccontrol frames */
+#define EMAC_DEF_SHORT_FRAME_EN     (0) /* Discard short frames */
+#define EMAC_DEF_ERROR_FRAME_EN     (0) /* Discard error frames */
+#define EMAC_DEF_PROM_EN        (0) /* Promiscous disabled */
+#define EMAC_DEF_PROM_CH        (0) /* Promiscous channel is 0 */
+#define EMAC_DEF_BCAST_EN       (1) /* Broadcast enabled */
+#define EMAC_DEF_BCAST_CH       (0) /* Broadcast channel is 0 */
+#define EMAC_DEF_MCAST_EN       (1) /* Multicast enabled */
+#define EMAC_DEF_MCAST_CH       (0) /* Multicast channel is 0 */
 
-#define EMAC_DEF_TXPRIO_FIXED		(1) /* TX Priority is fixed */
-#define EMAC_DEF_TXPACING_EN		(0) /* TX pacing NOT supported*/
+#define EMAC_DEF_TXPRIO_FIXED       (1) /* TX Priority is fixed */
+#define EMAC_DEF_TXPACING_EN        (0) /* TX pacing NOT supported*/
 
-#define EMAC_DEF_BUFFER_OFFSET		(0) /* Buffer offset to DMA (future) */
-#define EMAC_DEF_MIN_ETHPKTSIZE		(60) /* Minimum ethernet pkt size */
-#define EMAC_DEF_MAX_FRAME_SIZE		(1500 + 14 + 4 + 4)
-#define EMAC_DEF_TX_CH			(0) /* Default 0th channel */
-#define EMAC_DEF_RX_CH			(0) /* Default 0th channel */
-#define EMAC_DEF_MDIO_TICK_MS		(10) /* typically 1 tick=1 ms) */
-#define EMAC_DEF_MAX_TX_CH		(1) /* Max TX channels configured */
-#define EMAC_DEF_MAX_RX_CH		(1) /* Max RX channels configured */
-#define EMAC_POLL_WEIGHT		(64) /* Default NAPI poll weight */
+#define EMAC_DEF_BUFFER_OFFSET      (0) /* Buffer offset to DMA (future) */
+#define EMAC_DEF_MIN_ETHPKTSIZE     (60) /* Minimum ethernet pkt size */
+#define EMAC_DEF_MAX_FRAME_SIZE     (1500 + 14 + 4 + 4)
+#define EMAC_DEF_TX_CH          (0) /* Default 0th channel */
+#define EMAC_DEF_RX_CH          (0) /* Default 0th channel */
+#define EMAC_DEF_MDIO_TICK_MS       (10) /* typically 1 tick=1 ms) */
+#define EMAC_DEF_MAX_TX_CH      (1) /* Max TX channels configured */
+#define EMAC_DEF_MAX_RX_CH      (1) /* Max RX channels configured */
+#define EMAC_POLL_WEIGHT        (64) /* Default NAPI poll weight */
 
 /* Buffer descriptor parameters */
-#define EMAC_DEF_TX_MAX_SERVICE		(32) /* TX max service BD's */
-#define EMAC_DEF_RX_MAX_SERVICE		(64) /* should = netdev->weight */
+#define EMAC_DEF_TX_MAX_SERVICE     (32) /* TX max service BD's */
+#define EMAC_DEF_RX_MAX_SERVICE     (64) /* should = netdev->weight */
 
 /* EMAC register related defines */
-#define EMAC_ALL_MULTI_REG_VALUE	(0xFFFFFFFF)
-#define EMAC_NUM_MULTICAST_BITS		(64)
-#define EMAC_TEARDOWN_VALUE		(0xFFFFFFFC)
-#define EMAC_TX_CONTROL_TX_ENABLE_VAL	(0x1)
-#define EMAC_RX_CONTROL_RX_ENABLE_VAL	(0x1)
-#define EMAC_MAC_HOST_ERR_INTMASK_VAL	(0x2)
-#define EMAC_RX_UNICAST_CLEAR_ALL	(0xFF)
-#define EMAC_INT_MASK_CLEAR		(0xFF)
+#define EMAC_ALL_MULTI_REG_VALUE    (0xFFFFFFFF)
+#define EMAC_NUM_MULTICAST_BITS     (64)
+#define EMAC_TEARDOWN_VALUE     (0xFFFFFFFC)
+#define EMAC_TX_CONTROL_TX_ENABLE_VAL   (0x1)
+#define EMAC_RX_CONTROL_RX_ENABLE_VAL   (0x1)
+#define EMAC_MAC_HOST_ERR_INTMASK_VAL   (0x2)
+#define EMAC_RX_UNICAST_CLEAR_ALL   (0xFF)
+#define EMAC_INT_MASK_CLEAR     (0xFF)
 
 /* RX MBP register bit positions */
-#define EMAC_RXMBP_PASSCRC_MASK		BIT(30)
-#define EMAC_RXMBP_QOSEN_MASK		BIT(29)
-#define EMAC_RXMBP_NOCHAIN_MASK		BIT(28)
-#define EMAC_RXMBP_CMFEN_MASK		BIT(24)
-#define EMAC_RXMBP_CSFEN_MASK		BIT(23)
-#define EMAC_RXMBP_CEFEN_MASK		BIT(22)
-#define EMAC_RXMBP_CAFEN_MASK		BIT(21)
-#define EMAC_RXMBP_PROMCH_SHIFT		(16)
-#define EMAC_RXMBP_PROMCH_MASK		(0x7 << 16)
-#define EMAC_RXMBP_BROADEN_MASK		BIT(13)
-#define EMAC_RXMBP_BROADCH_SHIFT	(8)
-#define EMAC_RXMBP_BROADCH_MASK		(0x7 << 8)
-#define EMAC_RXMBP_MULTIEN_MASK		BIT(5)
-#define EMAC_RXMBP_MULTICH_SHIFT	(0)
-#define EMAC_RXMBP_MULTICH_MASK		(0x7)
-#define EMAC_RXMBP_CHMASK		(0x7)
+#define EMAC_RXMBP_PASSCRC_MASK     BIT(30)
+#define EMAC_RXMBP_QOSEN_MASK       BIT(29)
+#define EMAC_RXMBP_NOCHAIN_MASK     BIT(28)
+#define EMAC_RXMBP_CMFEN_MASK       BIT(24)
+#define EMAC_RXMBP_CSFEN_MASK       BIT(23)
+#define EMAC_RXMBP_CEFEN_MASK       BIT(22)
+#define EMAC_RXMBP_CAFEN_MASK       BIT(21)
+#define EMAC_RXMBP_PROMCH_SHIFT     (16)
+#define EMAC_RXMBP_PROMCH_MASK      (0x7 << 16)
+#define EMAC_RXMBP_BROADEN_MASK     BIT(13)
+#define EMAC_RXMBP_BROADCH_SHIFT    (8)
+#define EMAC_RXMBP_BROADCH_MASK     (0x7 << 8)
+#define EMAC_RXMBP_MULTIEN_MASK     BIT(5)
+#define EMAC_RXMBP_MULTICH_SHIFT    (0)
+#define EMAC_RXMBP_MULTICH_MASK     (0x7)
+#define EMAC_RXMBP_CHMASK       (0x7)
 
 /* EMAC register definitions/bit maps used */
-# define EMAC_MBP_RXPROMISC		(0x00200000)
-# define EMAC_MBP_PROMISCCH(ch)		(((ch) & 0x7) << 16)
-# define EMAC_MBP_RXBCAST		(0x00002000)
-# define EMAC_MBP_BCASTCHAN(ch)		(((ch) & 0x7) << 8)
-# define EMAC_MBP_RXMCAST		(0x00000020)
-# define EMAC_MBP_MCASTCHAN(ch)		((ch) & 0x7)
+# define EMAC_MBP_RXPROMISC     (0x00200000)
+# define EMAC_MBP_PROMISCCH(ch)     (((ch) & 0x7) << 16)
+# define EMAC_MBP_RXBCAST       (0x00002000)
+# define EMAC_MBP_BCASTCHAN(ch)     (((ch) & 0x7) << 8)
+# define EMAC_MBP_RXMCAST       (0x00000020)
+# define EMAC_MBP_MCASTCHAN(ch)     ((ch) & 0x7)
 
 /* EMAC mac_control register */
-#define EMAC_MACCONTROL_TXPTYPE		BIT(9)
-#define EMAC_MACCONTROL_TXPACEEN	BIT(6)
-#define EMAC_MACCONTROL_GMIIEN		BIT(5)
-#define EMAC_MACCONTROL_GIGABITEN	BIT(7)
-#define EMAC_MACCONTROL_FULLDUPLEXEN	BIT(0)
-#define EMAC_MACCONTROL_RMIISPEED_MASK	BIT(15)
+#define EMAC_MACCONTROL_TXPTYPE     BIT(9)
+#define EMAC_MACCONTROL_TXPACEEN    BIT(6)
+#define EMAC_MACCONTROL_GMIIEN      BIT(5)
+#define EMAC_MACCONTROL_GIGABITEN   BIT(7)
+#define EMAC_MACCONTROL_FULLDUPLEXEN    BIT(0)
+#define EMAC_MACCONTROL_RMIISPEED_MASK  BIT(15)
 
 /* GIGABIT MODE related bits */
-#define EMAC_DM646X_MACCONTORL_GIG	BIT(7)
-#define EMAC_DM646X_MACCONTORL_GIGFORCE	BIT(17)
+#define EMAC_DM646X_MACCONTORL_GIG  BIT(7)
+#define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17)
 
 /* EMAC mac_status register */
-#define EMAC_MACSTATUS_TXERRCODE_MASK	(0xF00000)
-#define EMAC_MACSTATUS_TXERRCODE_SHIFT	(20)
-#define EMAC_MACSTATUS_TXERRCH_MASK	(0x7)
-#define EMAC_MACSTATUS_TXERRCH_SHIFT	(16)
-#define EMAC_MACSTATUS_RXERRCODE_MASK	(0xF000)
-#define EMAC_MACSTATUS_RXERRCODE_SHIFT	(12)
-#define EMAC_MACSTATUS_RXERRCH_MASK	(0x7)
-#define EMAC_MACSTATUS_RXERRCH_SHIFT	(8)
+#define EMAC_MACSTATUS_TXERRCODE_MASK   (0xF00000)
+#define EMAC_MACSTATUS_TXERRCODE_SHIFT  (20)
+#define EMAC_MACSTATUS_TXERRCH_MASK (0x7)
+#define EMAC_MACSTATUS_TXERRCH_SHIFT    (16)
+#define EMAC_MACSTATUS_RXERRCODE_MASK   (0xF000)
+#define EMAC_MACSTATUS_RXERRCODE_SHIFT  (12)
+#define EMAC_MACSTATUS_RXERRCH_MASK (0x7)
+#define EMAC_MACSTATUS_RXERRCH_SHIFT    (8)
 
 /* EMAC RX register masks */
-#define EMAC_RX_MAX_LEN_MASK		(0xFFFF)
-#define EMAC_RX_BUFFER_OFFSET_MASK	(0xFFFF)
+#define EMAC_RX_MAX_LEN_MASK        (0xFFFF)
+#define EMAC_RX_BUFFER_OFFSET_MASK  (0xFFFF)
 
 /* MAC_IN_VECTOR (0x180) register bit fields */
-#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT	BIT(17)
-#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT	BIT(16)
-#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC	BIT(8)
-#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC	BIT(0)
+#define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT  BIT(17)
+#define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT  BIT(16)
+#define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC    BIT(8)
+#define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC    BIT(0)
 
 /** NOTE:: For DM646x the IN_VECTOR has changed */
-#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC	BIT(EMAC_DEF_RX_CH)
-#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC	BIT(16 + EMAC_DEF_TX_CH)
-#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT	BIT(26)
-#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT	BIT(27)
+#define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC    BIT(EMAC_DEF_RX_CH)
+#define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC    BIT(16 + EMAC_DEF_TX_CH)
+#define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT  BIT(26)
+#define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT  BIT(27)
 
 /* CPPI bit positions */
-#define EMAC_CPPI_SOP_BIT		BIT(31)
-#define EMAC_CPPI_EOP_BIT		BIT(30)
-#define EMAC_CPPI_OWNERSHIP_BIT		BIT(29)
-#define EMAC_CPPI_EOQ_BIT		BIT(28)
+#define EMAC_CPPI_SOP_BIT       BIT(31)
+#define EMAC_CPPI_EOP_BIT       BIT(30)
+#define EMAC_CPPI_OWNERSHIP_BIT     BIT(29)
+#define EMAC_CPPI_EOQ_BIT       BIT(28)
 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27)
-#define EMAC_CPPI_PASS_CRC_BIT		BIT(26)
-#define EMAC_RX_BD_BUF_SIZE		(0xFFFF)
-#define EMAC_BD_LENGTH_FOR_CACHE	(16) /* only CPPI bytes */
-#define EMAC_RX_BD_PKT_LENGTH_MASK	(0xFFFF)
+#define EMAC_CPPI_PASS_CRC_BIT      BIT(26)
+#define EMAC_RX_BD_BUF_SIZE     (0xFFFF)
+#define EMAC_BD_LENGTH_FOR_CACHE    (16) /* only CPPI bytes */
+#define EMAC_RX_BD_PKT_LENGTH_MASK  (0xFFFF)
 
 /* Max hardware defines */
-#define EMAC_MAX_TXRX_CHANNELS		 (8)  /* Max hardware channels */
+#define EMAC_MAX_TXRX_CHANNELS       (8)  /* Max hardware channels */
 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */
 
 /* EMAC Peripheral Device Register Memory Layout structure */
-#define EMAC_TXIDVER		0x0
-#define EMAC_TXCONTROL		0x4
-#define EMAC_TXTEARDOWN		0x8
-#define EMAC_RXIDVER		0x10
-#define EMAC_RXCONTROL		0x14
-#define EMAC_RXTEARDOWN		0x18
-#define EMAC_TXINTSTATRAW	0x80
-#define EMAC_TXINTSTATMASKED	0x84
-#define EMAC_TXINTMASKSET	0x88
-#define EMAC_TXINTMASKCLEAR	0x8C
-#define EMAC_MACINVECTOR	0x90
+#define EMAC_TXIDVER        0x0
+#define EMAC_TXCONTROL      0x4
+#define EMAC_TXTEARDOWN     0x8
+#define EMAC_RXIDVER        0x10
+#define EMAC_RXCONTROL      0x14
+#define EMAC_RXTEARDOWN     0x18
+#define EMAC_TXINTSTATRAW   0x80
+#define EMAC_TXINTSTATMASKED    0x84
+#define EMAC_TXINTMASKSET   0x88
+#define EMAC_TXINTMASKCLEAR 0x8C
+#define EMAC_MACINVECTOR    0x90
 
-#define EMAC_DM646X_MACEOIVECTOR	0x94
+#define EMAC_DM646X_MACEOIVECTOR    0x94
 
-#define EMAC_RXINTSTATRAW	0xA0
-#define EMAC_RXINTSTATMASKED	0xA4
-#define EMAC_RXINTMASKSET	0xA8
-#define EMAC_RXINTMASKCLEAR	0xAC
-#define EMAC_MACINTSTATRAW	0xB0
-#define EMAC_MACINTSTATMASKED	0xB4
-#define EMAC_MACINTMASKSET	0xB8
-#define EMAC_MACINTMASKCLEAR	0xBC
+#define EMAC_RXINTSTATRAW   0xA0
+#define EMAC_RXINTSTATMASKED    0xA4
+#define EMAC_RXINTMASKSET   0xA8
+#define EMAC_RXINTMASKCLEAR 0xAC
+#define EMAC_MACINTSTATRAW  0xB0
+#define EMAC_MACINTSTATMASKED   0xB4
+#define EMAC_MACINTMASKSET  0xB8
+#define EMAC_MACINTMASKCLEAR    0xBC
 
-#define EMAC_RXMBPENABLE	0x100
-#define EMAC_RXUNICASTSET	0x104
-#define EMAC_RXUNICASTCLEAR	0x108
-#define EMAC_RXMAXLEN		0x10C
-#define EMAC_RXBUFFEROFFSET	0x110
-#define EMAC_RXFILTERLOWTHRESH	0x114
+#define EMAC_RXMBPENABLE    0x100
+#define EMAC_RXUNICASTSET   0x104
+#define EMAC_RXUNICASTCLEAR 0x108
+#define EMAC_RXMAXLEN       0x10C
+#define EMAC_RXBUFFEROFFSET 0x110
+#define EMAC_RXFILTERLOWTHRESH  0x114
 
-#define EMAC_MACCONTROL		0x160
-#define EMAC_MACSTATUS		0x164
-#define EMAC_EMCONTROL		0x168
-#define EMAC_FIFOCONTROL	0x16C
-#define EMAC_MACCONFIG		0x170
-#define EMAC_SOFTRESET		0x174
-#define EMAC_MACSRCADDRLO	0x1D0
-#define EMAC_MACSRCADDRHI	0x1D4
-#define EMAC_MACHASH1		0x1D8
-#define EMAC_MACHASH2		0x1DC
-#define EMAC_MACADDRLO		0x500
-#define EMAC_MACADDRHI		0x504
-#define EMAC_MACINDEX		0x508
+#define EMAC_MACCONTROL     0x160
+#define EMAC_MACSTATUS      0x164
+#define EMAC_EMCONTROL      0x168
+#define EMAC_FIFOCONTROL    0x16C
+#define EMAC_MACCONFIG      0x170
+#define EMAC_SOFTRESET      0x174
+#define EMAC_MACSRCADDRLO   0x1D0
+#define EMAC_MACSRCADDRHI   0x1D4
+#define EMAC_MACHASH1       0x1D8
+#define EMAC_MACHASH2       0x1DC
+#define EMAC_MACADDRLO      0x500
+#define EMAC_MACADDRHI      0x504
+#define EMAC_MACINDEX       0x508
 
 /* EMAC HDP and Completion registors */
-#define EMAC_TXHDP(ch)		(0x600 + (ch * 4))
-#define EMAC_RXHDP(ch)		(0x620 + (ch * 4))
-#define EMAC_TXCP(ch)		(0x640 + (ch * 4))
-#define EMAC_RXCP(ch)		(0x660 + (ch * 4))
+#define EMAC_TXHDP(ch)      (0x600 + (ch * 4))
+#define EMAC_RXHDP(ch)      (0x620 + (ch * 4))
+#define EMAC_TXCP(ch)       (0x640 + (ch * 4))
+#define EMAC_RXCP(ch)       (0x660 + (ch * 4))
 
 /* EMAC statistics registers */
-#define EMAC_RXGOODFRAMES	0x200
-#define EMAC_RXBCASTFRAMES	0x204
-#define EMAC_RXMCASTFRAMES	0x208
-#define EMAC_RXPAUSEFRAMES	0x20C
-#define EMAC_RXCRCERRORS	0x210
-#define EMAC_RXALIGNCODEERRORS	0x214
-#define EMAC_RXOVERSIZED	0x218
-#define EMAC_RXJABBER		0x21C
-#define EMAC_RXUNDERSIZED	0x220
-#define EMAC_RXFRAGMENTS	0x224
-#define EMAC_RXFILTERED		0x228
-#define EMAC_RXQOSFILTERED	0x22C
-#define EMAC_RXOCTETS		0x230
-#define EMAC_TXGOODFRAMES	0x234
-#define EMAC_TXBCASTFRAMES	0x238
-#define EMAC_TXMCASTFRAMES	0x23C
-#define EMAC_TXPAUSEFRAMES	0x240
-#define EMAC_TXDEFERRED		0x244
-#define EMAC_TXCOLLISION	0x248
-#define EMAC_TXSINGLECOLL	0x24C
-#define EMAC_TXMULTICOLL	0x250
-#define EMAC_TXEXCESSIVECOLL	0x254
-#define EMAC_TXLATECOLL		0x258
-#define EMAC_TXUNDERRUN		0x25C
-#define EMAC_TXCARRIERSENSE	0x260
-#define EMAC_TXOCTETS		0x264
-#define EMAC_NETOCTETS		0x280
-#define EMAC_RXSOFOVERRUNS	0x284
-#define EMAC_RXMOFOVERRUNS	0x288
-#define EMAC_RXDMAOVERRUNS	0x28C
+#define EMAC_RXGOODFRAMES   0x200
+#define EMAC_RXBCASTFRAMES  0x204
+#define EMAC_RXMCASTFRAMES  0x208
+#define EMAC_RXPAUSEFRAMES  0x20C
+#define EMAC_RXCRCERRORS    0x210
+#define EMAC_RXALIGNCODEERRORS  0x214
+#define EMAC_RXOVERSIZED    0x218
+#define EMAC_RXJABBER       0x21C
+#define EMAC_RXUNDERSIZED   0x220
+#define EMAC_RXFRAGMENTS    0x224
+#define EMAC_RXFILTERED     0x228
+#define EMAC_RXQOSFILTERED  0x22C
+#define EMAC_RXOCTETS       0x230
+#define EMAC_TXGOODFRAMES   0x234
+#define EMAC_TXBCASTFRAMES  0x238
+#define EMAC_TXMCASTFRAMES  0x23C
+#define EMAC_TXPAUSEFRAMES  0x240
+#define EMAC_TXDEFERRED     0x244
+#define EMAC_TXCOLLISION    0x248
+#define EMAC_TXSINGLECOLL   0x24C
+#define EMAC_TXMULTICOLL    0x250
+#define EMAC_TXEXCESSIVECOLL    0x254
+#define EMAC_TXLATECOLL     0x258
+#define EMAC_TXUNDERRUN     0x25C
+#define EMAC_TXCARRIERSENSE 0x260
+#define EMAC_TXOCTETS       0x264
+#define EMAC_NETOCTETS      0x280
+#define EMAC_RXSOFOVERRUNS  0x284
+#define EMAC_RXMOFOVERRUNS  0x288
+#define EMAC_RXDMAOVERRUNS  0x28C
 
 /* EMAC DM644x control registers */
-#define EMAC_CTRL_EWCTL		(0x4)
-#define EMAC_CTRL_EWINTTCNT	(0x8)
+#define EMAC_CTRL_EWCTL     (0x4)
+#define EMAC_CTRL_EWINTTCNT (0x8)
 
 /* EMAC MDIO related */
 /* Mask & Control defines */
-#define MDIO_CONTROL_CLKDIV	(0xFF)
-#define MDIO_CONTROL_ENABLE	BIT(30)
-#define MDIO_USERACCESS_GO	BIT(31)
-#define MDIO_USERACCESS_WRITE	BIT(30)
-#define MDIO_USERACCESS_READ	(0)
-#define MDIO_USERACCESS_REGADR	(0x1F << 21)
-#define MDIO_USERACCESS_PHYADR	(0x1F << 16)
-#define MDIO_USERACCESS_DATA	(0xFFFF)
-#define MDIO_USERPHYSEL_LINKSEL	BIT(7)
-#define MDIO_VER_MODID		(0xFFFF << 16)
-#define MDIO_VER_REVMAJ		(0xFF   << 8)
-#define MDIO_VER_REVMIN		(0xFF)
+#define MDIO_CONTROL_CLKDIV (0xFF)
+#define MDIO_CONTROL_ENABLE BIT(30)
+#define MDIO_USERACCESS_GO  BIT(31)
+#define MDIO_USERACCESS_WRITE   BIT(30)
+#define MDIO_USERACCESS_READ    (0)
+#define MDIO_USERACCESS_REGADR  (0x1F << 21)
+#define MDIO_USERACCESS_PHYADR  (0x1F << 16)
+#define MDIO_USERACCESS_DATA    (0xFFFF)
+#define MDIO_USERPHYSEL_LINKSEL BIT(7)
+#define MDIO_VER_MODID      (0xFFFF << 16)
+#define MDIO_VER_REVMAJ     (0xFF   << 8)
+#define MDIO_VER_REVMIN     (0xFF)
 
-#define MDIO_USERACCESS(inst)	(0x80 + (inst * 8))
-#define MDIO_USERPHYSEL(inst)	(0x84 + (inst * 8))
-#define MDIO_CONTROL		(0x04)
+#define MDIO_USERACCESS(inst)   (0x80 + (inst * 8))
+#define MDIO_USERPHYSEL(inst)   (0x84 + (inst * 8))
+#define MDIO_CONTROL        (0x04)
 
 /* EMAC DM646X control module registers */
-#define EMAC_DM646X_CMRXINTEN	(0x14)
-#define EMAC_DM646X_CMTXINTEN	(0x18)
+#define EMAC_DM646X_CMRXINTEN   (0x14)
+#define EMAC_DM646X_CMTXINTEN   (0x18)
 
 /* EMAC EOI codes for C0 */
-#define EMAC_DM646X_MAC_EOI_C0_RXEN	(0x01)
-#define EMAC_DM646X_MAC_EOI_C0_TXEN	(0x02)
+#define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01)
+#define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02)
 
 /* EMAC Stats Clear Mask */
 #define EMAC_STATS_CLR_MASK    (0xFFFFFFFF)
@@ -269,9 +269,9 @@ enum {
  * EMAC network buffer data structure
  */
 struct emac_netbufobj {
-	void *buf_token;
-	char *data_ptr;
-	int length;
+    void *buf_token;
+    char *data_ptr;
+    int length;
 };
 
 /** net_pkt_obj: EMAC network packet data structure
@@ -279,10 +279,10 @@ struct emac_netbufobj {
  * EMAC network packet data structure - supports buffer list (for future)
  */
 struct emac_netpktobj {
-	void *pkt_token; /* data token may hold tx/rx chan id */
-	struct emac_netbufobj *buf_list; /* array of network buffer objects */
-	int num_bufs;
-	int pkt_length;
+    void *pkt_token; /* data token may hold tx/rx chan id */
+    struct emac_netbufobj *buf_list; /* array of network buffer objects */
+    int num_bufs;
+    int pkt_length;
 };
 
 /** emac_tx_bd: EMAC TX Buffer descriptor data structure
@@ -290,12 +290,12 @@ struct emac_netpktobj {
  * EMAC TX Buffer descriptor data structure
  */
 struct emac_tx_bd {
-	int h_next;
-	int buff_ptr;
-	int off_b_len;
-	int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
-	struct emac_tx_bd __iomem *next;
-	void *buf_token;
+    int h_next;
+    int buff_ptr;
+    int off_b_len;
+    int mode; /* SOP, EOP, ownership, EOQ, teardown,Qstarv, length */
+    struct emac_tx_bd __iomem *next;
+    void *buf_token;
 };
 
 /** emac_txch: EMAC TX Channel data structure
@@ -303,29 +303,29 @@ struct emac_tx_bd {
  * EMAC TX Channel data structure
  */
 struct emac_txch {
-	/* Config related */
-	rt_uint32_t num_bd;
-	rt_uint32_t service_max;
+    /* Config related */
+    rt_uint32_t num_bd;
+    rt_uint32_t service_max;
 
-	/* CPPI specific */
-	rt_uint32_t alloc_size;
-	void __iomem *bd_mem;
-	struct emac_tx_bd __iomem *bd_pool_head;
-	struct emac_tx_bd __iomem *active_queue_head;
-	struct emac_tx_bd __iomem *active_queue_tail;
-	struct emac_tx_bd __iomem *last_hw_bdprocessed;
-	rt_uint32_t queue_active;
-	rt_uint32_t teardown_pending;
-	rt_uint32_t *tx_complete;
+    /* CPPI specific */
+    rt_uint32_t alloc_size;
+    void __iomem *bd_mem;
+    struct emac_tx_bd __iomem *bd_pool_head;
+    struct emac_tx_bd __iomem *active_queue_head;
+    struct emac_tx_bd __iomem *active_queue_tail;
+    struct emac_tx_bd __iomem *last_hw_bdprocessed;
+    rt_uint32_t queue_active;
+    rt_uint32_t teardown_pending;
+    rt_uint32_t *tx_complete;
 
-	/** statistics */
-	rt_uint32_t proc_count;     /* TX: # of times emac_tx_bdproc is called */
-	rt_uint32_t mis_queued_packets;
-	rt_uint32_t queue_reinit;
-	rt_uint32_t end_of_queue_add;
-	rt_uint32_t out_of_tx_bd;
-	rt_uint32_t no_active_pkts; /* IRQ when there were no packets to process */
-	rt_uint32_t active_queue_count;
+    /** statistics */
+    rt_uint32_t proc_count;     /* TX: # of times emac_tx_bdproc is called */
+    rt_uint32_t mis_queued_packets;
+    rt_uint32_t queue_reinit;
+    rt_uint32_t end_of_queue_add;
+    rt_uint32_t out_of_tx_bd;
+    rt_uint32_t no_active_pkts; /* IRQ when there were no packets to process */
+    rt_uint32_t active_queue_count;
 };
 
 /** emac_rx_bd: EMAC RX Buffer descriptor data structure
@@ -333,13 +333,13 @@ struct emac_txch {
  * EMAC RX Buffer descriptor data structure
  */
 struct emac_rx_bd {
-	int h_next;
-	int buff_ptr;
-	int off_b_len;
-	int mode;
-	struct emac_rx_bd __iomem *next;
-	void *data_ptr;
-	void *buf_token;
+    int h_next;
+    int buff_ptr;
+    int off_b_len;
+    int mode;
+    struct emac_rx_bd __iomem *next;
+    void *data_ptr;
+    void *buf_token;
 };
 
 /** emac_rxch: EMAC RX Channel data structure
@@ -347,68 +347,68 @@ struct emac_rx_bd {
  * EMAC RX Channel data structure
  */
 struct emac_rxch {
-	/* configuration info */
-	rt_uint32_t num_bd;
-	rt_uint32_t service_max;
-	rt_uint32_t buf_size;
-	char mac_addr[6];
+    /* configuration info */
+    rt_uint32_t num_bd;
+    rt_uint32_t service_max;
+    rt_uint32_t buf_size;
+    char mac_addr[6];
 
-	/** CPPI specific */
-	rt_uint32_t alloc_size;
-	void __iomem *bd_mem;
-	struct emac_rx_bd __iomem *bd_pool_head;
-	struct emac_rx_bd __iomem *active_queue_head;
-	struct emac_rx_bd __iomem *active_queue_tail;
-	rt_uint32_t queue_active;
-	rt_uint32_t teardown_pending;
+    /** CPPI specific */
+    rt_uint32_t alloc_size;
+    void __iomem *bd_mem;
+    struct emac_rx_bd __iomem *bd_pool_head;
+    struct emac_rx_bd __iomem *active_queue_head;
+    struct emac_rx_bd __iomem *active_queue_tail;
+    rt_uint32_t queue_active;
+    rt_uint32_t teardown_pending;
 
-	/* packet and buffer objects */
-	struct emac_netpktobj pkt_queue;
-	struct emac_netbufobj buf_queue;
+    /* packet and buffer objects */
+    struct emac_netpktobj pkt_queue;
+    struct emac_netbufobj buf_queue;
 
-	/** statistics */
-	rt_uint32_t proc_count; /* number of times emac_rx_bdproc is called */
-	rt_uint32_t processed_bd;
-	rt_uint32_t recycled_bd;
-	rt_uint32_t out_of_rx_bd;
-	rt_uint32_t out_of_rx_buffers;
-	rt_uint32_t queue_reinit;
-	rt_uint32_t end_of_queue_add;
-	rt_uint32_t end_of_queue;
-	rt_uint32_t mis_queued_packets;
+    /** statistics */
+    rt_uint32_t proc_count; /* number of times emac_rx_bdproc is called */
+    rt_uint32_t processed_bd;
+    rt_uint32_t recycled_bd;
+    rt_uint32_t out_of_rx_bd;
+    rt_uint32_t out_of_rx_buffers;
+    rt_uint32_t queue_reinit;
+    rt_uint32_t end_of_queue_add;
+    rt_uint32_t end_of_queue;
+    rt_uint32_t mis_queued_packets;
 };
 
 struct net_device_stats
 {
-	unsigned long	rx_packets;		/* total packets received	*/
-	unsigned long	tx_packets;		/* total packets transmitted	*/
-	unsigned long	rx_bytes;		/* total bytes received 	*/
-	unsigned long	tx_bytes;		/* total bytes transmitted	*/
-	unsigned long	rx_errors;		/* bad packets received		*/
-	unsigned long	tx_errors;		/* packet transmit problems	*/
-	unsigned long	rx_dropped;		/* no space in linux buffers	*/
-	unsigned long	tx_dropped;		/* no space available in linux	*/
-	unsigned long	multicast;		/* multicast packets received	*/
-	unsigned long	collisions;
+    unsigned long   rx_packets;     /* total packets received   */
+    unsigned long   tx_packets;     /* total packets transmitted    */
+    unsigned long   rx_bytes;       /* total bytes received     */
+    unsigned long   tx_bytes;       /* total bytes transmitted  */
+    unsigned long   rx_errors;      /* bad packets received     */
+    unsigned long   tx_errors;      /* packet transmit problems */
+    unsigned long   rx_dropped;     /* no space in linux buffers    */
+    unsigned long   tx_dropped;     /* no space available in linux  */
+    unsigned long   multicast;      /* multicast packets received   */
+    unsigned long   collisions;
 
-	/* detailed rx_errors: */
-	unsigned long	rx_length_errors;
-	unsigned long	rx_over_errors;		/* receiver ring buff overflow	*/
-	unsigned long	rx_crc_errors;		/* recved pkt with crc error	*/
-	unsigned long	rx_frame_errors;	/* recv'd frame alignment error */
-	unsigned long	rx_fifo_errors;		/* recv'r fifo overrun		*/
-	unsigned long	rx_missed_errors;	/* receiver missed packet	*/
+    /* detailed rx_errors: */
+    unsigned long   rx_length_errors;
+    unsigned long   rx_over_errors;     /* receiver ring buff overflow  */
+    unsigned long   rx_crc_errors;      /* recved pkt with crc error    */
+    unsigned long   rx_frame_errors;    /* recv'd frame alignment error */
+    unsigned long   rx_fifo_errors;     /* recv'r fifo overrun      */
+    unsigned long   rx_missed_errors;   /* receiver missed packet   */
 
-	/* detailed tx_errors */
-	unsigned long	tx_aborted_errors;
-	unsigned long	tx_carrier_errors;
-	unsigned long	tx_fifo_errors;
-	unsigned long	tx_heartbeat_errors;
-	unsigned long	tx_window_errors;
-	
-	/* for cslip etc */
-	unsigned long	rx_compressed;
-	unsigned long	tx_compressed;
+    /* detailed tx_errors */
+    unsigned long   tx_aborted_errors;
+    unsigned long   tx_carrier_errors;
+    unsigned long   tx_fifo_errors;
+    unsigned long   tx_heartbeat_errors;
+    unsigned long   tx_window_errors;
+
+    /* for cslip etc */
+    unsigned long   rx_compressed;
+    unsigned long   tx_compressed;
 };
 
 
@@ -419,44 +419,44 @@ struct net_device_stats
 #define MAX_ADDR_LEN 6
 
 struct emac_priv {
-	/* inherit from ethernet device */
-	struct eth_device parent;
+    /* inherit from ethernet device */
+    struct eth_device parent;
+
+    /* interface address info. */
+    rt_uint8_t  mac_addr[MAX_ADDR_LEN];     /* hw address   */
+    unsigned short      phy_addr;
 
-	/* interface address info. */
-	rt_uint8_t  mac_addr[MAX_ADDR_LEN];		/* hw address	*/
-	unsigned short		phy_addr;
-	
-	struct rt_semaphore tx_lock;
-	struct rt_semaphore rx_lock;
-	void __iomem *remap_addr;
-	rt_uint32_t emac_base_phys;
-	void __iomem *emac_base;
-	void __iomem *ctrl_base;
-	void __iomem *emac_ctrl_ram;
-	void __iomem *mdio_base;
-	rt_uint32_t ctrl_ram_size;
-	rt_uint32_t hw_ram_addr;
-	struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
-	struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
-	rt_uint32_t link; /* 1=link on, 0=link off */
-	rt_uint32_t speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
-	rt_uint32_t duplex; /* Link duplex: 0=Half, 1=Full */
-	rt_uint32_t rx_buf_size;
-	rt_uint32_t isr_count;
-	rt_uint8_t rmii_en;
-	rt_uint8_t version;
-	struct net_device_stats net_dev_stats;
-	rt_uint32_t mac_hash1;
-	rt_uint32_t mac_hash2;
-	rt_uint32_t multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
-	rt_uint32_t rx_addr_type;
-	/* periodic timer required for MDIO polling */
-	struct rt_timer  timer;
-	rt_uint32_t periodic_ticks;
-	rt_uint32_t timer_active;
-	rt_uint32_t phy_mask;
-	/* mii_bus,phy members */
-	struct rt_semaphore lock;
+    struct rt_semaphore tx_lock;
+    struct rt_semaphore rx_lock;
+    void __iomem *remap_addr;
+    rt_uint32_t emac_base_phys;
+    void __iomem *emac_base;
+    void __iomem *ctrl_base;
+    void __iomem *emac_ctrl_ram;
+    void __iomem *mdio_base;
+    rt_uint32_t ctrl_ram_size;
+    rt_uint32_t hw_ram_addr;
+    struct emac_txch *txch[EMAC_DEF_MAX_TX_CH];
+    struct emac_rxch *rxch[EMAC_DEF_MAX_RX_CH];
+    rt_uint32_t link; /* 1=link on, 0=link off */
+    rt_uint32_t speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */
+    rt_uint32_t duplex; /* Link duplex: 0=Half, 1=Full */
+    rt_uint32_t rx_buf_size;
+    rt_uint32_t isr_count;
+    rt_uint8_t rmii_en;
+    rt_uint8_t version;
+    struct net_device_stats net_dev_stats;
+    rt_uint32_t mac_hash1;
+    rt_uint32_t mac_hash2;
+    rt_uint32_t multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS];
+    rt_uint32_t rx_addr_type;
+    /* periodic timer required for MDIO polling */
+    struct rt_timer  timer;
+    rt_uint32_t periodic_ticks;
+    rt_uint32_t timer_active;
+    rt_uint32_t phy_mask;
+    /* mii_bus,phy members */
+    struct rt_semaphore lock;
 };
 
 
diff --git a/bsp/dm365/drivers/davinci_serial.c b/bsp/dm365/drivers/davinci_serial.c
index 1b6b4b944b..96118ac347 100644
--- a/bsp/dm365/drivers/davinci_serial.c
+++ b/bsp/dm365/drivers/davinci_serial.c
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 #include <rtthread.h>
@@ -18,35 +18,35 @@ static struct rt_serial_device davinci_serial_dev0;
 static struct rt_serial_device davinci_serial_dev1;
 
 
-#define LSR_DR		0x01		/* Data ready */
-#define LSR_THRE	0x20		/* Xmit holding register empty */
-//#define	USTAT_TXB_EMPTY		0x02   	/* tx buffer empty */
-#define BPS					115200	/* serial baudrate */
+#define LSR_DR      0x01        /* Data ready */
+#define LSR_THRE    0x20        /* Xmit holding register empty */
+//#define   USTAT_TXB_EMPTY     0x02    /* tx buffer empty */
+#define BPS                 115200  /* serial baudrate */
 
 typedef struct uartport
 {
-	volatile rt_uint32_t rbr;
-	volatile rt_uint32_t ier;
-	volatile rt_uint32_t fcr;
-	volatile rt_uint32_t lcr;
-	volatile rt_uint32_t mcr;
-	volatile rt_uint32_t lsr;
-	volatile rt_uint32_t msr;
-	volatile rt_uint32_t scr;
-	volatile rt_uint32_t dll;
-	volatile rt_uint32_t dlh;
-	
-	volatile rt_uint32_t res[2];
-	volatile rt_uint32_t pwremu_mgmt;
-	volatile rt_uint32_t mdr;
+    volatile rt_uint32_t rbr;
+    volatile rt_uint32_t ier;
+    volatile rt_uint32_t fcr;
+    volatile rt_uint32_t lcr;
+    volatile rt_uint32_t mcr;
+    volatile rt_uint32_t lsr;
+    volatile rt_uint32_t msr;
+    volatile rt_uint32_t scr;
+    volatile rt_uint32_t dll;
+    volatile rt_uint32_t dlh;
+
+    volatile rt_uint32_t res[2];
+    volatile rt_uint32_t pwremu_mgmt;
+    volatile rt_uint32_t mdr;
 }uartport;
 
 #define thr rbr
 #define iir fcr
 
-#define UART0	((struct uartport *)DAVINCI_UART0_BASE)
+#define UART0   ((struct uartport *)DAVINCI_UART0_BASE)
 
-#define UART1	((struct uartport *)DM365_UART1_BASE)
+#define UART1   ((struct uartport *)DM365_UART1_BASE)
 
 
 /**
@@ -54,8 +54,8 @@ typedef struct uartport
  */
 void rt_davinci_serial_handler(int vector, void *param)
 {
-	struct rt_serial_device *dev = (struct rt_serial_device *)param;
-	rt_hw_serial_isr(dev, RT_SERIAL_EVENT_RX_IND);
+    struct rt_serial_device *dev = (struct rt_serial_device *)param;
+    rt_hw_serial_isr(dev, RT_SERIAL_EVENT_RX_IND);
 }
 
 /**
@@ -70,23 +70,23 @@ static rt_err_t davinci_uart_configure(struct rt_serial_device *serial,
 static rt_err_t davinci_uart_control(struct rt_serial_device *serial,
                               int cmd, void *arg)
 {
-	uartport *uart = serial->parent.user_data;
+    uartport *uart = serial->parent.user_data;
 
     switch (cmd)
     {
     case RT_DEVICE_CTRL_CLR_INT:
         /* disable rx irq */
-		if (uart == UART0)
-			rt_hw_interrupt_mask(IRQ_UARTINT0);
-		else if (uart == UART1)
-			rt_hw_interrupt_mask(IRQ_UARTINT1);
+        if (uart == UART0)
+            rt_hw_interrupt_mask(IRQ_UARTINT0);
+        else if (uart == UART1)
+            rt_hw_interrupt_mask(IRQ_UARTINT1);
         break;
     case RT_DEVICE_CTRL_SET_INT:
         /* enable rx irq */
-		if (uart == UART0)
-			rt_hw_interrupt_umask(IRQ_UARTINT0);
-		else if (uart == UART1)
-			rt_hw_interrupt_umask(IRQ_UARTINT1);
+        if (uart == UART0)
+            rt_hw_interrupt_umask(IRQ_UARTINT0);
+        else if (uart == UART1)
+            rt_hw_interrupt_umask(IRQ_UARTINT1);
         break;
     }
 
@@ -96,10 +96,10 @@ static rt_err_t davinci_uart_control(struct rt_serial_device *serial,
 static int davinci_uart_putc(struct rt_serial_device *serial, char c)
 {
     rt_uint32_t level;
-	uartport *uart = serial->parent.user_data;
+    uartport *uart = serial->parent.user_data;
 
     while (!(uart->lsr & LSR_THRE));
-	uart->thr = c;
+    uart->thr = c;
 
     return 1;
 }
@@ -107,16 +107,16 @@ static int davinci_uart_putc(struct rt_serial_device *serial, char c)
 static int davinci_uart_getc(struct rt_serial_device *serial)
 {
     int result;
-	uartport *uart = serial->parent.user_data;
+    uartport *uart = serial->parent.user_data;
 
     if (uart->lsr & LSR_DR)
-	{
-		result = uart->rbr & 0xff;
-	}
-	else
-	{
-		result = -1;
-	}
+    {
+        result = uart->rbr & 0xff;
+    }
+    else
+    {
+        result = -1;
+    }
 
     return result;
 }
@@ -131,78 +131,78 @@ static const struct rt_uart_ops davinci_uart_ops =
 
 void davinci_uart0_init(void)
 {
-	rt_uint32_t divisor;
+    rt_uint32_t divisor;
 
-	divisor = (24000000 + (115200 * (16 / 2))) / (16 * 115200);
-	UART0->ier = 0;
-	UART0->lcr = 0x83; //8N1
-	UART0->dll = 0;
-	UART0->dlh = 0;
-	UART0->lcr = 0x03;
-	UART0->mcr = 0x03; //RTS,CTS
-	UART0->fcr = 0x07; //FIFO
-	UART0->lcr = 0x83;
-	UART0->dll = divisor & 0xff;
-	UART0->dlh = (divisor >> 8) & 0xff;
-	UART0->lcr = 0x03;
-	UART0->mdr = 0; //16x over-sampling
-	UART0->pwremu_mgmt = 0x6000;
-	rt_hw_interrupt_install(IRQ_UARTINT0, rt_davinci_serial_handler, 
-							(void *)&davinci_serial_dev0, "UART0");
-	rt_hw_interrupt_mask(IRQ_UARTINT0);
-	UART0->ier = 0x05;
+    divisor = (24000000 + (115200 * (16 / 2))) / (16 * 115200);
+    UART0->ier = 0;
+    UART0->lcr = 0x83; //8N1
+    UART0->dll = 0;
+    UART0->dlh = 0;
+    UART0->lcr = 0x03;
+    UART0->mcr = 0x03; //RTS,CTS
+    UART0->fcr = 0x07; //FIFO
+    UART0->lcr = 0x83;
+    UART0->dll = divisor & 0xff;
+    UART0->dlh = (divisor >> 8) & 0xff;
+    UART0->lcr = 0x03;
+    UART0->mdr = 0; //16x over-sampling
+    UART0->pwremu_mgmt = 0x6000;
+    rt_hw_interrupt_install(IRQ_UARTINT0, rt_davinci_serial_handler,
+                            (void *)&davinci_serial_dev0, "UART0");
+    rt_hw_interrupt_mask(IRQ_UARTINT0);
+    UART0->ier = 0x05;
 }
 
 void davinci_uart_gpio_init()
 {
-	rt_uint32_t val;
+    rt_uint32_t val;
 
-	val = davinci_readl(PINMUX3);
-	val &= 0xf3ffffff; /* gio23 RS485_CTRL */
-	val |= 0x60000000; /*UART1_TXD (gio25)*/
-	davinci_writel(val, PINMUX3);
-	val = davinci_readl(PINMUX4);
-	val |= 0x0000c000; /* UART1_RXD (gio34) */
-	davinci_writel(val, PINMUX4);
+    val = davinci_readl(PINMUX3);
+    val &= 0xf3ffffff; /* gio23 RS485_CTRL */
+    val |= 0x60000000; /*UART1_TXD (gio25)*/
+    davinci_writel(val, PINMUX3);
+    val = davinci_readl(PINMUX4);
+    val |= 0x0000c000; /* UART1_RXD (gio34) */
+    davinci_writel(val, PINMUX4);
 
-	val = davinci_readl(DAVINCI_GPIO_BASE + 0x10);
-	val &= ~(1 << 23);
-	davinci_writel(val, DAVINCI_GPIO_BASE + 0x10);
-	davinci_writel((1<<23), DAVINCI_GPIO_BASE + 0x1C);
+    val = davinci_readl(DAVINCI_GPIO_BASE + 0x10);
+    val &= ~(1 << 23);
+    davinci_writel(val, DAVINCI_GPIO_BASE + 0x10);
+    davinci_writel((1<<23), DAVINCI_GPIO_BASE + 0x1C);
 }
 
 void davinci_uart1_init(void)
 {
-	rt_uint32_t divisor;
-	rt_uint32_t freq;
-	rt_uint32_t baudrate;
-	struct clk *clk;
+    rt_uint32_t divisor;
+    rt_uint32_t freq;
+    rt_uint32_t baudrate;
+    struct clk *clk;
+
+    davinci_uart_gpio_init();
+    psc_change_state(DAVINCI_DM365_LPSC_UART1, PSC_ENABLE);
+    clk = clk_get("UART1");
+    freq = clk_get_rate(clk);
 
-	davinci_uart_gpio_init();
-	psc_change_state(DAVINCI_DM365_LPSC_UART1, PSC_ENABLE);
-	clk = clk_get("UART1");
-	freq = clk_get_rate(clk);
+    baudrate = 9600;
+    divisor = (freq + (baudrate * (16 / 2))) / (16 * baudrate);
+    UART1->ier = 0;
+    UART1->lcr = 0x87; //8N2, 0x83 8N1
+    UART1->dll = 0;
+    UART1->dlh = 0;
+    UART1->lcr = 0x07;
+    UART1->mcr = 0x03; //RTS,CTS
+    UART1->fcr = 0x07; //FIFO
+    UART1->lcr = 0x87;
+    UART1->dll = divisor & 0xff;
+    UART1->dlh = (divisor >> 8) & 0xff;
+    UART1->lcr = 0x07;
+    UART1->mdr = 0; //16x over-sampling
+    UART1->pwremu_mgmt = 0x6000;
 
-	baudrate = 9600;
-	divisor = (freq + (baudrate * (16 / 2))) / (16 * baudrate);
-	UART1->ier = 0;
-	UART1->lcr = 0x87; //8N2, 0x83 8N1
-	UART1->dll = 0;
-	UART1->dlh = 0;
-	UART1->lcr = 0x07;
-	UART1->mcr = 0x03; //RTS,CTS
-	UART1->fcr = 0x07; //FIFO
-	UART1->lcr = 0x87;
-	UART1->dll = divisor & 0xff;
-	UART1->dlh = (divisor >> 8) & 0xff;
-	UART1->lcr = 0x07;
-	UART1->mdr = 0; //16x over-sampling
-	UART1->pwremu_mgmt = 0x6000;
-	
-	rt_hw_interrupt_install(IRQ_UARTINT1, rt_davinci_serial_handler, 
-							(void *)&davinci_serial_dev1, "UART1");
-	rt_hw_interrupt_mask(IRQ_UARTINT1);
-	UART1->ier = 0x05;
+    rt_hw_interrupt_install(IRQ_UARTINT1, rt_davinci_serial_handler,
+                            (void *)&davinci_serial_dev1, "UART1");
+    rt_hw_interrupt_mask(IRQ_UARTINT1);
+    UART1->ier = 0x05;
 }
 
 
@@ -211,39 +211,39 @@ void davinci_uart1_init(void)
  */
 int rt_hw_uart_init(void)
 {
-	davinci_serial_dev0.ops = &davinci_uart_ops;
+    davinci_serial_dev0.ops = &davinci_uart_ops;
     //davinci_serial_dev0.config = RT_SERIAL_CONFIG_DEFAULT;
-	davinci_serial_dev0.config.baud_rate = BAUD_RATE_115200;
+    davinci_serial_dev0.config.baud_rate = BAUD_RATE_115200;
     davinci_serial_dev0.config.bit_order = BIT_ORDER_LSB;
     davinci_serial_dev0.config.data_bits = DATA_BITS_8;
     davinci_serial_dev0.config.parity = PARITY_NONE;
     davinci_serial_dev0.config.stop_bits = STOP_BITS_1;
     davinci_serial_dev0.config.invert = NRZ_NORMAL;
-	davinci_serial_dev0.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    davinci_serial_dev0.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&davinci_serial_dev0, "uart0",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
                           UART0);
-	davinci_uart0_init();
+    davinci_uart0_init();
 
-	davinci_serial_dev1.ops = &davinci_uart_ops;
+    davinci_serial_dev1.ops = &davinci_uart_ops;
     //davinci_serial_dev1.config = RT_SERIAL_CONFIG_DEFAULT;
-	davinci_serial_dev1.config.baud_rate = BAUD_RATE_115200;
+    davinci_serial_dev1.config.baud_rate = BAUD_RATE_115200;
     davinci_serial_dev1.config.bit_order = BIT_ORDER_LSB;
     davinci_serial_dev1.config.data_bits = DATA_BITS_8;
     davinci_serial_dev1.config.parity = PARITY_NONE;
     davinci_serial_dev1.config.stop_bits = STOP_BITS_1;
     davinci_serial_dev1.config.invert = NRZ_NORMAL;
-	davinci_serial_dev1.config.bufsz = RT_SERIAL_RB_BUFSZ;
+    davinci_serial_dev1.config.bufsz = RT_SERIAL_RB_BUFSZ;
 
     /* register vcom device */
     rt_hw_serial_register(&davinci_serial_dev1, "uart1",
                           RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
                           UART1);
-	davinci_uart1_init();
+    davinci_uart1_init();
 
-	return 0;
+    return 0;
 }
 
 INIT_BOARD_EXPORT(rt_hw_uart_init);
diff --git a/bsp/dm365/drivers/gpio.c b/bsp/dm365/drivers/gpio.c
index 47c40b2e19..b226c736c8 100644
--- a/bsp/dm365/drivers/gpio.c
+++ b/bsp/dm365/drivers/gpio.c
@@ -4,159 +4,159 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 #include <rtthread.h>
 #include "gpio.h"
 
-#define GPIO0_BASE			(DAVINCI_GPIO_BASE + 0x10)
-#define GPIO1_BASE			(DAVINCI_GPIO_BASE + 0x38)
-#define GPIO2_BASE			(DAVINCI_GPIO_BASE + 0x60)
-#define GPIO3_BASE			(DAVINCI_GPIO_BASE + 0x88)
+#define GPIO0_BASE          (DAVINCI_GPIO_BASE + 0x10)
+#define GPIO1_BASE          (DAVINCI_GPIO_BASE + 0x38)
+#define GPIO2_BASE          (DAVINCI_GPIO_BASE + 0x60)
+#define GPIO3_BASE          (DAVINCI_GPIO_BASE + 0x88)
 
 
 static unsigned int dm365_gpio_base = (unsigned int)GPIO0_BASE;
 
-#define GPIO_OE			(dm365_gpio_base + 0x00)
-#define GPIO_DATAIN		(dm365_gpio_base + 0x10)
-#define GPIO_DATAOUT		(dm365_gpio_base + 0x04)
-#define GPIO_CLROUT		(dm365_gpio_base + 0x0C)
-#define GPIO_SETOUT		(dm365_gpio_base + 0x08)
+#define GPIO_OE         (dm365_gpio_base + 0x00)
+#define GPIO_DATAIN     (dm365_gpio_base + 0x10)
+#define GPIO_DATAOUT        (dm365_gpio_base + 0x04)
+#define GPIO_CLROUT     (dm365_gpio_base + 0x0C)
+#define GPIO_SETOUT     (dm365_gpio_base + 0x08)
 
-#define gpio_dirin(n)		*(volatile unsigned int *)((GPIO_OE)) |= 1<<(n)
-#define gpio_dirout(n)	*(volatile unsigned int *)((GPIO_OE)) &= ~(1u<<(n))
-#define gpio_set(n)		*(volatile unsigned int *)((GPIO_SETOUT)) = 1<<(n)
-#define gpio_clr(n)		*(volatile unsigned int *)((GPIO_CLROUT)) = 1<<(n)
-#define gpio_get(n)		( ( *(volatile unsigned int *)((GPIO_DATAIN)) & (1<<(n)) ) ? 1 : 0 )
+#define gpio_dirin(n)       *(volatile unsigned int *)((GPIO_OE)) |= 1<<(n)
+#define gpio_dirout(n)  *(volatile unsigned int *)((GPIO_OE)) &= ~(1u<<(n))
+#define gpio_set(n)     *(volatile unsigned int *)((GPIO_SETOUT)) = 1<<(n)
+#define gpio_clr(n)     *(volatile unsigned int *)((GPIO_CLROUT)) = 1<<(n)
+#define gpio_get(n)     ( ( *(volatile unsigned int *)((GPIO_DATAIN)) & (1<<(n)) ) ? 1 : 0 )
 
  #define GPIO_GRP_MASK (5)
- 
+
 static int gpio_to_base(unsigned int gpio)
 {
-	unsigned int grp_idx;
-	int ret;
+    unsigned int grp_idx;
+    int ret;
 
-	grp_idx = gpio >> GPIO_GRP_MASK;  
+    grp_idx = gpio >> GPIO_GRP_MASK;
 
-	switch (grp_idx) {
-		case 0:
-			dm365_gpio_base = (unsigned int)GPIO0_BASE;
-			ret = 0;
-			break;
-		case 1:
-			dm365_gpio_base = (unsigned int)GPIO1_BASE;
-			ret = 0;
-			break;
-		case 2:
-			dm365_gpio_base = (unsigned int)GPIO2_BASE;
-			ret = 0;
-			break;    
-		case 3:
-			dm365_gpio_base = (unsigned int)GPIO3_BASE;
-			ret = 0;
-			break;   
-		default:
-			ret =-RT_EIO;
-			break;      
-	}
-	return ret;
+    switch (grp_idx) {
+        case 0:
+            dm365_gpio_base = (unsigned int)GPIO0_BASE;
+            ret = 0;
+            break;
+        case 1:
+            dm365_gpio_base = (unsigned int)GPIO1_BASE;
+            ret = 0;
+            break;
+        case 2:
+            dm365_gpio_base = (unsigned int)GPIO2_BASE;
+            ret = 0;
+            break;
+        case 3:
+            dm365_gpio_base = (unsigned int)GPIO3_BASE;
+            ret = 0;
+            break;
+        default:
+            ret =-RT_EIO;
+            break;
+    }
+    return ret;
 }
 
 
 int gpio_direction_input(unsigned int gpio)
 {
-	unsigned int offset;
-	int ret=0;
+    unsigned int offset;
+    int ret=0;
 
-	rt_ubase_t temp = rt_hw_interrupt_disable();
-	ret = gpio_to_base(gpio); 
-	if (ret < 0) {
-		goto gpio_free;
-	}
-	offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
+    rt_ubase_t temp = rt_hw_interrupt_disable();
+    ret = gpio_to_base(gpio);
+    if (ret < 0) {
+        goto gpio_free;
+    }
+    offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
 
-	gpio_dirin(offset);
+    gpio_dirin(offset);
 
 gpio_free:
-	rt_hw_interrupt_enable(temp);
+    rt_hw_interrupt_enable(temp);
 
-	return ret;
+    return ret;
 }
 
 int gpio_direction_output(unsigned int gpio, int value)
 {
-	unsigned int offset;
-	int ret=0;
+    unsigned int offset;
+    int ret=0;
 
-	rt_ubase_t temp = rt_hw_interrupt_disable();
-	ret = gpio_to_base(gpio); 
-	if (ret < 0) {
-		goto gpio_free;
-	}
+    rt_ubase_t temp = rt_hw_interrupt_disable();
+    ret = gpio_to_base(gpio);
+    if (ret < 0) {
+        goto gpio_free;
+    }
 
-	offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
+    offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
 
-	if (value) {
-		gpio_set(offset);
-	}
-	else {
-		gpio_clr(offset);
-	}
+    if (value) {
+        gpio_set(offset);
+    }
+    else {
+        gpio_clr(offset);
+    }
 
-	gpio_dirout(offset);
+    gpio_dirout(offset);
 
 gpio_free:
-	rt_hw_interrupt_enable(temp);
+    rt_hw_interrupt_enable(temp);
 
-	return ret;
+    return ret;
 }
 
 int  gpio_set_value(unsigned int gpio, int value)
 {
-	unsigned int offset;
-	int ret=0;
+    unsigned int offset;
+    int ret=0;
 
-	rt_ubase_t temp = rt_hw_interrupt_disable();
-	ret = gpio_to_base(gpio); 
-	if (ret < 0) {
-		goto gpio_free;
-	}
+    rt_ubase_t temp = rt_hw_interrupt_disable();
+    ret = gpio_to_base(gpio);
+    if (ret < 0) {
+        goto gpio_free;
+    }
 
-	offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
+    offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
 
-	if (value) {
-		gpio_set(offset);
-	}
-	else {
-		gpio_clr(offset);
-	}
+    if (value) {
+        gpio_set(offset);
+    }
+    else {
+        gpio_clr(offset);
+    }
 
 gpio_free:
-	rt_hw_interrupt_enable(temp);
+    rt_hw_interrupt_enable(temp);
 
-	return ret;
+    return ret;
 }
 
 int gpio_get_value(unsigned int gpio)
 {
-	unsigned int offset;
-	int ret=0;
+    unsigned int offset;
+    int ret=0;
 
-	rt_ubase_t temp = rt_hw_interrupt_disable();
-	ret = gpio_to_base(gpio); 
-	if (ret < 0) {
-		goto gpio_free;
-	}
+    rt_ubase_t temp = rt_hw_interrupt_disable();
+    ret = gpio_to_base(gpio);
+    if (ret < 0) {
+        goto gpio_free;
+    }
 
-	offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
-	ret = gpio_get(offset);
+    offset =  gpio & ((1 << GPIO_GRP_MASK) -1);
+    ret = gpio_get(offset);
 
 gpio_free:
-	rt_hw_interrupt_enable(temp);
+    rt_hw_interrupt_enable(temp);
 
-	return ret;
+    return ret;
 }
 
 
diff --git a/bsp/dm365/drivers/gpio.h b/bsp/dm365/drivers/gpio.h
index 5e648596ee..a6c8265648 100644
--- a/bsp/dm365/drivers/gpio.h
+++ b/bsp/dm365/drivers/gpio.h
@@ -4,34 +4,34 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
-#ifndef	__DM365_GPIO_H
-#define	__DM365_GPIO_H
+#ifndef __DM365_GPIO_H
+#define __DM365_GPIO_H
 #include <dm36x.h>
 
-#define	GPIO(X)		(X)		
+#define GPIO(X)     (X)
 
 
-#define get_io(r)			*((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r)))
-#define set_io(r,v)		*((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) = (v)
-#define and_io(r,v)		*((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) &= (v)
-#define or_io(r,v)			*((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) |= (v)
+#define get_io(r)           *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r)))
+#define set_io(r,v)     *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) = (v)
+#define and_io(r,v)     *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) &= (v)
+#define or_io(r,v)          *((volatile u_int *)(TI81XX_L4_SLOW_IO_ADDRESS(r))) |= (v)
 
-#define v_get_io(r)			*((volatile u_int *)(r))
-#define v_set_io(r,v)		*((volatile u_int *)(r)) = (v)
-#define v_and_io(r,v)		*((volatile u_int *)(r)) &= (v)
-#define v_or_io(r,v)			*((volatile u_int *)(r)) |= (v)
+#define v_get_io(r)         *((volatile u_int *)(r))
+#define v_set_io(r,v)       *((volatile u_int *)(r)) = (v)
+#define v_and_io(r,v)       *((volatile u_int *)(r)) &= (v)
+#define v_or_io(r,v)            *((volatile u_int *)(r)) |= (v)
 
 enum gpio_intr_mode
 {
     LEVELDETECT_LOW = 0,
     LEVELDETECT_HIGH,
-    RISINGDETECT,  
+    RISINGDETECT,
     FALLINGDETECT,
-    EDGEDETECT	//both rising-edge and falling-edge detect
+    EDGEDETECT  //both rising-edge and falling-edge detect
 };
 
 enum gpio_intr_req
@@ -42,10 +42,10 @@ enum gpio_intr_req
 
 enum gpio_intr_num
 {
-	GPIOINT0A = 96,
-	GPIOINT0B,
-	GPIOINT1A,
-	GPIOINT1B, 
+    GPIOINT0A = 96,
+    GPIOINT0B,
+    GPIOINT1A,
+    GPIOINT1B,
 };
 
 enum pin_func_mod
@@ -56,4 +56,4 @@ enum pin_func_mod
     IIC_MOD=0x20
 };
 
-#endif				/* __TI814X_GPIO_H */
+#endif              /* __TI814X_GPIO_H */
diff --git a/bsp/dm365/drivers/i2c-davinci.c b/bsp/dm365/drivers/i2c-davinci.c
index 8c67cfce80..6da4e72d6c 100644
--- a/bsp/dm365/drivers/i2c-davinci.c
+++ b/bsp/dm365/drivers/i2c-davinci.c
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 #include <rtthread.h>
@@ -13,61 +13,61 @@
 #include <dm36x.h>
 
 /* ----- global defines ----------------------------------------------- */
-#define BIT(nr)			(1UL << (nr))
+#define BIT(nr)         (1UL << (nr))
 
-#define DAVINCI_I2C_TIMEOUT	(1*RT_TICK_PER_SECOND)
-#define DAVINCI_I2C_MAX_TRIES	2
+#define DAVINCI_I2C_TIMEOUT (1*RT_TICK_PER_SECOND)
+#define DAVINCI_I2C_MAX_TRIES   2
 #define I2C_DAVINCI_INTR_ALL    (DAVINCI_I2C_IMR_AAS | \
-				 DAVINCI_I2C_IMR_SCD | \
-				 DAVINCI_I2C_IMR_ARDY | \
-				 DAVINCI_I2C_IMR_NACK | \
-				 DAVINCI_I2C_IMR_AL)
+                 DAVINCI_I2C_IMR_SCD | \
+                 DAVINCI_I2C_IMR_ARDY | \
+                 DAVINCI_I2C_IMR_NACK | \
+                 DAVINCI_I2C_IMR_AL)
 
-#define DAVINCI_I2C_OAR_REG	0x00
-#define DAVINCI_I2C_IMR_REG	0x04
-#define DAVINCI_I2C_STR_REG	0x08
-#define DAVINCI_I2C_CLKL_REG	0x0c
-#define DAVINCI_I2C_CLKH_REG	0x10
-#define DAVINCI_I2C_CNT_REG	0x14
-#define DAVINCI_I2C_DRR_REG	0x18
-#define DAVINCI_I2C_SAR_REG	0x1c
-#define DAVINCI_I2C_DXR_REG	0x20
-#define DAVINCI_I2C_MDR_REG	0x24
-#define DAVINCI_I2C_IVR_REG	0x28
-#define DAVINCI_I2C_EMDR_REG	0x2c
-#define DAVINCI_I2C_PSC_REG	0x30
+#define DAVINCI_I2C_OAR_REG 0x00
+#define DAVINCI_I2C_IMR_REG 0x04
+#define DAVINCI_I2C_STR_REG 0x08
+#define DAVINCI_I2C_CLKL_REG    0x0c
+#define DAVINCI_I2C_CLKH_REG    0x10
+#define DAVINCI_I2C_CNT_REG 0x14
+#define DAVINCI_I2C_DRR_REG 0x18
+#define DAVINCI_I2C_SAR_REG 0x1c
+#define DAVINCI_I2C_DXR_REG 0x20
+#define DAVINCI_I2C_MDR_REG 0x24
+#define DAVINCI_I2C_IVR_REG 0x28
+#define DAVINCI_I2C_EMDR_REG    0x2c
+#define DAVINCI_I2C_PSC_REG 0x30
 
-#define DAVINCI_I2C_IVR_AAS	0x07
-#define DAVINCI_I2C_IVR_SCD	0x06
-#define DAVINCI_I2C_IVR_XRDY	0x05
-#define DAVINCI_I2C_IVR_RDR	0x04
-#define DAVINCI_I2C_IVR_ARDY	0x03
-#define DAVINCI_I2C_IVR_NACK	0x02
-#define DAVINCI_I2C_IVR_AL	0x01
+#define DAVINCI_I2C_IVR_AAS 0x07
+#define DAVINCI_I2C_IVR_SCD 0x06
+#define DAVINCI_I2C_IVR_XRDY    0x05
+#define DAVINCI_I2C_IVR_RDR 0x04
+#define DAVINCI_I2C_IVR_ARDY    0x03
+#define DAVINCI_I2C_IVR_NACK    0x02
+#define DAVINCI_I2C_IVR_AL  0x01
 
-#define DAVINCI_I2C_STR_BB	BIT(12)
-#define DAVINCI_I2C_STR_RSFULL	BIT(11)
-#define DAVINCI_I2C_STR_SCD	BIT(5)
-#define DAVINCI_I2C_STR_ARDY	BIT(2)
-#define DAVINCI_I2C_STR_NACK	BIT(1)
-#define DAVINCI_I2C_STR_AL	BIT(0)
+#define DAVINCI_I2C_STR_BB  BIT(12)
+#define DAVINCI_I2C_STR_RSFULL  BIT(11)
+#define DAVINCI_I2C_STR_SCD BIT(5)
+#define DAVINCI_I2C_STR_ARDY    BIT(2)
+#define DAVINCI_I2C_STR_NACK    BIT(1)
+#define DAVINCI_I2C_STR_AL  BIT(0)
 
-#define DAVINCI_I2C_MDR_NACK	BIT(15)
-#define DAVINCI_I2C_MDR_STT	BIT(13)
-#define DAVINCI_I2C_MDR_STP	BIT(11)
-#define DAVINCI_I2C_MDR_MST	BIT(10)
-#define DAVINCI_I2C_MDR_TRX	BIT(9)
-#define DAVINCI_I2C_MDR_XA	BIT(8)
-#define DAVINCI_I2C_MDR_RM	BIT(7)
-#define DAVINCI_I2C_MDR_IRS	BIT(5)
+#define DAVINCI_I2C_MDR_NACK    BIT(15)
+#define DAVINCI_I2C_MDR_STT BIT(13)
+#define DAVINCI_I2C_MDR_STP BIT(11)
+#define DAVINCI_I2C_MDR_MST BIT(10)
+#define DAVINCI_I2C_MDR_TRX BIT(9)
+#define DAVINCI_I2C_MDR_XA  BIT(8)
+#define DAVINCI_I2C_MDR_RM  BIT(7)
+#define DAVINCI_I2C_MDR_IRS BIT(5)
 
-#define DAVINCI_I2C_IMR_AAS	BIT(6)
-#define DAVINCI_I2C_IMR_SCD	BIT(5)
-#define DAVINCI_I2C_IMR_XRDY	BIT(4)
-#define DAVINCI_I2C_IMR_RRDY	BIT(3)
-#define DAVINCI_I2C_IMR_ARDY	BIT(2)
-#define DAVINCI_I2C_IMR_NACK	BIT(1)
-#define DAVINCI_I2C_IMR_AL	BIT(0)
+#define DAVINCI_I2C_IMR_AAS BIT(6)
+#define DAVINCI_I2C_IMR_SCD BIT(5)
+#define DAVINCI_I2C_IMR_XRDY    BIT(4)
+#define DAVINCI_I2C_IMR_RRDY    BIT(3)
+#define DAVINCI_I2C_IMR_ARDY    BIT(2)
+#define DAVINCI_I2C_IMR_NACK    BIT(1)
+#define DAVINCI_I2C_IMR_AL  BIT(0)
 
 #ifdef RT_EDMA_DEBUG
 #define i2c_dbg(fmt, ...)  rt_kprintf(fmt, ##__VA_ARGS__)
@@ -77,42 +77,42 @@
 
 
 struct davinci_i2c_dev {
-	void		*base;
-	struct rt_semaphore  completion;
-	struct clk  *clk;
-	int         cmd_err;
-	rt_uint8_t  *buf;
-	rt_uint32_t      buf_len;
-	int         irq;
-	int         stop;
-	rt_uint8_t  terminate;
-	rt_uint32_t bus_freq;
-	rt_uint32_t bus_delay;
-	struct rt_i2c_bus_device *bus;
+    void        *base;
+    struct rt_semaphore  completion;
+    struct clk  *clk;
+    int         cmd_err;
+    rt_uint8_t  *buf;
+    rt_uint32_t      buf_len;
+    int         irq;
+    int         stop;
+    rt_uint8_t  terminate;
+    rt_uint32_t bus_freq;
+    rt_uint32_t bus_delay;
+    struct rt_i2c_bus_device *bus;
 };
 
 static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
-					 int reg, rt_uint16_t val)
+                     int reg, rt_uint16_t val)
 {
-	davinci_writew(val, i2c_dev->base + reg);
+    davinci_writew(val, i2c_dev->base + reg);
 }
 
 static inline rt_uint16_t davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
 {
-	return davinci_readw(i2c_dev->base + reg);
+    return davinci_readw(i2c_dev->base + reg);
 }
 
 static void udelay (rt_uint32_t us)
 {
-	rt_int32_t i;
-	for (; us > 0; us--)
-	{
-		i = 50000;
-		while(i > 0)
-		{
-			i--;
-		}
-	}
+    rt_int32_t i;
+    for (; us > 0; us--)
+    {
+        i = 50000;
+        while(i > 0)
+        {
+            i--;
+        }
+    }
 }
 
 
@@ -120,17 +120,17 @@ static void udelay (rt_uint32_t us)
 /* Generate a pulse on the i2c clock pin. */
 static void generic_i2c_clock_pulse(unsigned int scl_pin)
 {
-	rt_uint16_t i;
+    rt_uint16_t i;
 
-	if (scl_pin) {
-		/* Send high and low on the SCL line */
-		for (i = 0; i < 9; i++) {
-			gpio_set_value(scl_pin, 0);
-			udelay(20);
-			gpio_set_value(scl_pin, 1);
-			udelay(20);
-		}
-	}
+    if (scl_pin) {
+        /* Send high and low on the SCL line */
+        for (i = 0; i < 9; i++) {
+            gpio_set_value(scl_pin, 0);
+            udelay(20);
+            gpio_set_value(scl_pin, 1);
+            udelay(20);
+        }
+    }
 }
 #endif
 
@@ -139,78 +139,78 @@ static void generic_i2c_clock_pulse(unsigned int scl_pin)
  */
 static void i2c_recover_bus(struct davinci_i2c_dev *dev)
 {
-	rt_uint32_t flag = 0;
+    rt_uint32_t flag = 0;
 
-	i2c_dbg("initiating i2c bus recovery\n");
-	/* Send NACK to the slave */
-	flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
-	flag |=  DAVINCI_I2C_MDR_NACK;
-	/* write the data into mode register */
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
+    i2c_dbg("initiating i2c bus recovery\n");
+    /* Send NACK to the slave */
+    flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
+    flag |=  DAVINCI_I2C_MDR_NACK;
+    /* write the data into mode register */
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 #if 0
-	if (pdata)
-		generic_i2c_clock_pulse(pdata->scl_pin);
+    if (pdata)
+        generic_i2c_clock_pulse(pdata->scl_pin);
 #endif
-	/* Send STOP */
-	flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
-	flag |= DAVINCI_I2C_MDR_STP;
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
+    /* Send STOP */
+    flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
+    flag |= DAVINCI_I2C_MDR_STP;
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 }
 
 static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
-								int val)
+                                int val)
 {
-	rt_uint16_t w;
+    rt_uint16_t w;
 
-	w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
-	if (!val)	/* put I2C into reset */
-		w &= ~DAVINCI_I2C_MDR_IRS;
-	else		/* take I2C out of reset */
-		w |= DAVINCI_I2C_MDR_IRS;
+    w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
+    if (!val)   /* put I2C into reset */
+        w &= ~DAVINCI_I2C_MDR_IRS;
+    else        /* take I2C out of reset */
+        w |= DAVINCI_I2C_MDR_IRS;
 
-	davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
+    davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
 }
 
 static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
 {
-	rt_uint16_t psc;
-	rt_uint32_t clk;
-	rt_uint32_t d;
-	rt_uint32_t clkh;
-	rt_uint32_t clkl;
-	rt_uint32_t input_clock = clk_get_rate(dev->clk);
+    rt_uint16_t psc;
+    rt_uint32_t clk;
+    rt_uint32_t d;
+    rt_uint32_t clkh;
+    rt_uint32_t clkl;
+    rt_uint32_t input_clock = clk_get_rate(dev->clk);
 
-	/* NOTE: I2C Clock divider programming info
-	 * As per I2C specs the following formulas provide prescaler
-	 * and low/high divider values
-	 * input clk --> PSC Div -----------> ICCL/H Div --> output clock
-	 *                       module clk
-	 *
-	 * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
-	 *
-	 * Thus,
-	 * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
-	 *
-	 * where if PSC == 0, d = 7,
-	 *       if PSC == 1, d = 6
-	 *       if PSC > 1 , d = 5
-	 */
+    /* NOTE: I2C Clock divider programming info
+     * As per I2C specs the following formulas provide prescaler
+     * and low/high divider values
+     * input clk --> PSC Div -----------> ICCL/H Div --> output clock
+     *                       module clk
+     *
+     * output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
+     *
+     * Thus,
+     * (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
+     *
+     * where if PSC == 0, d = 7,
+     *       if PSC == 1, d = 6
+     *       if PSC > 1 , d = 5
+     */
 
-	/* get minimum of 7 MHz clock, but max of 12 MHz */
-	psc = (input_clock / 7000000) - 1;
-	if ((input_clock / (psc + 1)) > 12000000)
-		psc++;	/* better to run under spec than over */
-	d = (psc >= 2) ? 5 : 7 - psc;
+    /* get minimum of 7 MHz clock, but max of 12 MHz */
+    psc = (input_clock / 7000000) - 1;
+    if ((input_clock / (psc + 1)) > 12000000)
+        psc++;  /* better to run under spec than over */
+    d = (psc >= 2) ? 5 : 7 - psc;
 
-	clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)) - (d << 1);
-	clkh = clk >> 1;
-	clkl = clk - clkh;
+    clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)) - (d << 1);
+    clkh = clk >> 1;
+    clkl = clk - clkh;
 
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
 
-	i2c_dbg("input_clock = %d, CLK = %d\n", input_clock, clk);
+    i2c_dbg("input_clock = %d, CLK = %d\n", input_clock, clk);
 }
 
 /*
@@ -220,65 +220,65 @@ static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
  */
 static int i2c_davinci_init(struct davinci_i2c_dev *dev)
 {
-	/* put I2C into reset */
-	davinci_i2c_reset_ctrl(dev, 0);
+    /* put I2C into reset */
+    davinci_i2c_reset_ctrl(dev, 0);
 
-	/* compute clock dividers */
-	i2c_davinci_calc_clk_dividers(dev);
+    /* compute clock dividers */
+    i2c_davinci_calc_clk_dividers(dev);
 
-	/* Respond at reserved "SMBus Host" slave address" (and zero);
-	 * we seem to have no option to not respond...
-	 */
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
+    /* Respond at reserved "SMBus Host" slave address" (and zero);
+     * we seem to have no option to not respond...
+     */
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
 
-	i2c_dbg("PSC  = %d\n",
-		davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
-	i2c_dbg("CLKL = %d\n",
-		davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
-	i2c_dbg("CLKH = %d\n",
-		davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
-	i2c_dbg("bus_freq = %dkHz, bus_delay = %d\n",
-		dev->bus_freq, dev->bus_delay);
+    i2c_dbg("PSC  = %d\n",
+        davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
+    i2c_dbg("CLKL = %d\n",
+        davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
+    i2c_dbg("CLKH = %d\n",
+        davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
+    i2c_dbg("bus_freq = %dkHz, bus_delay = %d\n",
+        dev->bus_freq, dev->bus_delay);
 
-	/* Take the I2C module out of reset: */
-	davinci_i2c_reset_ctrl(dev, 1);
+    /* Take the I2C module out of reset: */
+    davinci_i2c_reset_ctrl(dev, 1);
 
-	/* Enable interrupts */
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
+    /* Enable interrupts */
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
 
-	return 0;
+    return 0;
 }
 
 /*
  * Waiting for bus not busy
  */
 static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
-					 char allow_sleep)
+                     char allow_sleep)
 {
-	unsigned long timeout;
-	static rt_uint16_t to_cnt;
-	RT_ASSERT(dev != RT_NULL);
-	RT_ASSERT(dev->bus != RT_NULL);
+    unsigned long timeout;
+    static rt_uint16_t to_cnt;
+    RT_ASSERT(dev != RT_NULL);
+    RT_ASSERT(dev->bus != RT_NULL);
 
-	timeout = rt_tick_get() + dev->bus->timeout;
-	while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
-	       & DAVINCI_I2C_STR_BB) {
-		if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
-			if (rt_tick_get() >= timeout) {
-				rt_kprintf("timeout waiting for bus ready\n");
-				to_cnt++;
-				return -RT_ETIMEOUT;
-			} else {
-				to_cnt = 0;
-				i2c_recover_bus(dev);
-				i2c_davinci_init(dev);
-			}
-		}
-		if (allow_sleep)
-			rt_thread_delay(2);
-	}
+    timeout = rt_tick_get() + dev->bus->timeout;
+    while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
+           & DAVINCI_I2C_STR_BB) {
+        if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
+            if (rt_tick_get() >= timeout) {
+                rt_kprintf("timeout waiting for bus ready\n");
+                to_cnt++;
+                return -RT_ETIMEOUT;
+            } else {
+                to_cnt = 0;
+                i2c_recover_bus(dev);
+                i2c_davinci_init(dev);
+            }
+        }
+        if (allow_sleep)
+            rt_thread_delay(2);
+    }
 
-	return 0;
+    return 0;
 }
 
 /*
@@ -288,125 +288,125 @@ static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
 static int
 i2c_davinci_xfer_msg(struct rt_i2c_bus_device *bus, struct rt_i2c_msg *msg, int stop)
 {
-	struct davinci_i2c_dev *dev = bus->priv;
-	rt_uint32_t flag;
-	rt_uint16_t w;
-	int r;
+    struct davinci_i2c_dev *dev = bus->priv;
+    rt_uint32_t flag;
+    rt_uint16_t w;
+    int r;
 
-	/* Introduce a delay, required for some boards (e.g Davinci EVM) */
-	if (dev->bus_delay)
-		udelay(dev->bus_delay);
+    /* Introduce a delay, required for some boards (e.g Davinci EVM) */
+    if (dev->bus_delay)
+        udelay(dev->bus_delay);
 
-	/* set the slave address */
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
+    /* set the slave address */
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
 
-	dev->buf = msg->buf;
-	dev->buf_len = msg->len;
-	dev->stop = stop;
+    dev->buf = msg->buf;
+    dev->buf_len = msg->len;
+    dev->stop = stop;
 
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
 
-	//INIT_COMPLETION(dev->cmd_complete);
-	dev->cmd_err = 0;
+    //INIT_COMPLETION(dev->cmd_complete);
+    dev->cmd_err = 0;
 
-	/* Take I2C out of reset and configure it as master */
-	flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
+    /* Take I2C out of reset and configure it as master */
+    flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
 
-	/* if the slave address is ten bit address, enable XA bit */
-	if (msg->flags & RT_I2C_ADDR_10BIT)
-		flag |= DAVINCI_I2C_MDR_XA;
-	if (!(msg->flags & RT_I2C_RD))
-		flag |= DAVINCI_I2C_MDR_TRX;
-	if (msg->len == 0)
-		flag |= DAVINCI_I2C_MDR_RM;
+    /* if the slave address is ten bit address, enable XA bit */
+    if (msg->flags & RT_I2C_ADDR_10BIT)
+        flag |= DAVINCI_I2C_MDR_XA;
+    if (!(msg->flags & RT_I2C_RD))
+        flag |= DAVINCI_I2C_MDR_TRX;
+    if (msg->len == 0)
+        flag |= DAVINCI_I2C_MDR_RM;
 
-	/* Enable receive or transmit interrupts */
-	w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
-	if (msg->flags & RT_I2C_RD)
-		w |= DAVINCI_I2C_IMR_RRDY;
-	else
-		w |= DAVINCI_I2C_IMR_XRDY;
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
+    /* Enable receive or transmit interrupts */
+    w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
+    if (msg->flags & RT_I2C_RD)
+        w |= DAVINCI_I2C_IMR_RRDY;
+    else
+        w |= DAVINCI_I2C_IMR_XRDY;
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
 
-	dev->terminate = 0;
+    dev->terminate = 0;
 
-	/*
-	 * Write mode register first as needed for correct behaviour
-	 * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
-	 * occurring before we have loaded DXR
-	 */
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
+    /*
+     * Write mode register first as needed for correct behaviour
+     * on OMAP-L138, but don't set STT yet to avoid a race with XRDY
+     * occurring before we have loaded DXR
+     */
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 
-	/*
-	 * First byte should be set here, not after interrupt,
-	 * because transmit-data-ready interrupt can come before
-	 * NACK-interrupt during sending of previous message and
-	 * ICDXR may have wrong data
-	 * It also saves us one interrupt, slightly faster
-	 */
-	if ((!(msg->flags & RT_I2C_RD)) && dev->buf_len)
-	{
-		davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
-		dev->buf_len--;
-	}
+    /*
+     * First byte should be set here, not after interrupt,
+     * because transmit-data-ready interrupt can come before
+     * NACK-interrupt during sending of previous message and
+     * ICDXR may have wrong data
+     * It also saves us one interrupt, slightly faster
+     */
+    if ((!(msg->flags & RT_I2C_RD)) && dev->buf_len)
+    {
+        davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
+        dev->buf_len--;
+    }
 
-	/* Set STT to begin transmit now DXR is loaded */
-	flag |= DAVINCI_I2C_MDR_STT;
-	if (stop && msg->len != 0)
-		flag |= DAVINCI_I2C_MDR_STP;
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
+    /* Set STT to begin transmit now DXR is loaded */
+    flag |= DAVINCI_I2C_MDR_STT;
+    if (stop && msg->len != 0)
+        flag |= DAVINCI_I2C_MDR_STP;
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
 
-	r = rt_sem_take(&dev->completion, dev->bus->timeout);
-	if (r == -RT_ETIMEOUT)
-	{
-		rt_kprintf("controller timed out\n");
-		i2c_recover_bus(dev);
-		i2c_davinci_init(dev);
-		dev->buf_len = 0;
-		return -RT_ETIMEOUT;
-	}
-	if (dev->buf_len)
-	{
-		/* This should be 0 if all bytes were transferred
-		 * or dev->cmd_err denotes an error.
-		 * A signal may have aborted the transfer.
-		 */
-		if (r == RT_EOK)
-		{
-			rt_kprintf("abnormal termination buf_len=%i\n",
-				dev->buf_len);
-			r = -RT_EIO;
-		}
-		dev->terminate = 1;
-		dev->buf_len = 0;
-	}
-	if (r < 0)
-		return r;
+    r = rt_sem_take(&dev->completion, dev->bus->timeout);
+    if (r == -RT_ETIMEOUT)
+    {
+        rt_kprintf("controller timed out\n");
+        i2c_recover_bus(dev);
+        i2c_davinci_init(dev);
+        dev->buf_len = 0;
+        return -RT_ETIMEOUT;
+    }
+    if (dev->buf_len)
+    {
+        /* This should be 0 if all bytes were transferred
+         * or dev->cmd_err denotes an error.
+         * A signal may have aborted the transfer.
+         */
+        if (r == RT_EOK)
+        {
+            rt_kprintf("abnormal termination buf_len=%i\n",
+                dev->buf_len);
+            r = -RT_EIO;
+        }
+        dev->terminate = 1;
+        dev->buf_len = 0;
+    }
+    if (r < 0)
+        return r;
 
-	/* no error */
-	if (!dev->cmd_err)
-		return msg->len;
+    /* no error */
+    if (!dev->cmd_err)
+        return msg->len;
 
-	/* We have an error */
-	if (dev->cmd_err & DAVINCI_I2C_STR_AL)
-	{
-		i2c_davinci_init(dev);
-		return -RT_EIO;
-	}
+    /* We have an error */
+    if (dev->cmd_err & DAVINCI_I2C_STR_AL)
+    {
+        i2c_davinci_init(dev);
+        return -RT_EIO;
+    }
 
-	if (dev->cmd_err & DAVINCI_I2C_STR_NACK)
-	{
-		if (msg->flags & RT_I2C_IGNORE_NACK)
-			return msg->len;
-		if (stop)
-		{
-			w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
-			w |= DAVINCI_I2C_MDR_STP;
-			davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
-		}
-		return -RT_EIO;
-	}
-	return -RT_EIO;
+    if (dev->cmd_err & DAVINCI_I2C_STR_NACK)
+    {
+        if (msg->flags & RT_I2C_IGNORE_NACK)
+            return msg->len;
+        if (stop)
+        {
+            w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
+            w |= DAVINCI_I2C_MDR_STP;
+            davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
+        }
+        return -RT_EIO;
+    }
+    return -RT_EIO;
 }
 
 /*
@@ -415,52 +415,52 @@ i2c_davinci_xfer_msg(struct rt_i2c_bus_device *bus, struct rt_i2c_msg *msg, int
 static int
 i2c_davinci_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], int num)
 {
-	struct davinci_i2c_dev *dev = bus->priv;
-	int i;
-	int ret;
+    struct davinci_i2c_dev *dev = bus->priv;
+    int i;
+    int ret;
 
-	i2c_dbg("%s: msgs: %d\n", __func__, num);
+    i2c_dbg("%s: msgs: %d\n", __func__, num);
 
-	ret = i2c_davinci_wait_bus_not_busy(dev, 1);
-	if (ret < 0)
-	{
-		i2c_dbg("timeout waiting for bus ready\n");
-		return ret;
-	}
+    ret = i2c_davinci_wait_bus_not_busy(dev, 1);
+    if (ret < 0)
+    {
+        i2c_dbg("timeout waiting for bus ready\n");
+        return ret;
+    }
 
-	for (i = 0; i < num; i++)
-	{
-		ret = i2c_davinci_xfer_msg(bus, &msgs[i], (i == (num - 1)));
-		i2c_dbg("%s [%d/%d] ret: %d\n", __func__, i + 1, num,
-			ret);
-		if (ret < 0)
-			return ret;
-	}
+    for (i = 0; i < num; i++)
+    {
+        ret = i2c_davinci_xfer_msg(bus, &msgs[i], (i == (num - 1)));
+        i2c_dbg("%s [%d/%d] ret: %d\n", __func__, i + 1, num,
+            ret);
+        if (ret < 0)
+            return ret;
+    }
 
 
-	return num;
+    return num;
 }
 
 
 static void terminate_read(struct davinci_i2c_dev *dev)
 {
-	rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
-	w |= DAVINCI_I2C_MDR_NACK;
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
+    rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
+    w |= DAVINCI_I2C_MDR_NACK;
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 
-	/* Throw away data */
-	davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
-	if (!dev->terminate)
-		rt_kprintf("RDR IRQ while no data requested\n");
+    /* Throw away data */
+    davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
+    if (!dev->terminate)
+        rt_kprintf("RDR IRQ while no data requested\n");
 }
 static void terminate_write(struct davinci_i2c_dev *dev)
 {
-	rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
-	w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
-	davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
+    rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
+    w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
+    davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
 
-	if (!dev->terminate)
-		i2c_dbg("TDR IRQ while no data to send\n");
+    if (!dev->terminate)
+        i2c_dbg("TDR IRQ while no data to send\n");
 }
 
 /*
@@ -469,173 +469,173 @@ static void terminate_write(struct davinci_i2c_dev *dev)
  */
 static void i2c_davinci_isr(int irq, void *param)
 {
-	struct davinci_i2c_dev *dev = (struct davinci_i2c_dev *)param;
-	rt_uint32_t stat;
-	int count = 0;
-	rt_uint16_t w;
+    struct davinci_i2c_dev *dev = (struct davinci_i2c_dev *)param;
+    rt_uint32_t stat;
+    int count = 0;
+    rt_uint16_t w;
 
-	while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
-		i2c_dbg("%s: stat=0x%x\n", __func__, stat);
-		if (count++ == 100) {
-			rt_kprintf("Too much work in one IRQ\n");
-			break;
-		}
+    while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
+        i2c_dbg("%s: stat=0x%x\n", __func__, stat);
+        if (count++ == 100) {
+            rt_kprintf("Too much work in one IRQ\n");
+            break;
+        }
 
-		switch (stat) {
-		case DAVINCI_I2C_IVR_AL:
-			/* Arbitration lost, must retry */
-			dev->cmd_err |= DAVINCI_I2C_STR_AL;
-			dev->buf_len = 0;
-			rt_sem_release(&dev->completion);
-			break;
+        switch (stat) {
+        case DAVINCI_I2C_IVR_AL:
+            /* Arbitration lost, must retry */
+            dev->cmd_err |= DAVINCI_I2C_STR_AL;
+            dev->buf_len = 0;
+            rt_sem_release(&dev->completion);
+            break;
 
-		case DAVINCI_I2C_IVR_NACK:
-			dev->cmd_err |= DAVINCI_I2C_STR_NACK;
-			dev->buf_len = 0;
-			rt_sem_release(&dev->completion);
-			break;
+        case DAVINCI_I2C_IVR_NACK:
+            dev->cmd_err |= DAVINCI_I2C_STR_NACK;
+            dev->buf_len = 0;
+            rt_sem_release(&dev->completion);
+            break;
 
-		case DAVINCI_I2C_IVR_ARDY:
-			davinci_i2c_write_reg(dev,
-				DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
-			if (((dev->buf_len == 0) && (dev->stop != 0)) ||
-			    (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
-				w = davinci_i2c_read_reg(dev,
-							 DAVINCI_I2C_MDR_REG);
-				w |= DAVINCI_I2C_MDR_STP;
-				davinci_i2c_write_reg(dev,
-						      DAVINCI_I2C_MDR_REG, w);
-			}
-			rt_sem_release(&dev->completion);
-			break;
+        case DAVINCI_I2C_IVR_ARDY:
+            davinci_i2c_write_reg(dev,
+                DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
+            if (((dev->buf_len == 0) && (dev->stop != 0)) ||
+                (dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
+                w = davinci_i2c_read_reg(dev,
+                             DAVINCI_I2C_MDR_REG);
+                w |= DAVINCI_I2C_MDR_STP;
+                davinci_i2c_write_reg(dev,
+                              DAVINCI_I2C_MDR_REG, w);
+            }
+            rt_sem_release(&dev->completion);
+            break;
 
-		case DAVINCI_I2C_IVR_RDR:
-			if (dev->buf_len) {
-				*dev->buf++ =
-				    davinci_i2c_read_reg(dev,
-							 DAVINCI_I2C_DRR_REG);
-				dev->buf_len--;
-				if (dev->buf_len)
-					continue;
+        case DAVINCI_I2C_IVR_RDR:
+            if (dev->buf_len) {
+                *dev->buf++ =
+                    davinci_i2c_read_reg(dev,
+                             DAVINCI_I2C_DRR_REG);
+                dev->buf_len--;
+                if (dev->buf_len)
+                    continue;
 
-				davinci_i2c_write_reg(dev,
-					DAVINCI_I2C_STR_REG,
-					DAVINCI_I2C_IMR_RRDY);
-			} else {
-				/* signal can terminate transfer */
-				terminate_read(dev);
-			}
-			break;
+                davinci_i2c_write_reg(dev,
+                    DAVINCI_I2C_STR_REG,
+                    DAVINCI_I2C_IMR_RRDY);
+            } else {
+                /* signal can terminate transfer */
+                terminate_read(dev);
+            }
+            break;
 
-		case DAVINCI_I2C_IVR_XRDY:
-			if (dev->buf_len) {
-				davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
-						      *dev->buf++);
-				dev->buf_len--;
-				if (dev->buf_len)
-					continue;
+        case DAVINCI_I2C_IVR_XRDY:
+            if (dev->buf_len) {
+                davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
+                              *dev->buf++);
+                dev->buf_len--;
+                if (dev->buf_len)
+                    continue;
 
-				w = davinci_i2c_read_reg(dev,
-							 DAVINCI_I2C_IMR_REG);
-				w &= ~DAVINCI_I2C_IMR_XRDY;
-				davinci_i2c_write_reg(dev,
-						      DAVINCI_I2C_IMR_REG,
-						      w);
-			} else {
-				/* signal can terminate transfer */
-				terminate_write(dev);
-			}
-			break;
+                w = davinci_i2c_read_reg(dev,
+                             DAVINCI_I2C_IMR_REG);
+                w &= ~DAVINCI_I2C_IMR_XRDY;
+                davinci_i2c_write_reg(dev,
+                              DAVINCI_I2C_IMR_REG,
+                              w);
+            } else {
+                /* signal can terminate transfer */
+                terminate_write(dev);
+            }
+            break;
 
-		case DAVINCI_I2C_IVR_SCD:
-			davinci_i2c_write_reg(dev,
-				DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
-			rt_sem_release(&dev->completion);
-			break;
+        case DAVINCI_I2C_IVR_SCD:
+            davinci_i2c_write_reg(dev,
+                DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
+            rt_sem_release(&dev->completion);
+            break;
 
-		case DAVINCI_I2C_IVR_AAS:
-			i2c_dbg("Address as slave interrupt\n");
-			break;
+        case DAVINCI_I2C_IVR_AAS:
+            i2c_dbg("Address as slave interrupt\n");
+            break;
 
-		default:
-			i2c_dbg("Unrecognized irq stat %d\n", stat);
-			break;
-		}
-	}
+        default:
+            i2c_dbg("Unrecognized irq stat %d\n", stat);
+            break;
+        }
+    }
 
 }
 
 
 
 static struct rt_i2c_bus_device_ops bus_ops = {
-	.master_xfer	= i2c_davinci_xfer,
+    .master_xfer    = i2c_davinci_xfer,
 };
 
 int davinci_i2c_init(char *bus_name)
 {
-	struct rt_i2c_bus_device *bus;
-	struct davinci_i2c_dev *dev;
-	int r;
+    struct rt_i2c_bus_device *bus;
+    struct davinci_i2c_dev *dev;
+    int r;
 
-	bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
-	if (bus == RT_NULL)
-	{
-		rt_kprintf("rt_malloc failed\n");
-		return -RT_ENOMEM;
-	}
-	
-	rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
+    bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
+    if (bus == RT_NULL)
+    {
+        rt_kprintf("rt_malloc failed\n");
+        return -RT_ENOMEM;
+    }
 
-	bus->ops = &bus_ops;
-	bus->timeout = DAVINCI_I2C_TIMEOUT;
+    rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
 
-	dev = rt_malloc(sizeof(struct davinci_i2c_dev));
-	if (!dev) 
-	{
-		r = -RT_ENOMEM;
-		goto err;
-	}
+    bus->ops = &bus_ops;
+    bus->timeout = DAVINCI_I2C_TIMEOUT;
 
-	rt_memset((void *)dev, 0, sizeof(struct davinci_i2c_dev));
+    dev = rt_malloc(sizeof(struct davinci_i2c_dev));
+    if (!dev)
+    {
+        r = -RT_ENOMEM;
+        goto err;
+    }
 
-	rt_sem_init(&dev->completion, "i2c_ack", 0, RT_IPC_FLAG_FIFO);
+    rt_memset((void *)dev, 0, sizeof(struct davinci_i2c_dev));
 
-	dev->irq = IRQ_I2C;
+    rt_sem_init(&dev->completion, "i2c_ack", 0, RT_IPC_FLAG_FIFO);
 
-	dev->clk = clk_get("I2CCLK");
-	if (dev->clk == RT_NULL) {
-		r = -RT_ERROR;
-		goto err1;
-	}
+    dev->irq = IRQ_I2C;
 
-	psc_change_state(DAVINCI_DM365_LPSC_I2C, 3);
+    dev->clk = clk_get("I2CCLK");
+    if (dev->clk == RT_NULL) {
+        r = -RT_ERROR;
+        goto err1;
+    }
 
-	dev->base = DAVINCI_I2C_BASE;
-	dev->bus_freq = 100;
-	dev->bus_delay = 0;
-	dev->bus = bus;
+    psc_change_state(DAVINCI_DM365_LPSC_I2C, 3);
 
-	bus->priv = dev;
+    dev->base = DAVINCI_I2C_BASE;
+    dev->bus_freq = 100;
+    dev->bus_delay = 0;
+    dev->bus = bus;
 
-	i2c_davinci_init(dev);
+    bus->priv = dev;
 
-	rt_hw_interrupt_install(dev->irq, i2c_davinci_isr, (void *)dev, "I2C");
-	rt_hw_interrupt_umask(dev->irq);
+    i2c_davinci_init(dev);
 
-	return rt_i2c_bus_device_register(bus, bus_name);
+    rt_hw_interrupt_install(dev->irq, i2c_davinci_isr, (void *)dev, "I2C");
+    rt_hw_interrupt_umask(dev->irq);
+
+    return rt_i2c_bus_device_register(bus, bus_name);
 
 err1:
-	rt_free(dev);
+    rt_free(dev);
 
 err:
-	rt_free(bus);
+    rt_free(bus);
 
-	return r;
+    return r;
 }
 
 int rt_hw_iic_init(void)
 {
-	davinci_i2c_init("I2C1");
+    davinci_i2c_init("I2C1");
 }
 
 INIT_DEVICE_EXPORT(rt_hw_iic_init);
diff --git a/bsp/dm365/drivers/mii.h b/bsp/dm365/drivers/mii.h
index d567b9fa84..8b42352bf4 100644
--- a/bsp/dm365/drivers/mii.h
+++ b/bsp/dm365/drivers/mii.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-03-18     weety		first version
+ * Date           Author        Notes
+ * 2011-03-18     weety     first version
  */
 
 
@@ -23,7 +23,7 @@
 #define MII_EXPANSION       0x06        /* Expansion register          */
 #define MII_CTRL1000        0x09        /* 1000BASE-T control          */
 #define MII_STAT1000        0x0a        /* 1000BASE-T status           */
-#define MII_ESTATUS	    0x0f	/* Extended Status */
+#define MII_ESTATUS     0x0f    /* Extended Status */
 #define MII_DCOUNTER        0x12        /* Disconnect counter          */
 #define MII_FCSCOUNTER      0x13        /* False carrier counter       */
 #define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
@@ -38,7 +38,7 @@
 
 /* Basic mode control register. */
 #define BMCR_RESV               0x003f  /* Unused...                   */
-#define BMCR_SPEED1000		0x0040  /* MSB of Speed (1000)         */
+#define BMCR_SPEED1000      0x0040  /* MSB of Speed (1000)         */
 #define BMCR_CTST               0x0080  /* Collision test              */
 #define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
 #define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
@@ -57,7 +57,7 @@
 #define BMSR_RFAULT             0x0010  /* Remote fault detected       */
 #define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
 #define BMSR_RESV               0x00c0  /* Unused...                   */
-#define BMSR_ESTATEN		0x0100	/* Extended Status in R15 */
+#define BMSR_ESTATEN        0x0100  /* Extended Status in R15 */
 #define BMSR_100HALF2           0x0200  /* Can do 100BASE-T2 HDX */
 #define BMSR_100FULL2           0x0400  /* Can do 100BASE-T2 FDX */
 #define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
@@ -86,7 +86,7 @@
 #define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
 
 #define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
-			ADVERTISE_CSMA)
+            ADVERTISE_CSMA)
 #define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
                        ADVERTISE_100HALF | ADVERTISE_100FULL)
 
@@ -108,8 +108,8 @@
 #define LPA_LPACK               0x4000  /* Link partner acked us       */
 #define LPA_NPAGE               0x8000  /* Next page bit               */
 
-#define LPA_DUPLEX		(LPA_10FULL | LPA_100FULL)
-#define LPA_100			(LPA_100FULL | LPA_100HALF | LPA_100BASE4)
+#define LPA_DUPLEX      (LPA_10FULL | LPA_100FULL)
+#define LPA_100         (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
 
 /* Expansion register for auto-negotiation. */
 #define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
@@ -119,8 +119,8 @@
 #define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
 #define EXPANSION_RESV          0xffe0  /* Unused...                   */
 
-#define ESTATUS_1000_TFULL	0x2000	/* Can do 1000BT Full */
-#define ESTATUS_1000_THALF	0x1000	/* Can do 1000BT Half */
+#define ESTATUS_1000_TFULL  0x2000  /* Can do 1000BT Full */
+#define ESTATUS_1000_THALF  0x1000  /* Can do 1000BT Half */
 
 /* N-way test register. */
 #define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
@@ -138,8 +138,8 @@
 #define LPA_1000HALF            0x0400  /* Link partner 1000BASE-T half duplex */
 
 /* Flow control flags */
-#define FLOW_CTRL_TX		0x01
-#define FLOW_CTRL_RX		0x02
+#define FLOW_CTRL_TX        0x01
+#define FLOW_CTRL_RX        0x02
 
 /**
  * mii_nway_result
@@ -174,11 +174,11 @@ rt_inline unsigned int mii_nway_result (unsigned int negotiated)
 }
 
 /* The forced speed, 10Mb, 100Mb, gigabit, 2.5Gb, 10GbE. */
-#define SPEED_10		10
-#define SPEED_100		100
-#define SPEED_1000		1000
-#define SPEED_2500		2500
-#define SPEED_10000		10000
+#define SPEED_10        10
+#define SPEED_100       100
+#define SPEED_1000      1000
+#define SPEED_2500      2500
+#define SPEED_10000     10000
 
 
 #endif /* __MII_H__ */
diff --git a/bsp/dm365/drivers/mmcsd.c b/bsp/dm365/drivers/mmcsd.c
index 7fcd0ef0c7..8e12236256 100644
--- a/bsp/dm365/drivers/mmcsd.c
+++ b/bsp/dm365/drivers/mmcsd.c
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 #include <rtthread.h>
@@ -18,66 +18,66 @@
 
 #define RT_USING_MMCSD0
 
-#define MMCSD_DEBUG			0	
+#define MMCSD_DEBUG         0
 #if MMCSD_DEBUG
-#define mmc_dbg(fmt, ...)	rt_kprintf(fmt, ##__VA_ARGS__)
+#define mmc_dbg(fmt, ...)   rt_kprintf(fmt, ##__VA_ARGS__)
 #else
 #define mmc_dbg(fmt, ...)
 #endif
 
-#define MMU_NOCACHE_ADDR(a)      	((rt_uint32_t)a | (1UL<<29))
-#define CACHE_LINE_SIZE	32
+#define MMU_NOCACHE_ADDR(a)         ((rt_uint32_t)a | (1UL<<29))
+#define CACHE_LINE_SIZE 32
 
 
 extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size);
 extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
 
-#define EVT_QUEUE_NUM				0	/* EDMA3 Event queue number. */
+#define EVT_QUEUE_NUM               0   /* EDMA3 Event queue number. */
 
 static unsigned rw_threshold = 32;
 static rt_bool_t use_dma = RT_TRUE;
 
 enum DATA_DIR_TYPE
 {
-	DM365_MMC_DATADIR_NONE = 0,
-	DM365_MMC_DATADIR_READ,
-	DM365_MMC_DATADIR_WRITE,
+    DM365_MMC_DATADIR_NONE = 0,
+    DM365_MMC_DATADIR_READ,
+    DM365_MMC_DATADIR_WRITE,
 };
 
-struct mmc_dm365_host 
+struct mmc_dm365_host
 {
-	struct rt_mmcsd_host		*mmc;
-	struct rt_mmcsd_req			*req;
-	struct rt_mmcsd_data		*data;
-	struct rt_mmcsd_cmd			*cmd;
-	struct edmacc_param 	tx_template;
-	struct edmacc_param 	rx_template;
+    struct rt_mmcsd_host        *mmc;
+    struct rt_mmcsd_req         *req;
+    struct rt_mmcsd_data        *data;
+    struct rt_mmcsd_cmd         *cmd;
+    struct edmacc_param     tx_template;
+    struct edmacc_param     rx_template;
 
-	rt_uint32_t	mmc_input_clk;
-	rt_uint32_t ns_in_one_cycle;	/* for ns in one cycle calculation */
+    rt_uint32_t mmc_input_clk;
+    rt_uint32_t ns_in_one_cycle;    /* for ns in one cycle calculation */
 
-	mmcsd_regs_t *mmcsd_regs;
-	rt_uint8_t	bus_mode;
+    mmcsd_regs_t *mmcsd_regs;
+    rt_uint8_t  bus_mode;
 
-	enum DATA_DIR_TYPE	data_dir;
+    enum DATA_DIR_TYPE  data_dir;
 
-	rt_uint32_t	rxdma;
-	rt_uint32_t	txdma;
-	rt_bool_t	use_dma;
-	rt_bool_t	do_dma;
+    rt_uint32_t rxdma;
+    rt_uint32_t txdma;
+    rt_bool_t   use_dma;
+    rt_bool_t   do_dma;
 
-	rt_uint8_t *buffer;
-	rt_uint32_t buffer_bytes_left;
-	rt_uint32_t bytes_left;
+    rt_uint8_t *buffer;
+    rt_uint32_t buffer_bytes_left;
+    rt_uint32_t bytes_left;
 
-	rt_uint8_t *dma_buffer;
-	rt_bool_t   use_dma_buffer;
-	rt_bool_t   sdio_int;
+    rt_uint8_t *dma_buffer;
+    rt_bool_t   use_dma_buffer;
+    rt_bool_t   sdio_int;
 };
 
 void *mmc_priv(struct rt_mmcsd_host *host)
 {
-	return (void *)host->private_data;
+    return (void *)host->private_data;
 }
 
 static void delay_us(rt_uint32_t us)
@@ -90,968 +90,968 @@ static void delay_us(rt_uint32_t us)
 /*******************************************************************************************************
 ** 函数名称: calculate_freq_for_card()
 ** 功能描述: 此函数用于计算设置SD卡频率所需的分频数
-** 
-** 输　入: host			->	DM365 MMC host句柄
-**         mmc_req_freq	->	MMC工作频率
+**
+** 输　入: host            ->  DM365 MMC host句柄
+**         mmc_req_freq ->  MMC工作频率
 **
 ** 输　出: 分频值
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static rt_uint32_t calculate_freq_for_card(struct mmc_dm365_host *host, rt_uint32_t mmc_req_freq)
 {
-	rt_uint32_t mmc_freq = 0;
-	rt_uint32_t mmc_pclk = 0;
-	rt_uint32_t mmc_push_pull_divisor = 0;
+    rt_uint32_t mmc_freq = 0;
+    rt_uint32_t mmc_pclk = 0;
+    rt_uint32_t mmc_push_pull_divisor = 0;
+
+    mmc_pclk = host->mmc_input_clk;
+
+    if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq))
+        mmc_push_pull_divisor = ((rt_uint32_t)mmc_pclk / (2 * mmc_req_freq)) - 1;
+    else
+        mmc_push_pull_divisor = 0;
 
-	mmc_pclk = host->mmc_input_clk;
-	
-	if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq))
-		mmc_push_pull_divisor = ((rt_uint32_t)mmc_pclk / (2 * mmc_req_freq)) - 1;
-	else
-		mmc_push_pull_divisor = 0;
+    mmc_freq = (rt_uint32_t)mmc_pclk / (2 * (mmc_push_pull_divisor + 1));
 
-	mmc_freq = (rt_uint32_t)mmc_pclk / (2 * (mmc_push_pull_divisor + 1));
+    if (mmc_freq > mmc_req_freq)
+        mmc_push_pull_divisor = mmc_push_pull_divisor + 1;
 
-	if (mmc_freq > mmc_req_freq)
-		mmc_push_pull_divisor = mmc_push_pull_divisor + 1;
-	
-	/* Convert ns to clock cycles */
-	if (mmc_req_freq <= 400000)
-		host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000));
-	else
-		host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000000));
+    /* Convert ns to clock cycles */
+    if (mmc_req_freq <= 400000)
+        host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000));
+    else
+        host->ns_in_one_cycle = (1000000)/(((mmc_pclk/(2*(mmc_push_pull_divisor+1)))/1000000));
 
-	return mmc_push_pull_divisor;
+    return mmc_push_pull_divisor;
 }
 
 /*******************************************************************************************************
 ** 函数名称: calculate_freq_for_card()
 ** 功能描述: 此函数用于计算MMC clock分频数
-** 
-** 输　入: host			->	DM365 MMC host句柄
-**         ios			->	MMC 操作句柄
+**
+** 输　入: host            ->  DM365 MMC host句柄
+**         ios          ->  MMC 操作句柄
 **
 ** 输　出: 读取到的PHY寄存器值
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void calculate_clk_divider(struct rt_mmcsd_host *mmc, struct rt_mmcsd_io_cfg *ios)
 {
-	rt_uint32_t temp = 0;
-	rt_uint32_t mmc_pclk = 0;
-	rt_uint32_t open_drain_freq = 0;
-	rt_uint32_t mmc_push_pull_freq = 0;
-	struct mmc_dm365_host *host = mmc_priv(mmc);
+    rt_uint32_t temp = 0;
+    rt_uint32_t mmc_pclk = 0;
+    rt_uint32_t open_drain_freq = 0;
+    rt_uint32_t mmc_push_pull_freq = 0;
+    struct mmc_dm365_host *host = mmc_priv(mmc);
 
-	mmc_pclk = host->mmc_input_clk;
+    mmc_pclk = host->mmc_input_clk;
 
-	if (ios->bus_mode == MMCSD_BUSMODE_OPENDRAIN) 
-	{
-		/* Ignoring the init clock value passed for fixing the inter
-		 * operability with different cards.
-		 */
-		open_drain_freq = ((rt_uint32_t)mmc_pclk / (2 * MMCSD_INIT_CLOCK)) - 1;
+    if (ios->bus_mode == MMCSD_BUSMODE_OPENDRAIN)
+    {
+        /* Ignoring the init clock value passed for fixing the inter
+         * operability with different cards.
+         */
+        open_drain_freq = ((rt_uint32_t)mmc_pclk / (2 * MMCSD_INIT_CLOCK)) - 1;
 
-		if (open_drain_freq > 0xFF)
-			open_drain_freq = 0xFF;
+        if (open_drain_freq > 0xFF)
+            open_drain_freq = 0xFF;
 
-		temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK; 
-		temp |= open_drain_freq;
-		host->mmcsd_regs->MMCCLK = temp;
+        temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK;
+        temp |= open_drain_freq;
+        host->mmcsd_regs->MMCCLK = temp;
 
-		
-		/* Convert ns to clock cycles */
-		host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK / 1000);
-	} 
-	else 
-	{
-		mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock);
 
-		if (mmc_push_pull_freq > 0xFF)
-			mmc_push_pull_freq = 0xFF;
+        /* Convert ns to clock cycles */
+        host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK / 1000);
+    }
+    else
+    {
+        mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock);
+
+        if (mmc_push_pull_freq > 0xFF)
+            mmc_push_pull_freq = 0xFF;
+
+        temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKEN;
+        host->mmcsd_regs->MMCCLK = temp;
 
-		temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKEN;
-		host->mmcsd_regs->MMCCLK = temp;
-		
-		delay_us(10);
+        delay_us(10);
 
-		temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK;
-		temp |= mmc_push_pull_freq;
-		host->mmcsd_regs->MMCCLK = temp;
-		
-		host->mmcsd_regs->MMCCLK = temp | MMCCLK_CLKEN;
+        temp = host->mmcsd_regs->MMCCLK & ~MMCCLK_CLKRT_MASK;
+        temp |= mmc_push_pull_freq;
+        host->mmcsd_regs->MMCCLK = temp;
 
-		delay_us(10);
-	}
+        host->mmcsd_regs->MMCCLK = temp | MMCCLK_CLKEN;
+
+        delay_us(10);
+    }
 }
 
 /*******************************************************************************************************
 ** 函数名称: mmc_dm365_set_ios()
 ** 功能描述: 此函数是mmc设置设置
-** 
-** 输　入: mmc			->	mmc host 句柄 
-**         ios			->	mmc 操作句柄
+**
+** 输　入: mmc         ->  mmc host 句柄
+**         ios          ->  mmc 操作句柄
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void mmc_dm365_set_ios(struct rt_mmcsd_host *mmc, struct rt_mmcsd_io_cfg *ios)
 {
-	struct mmc_dm365_host *host = mmc_priv(mmc);
+    struct mmc_dm365_host *host = mmc_priv(mmc);
 
-	mmc_dbg("clock %dHz busmode %d powermode %d Vdd %04x\n", ios->clock, ios->bus_mode, ios->power_mode, ios->vdd);
+    mmc_dbg("clock %dHz busmode %d powermode %d Vdd %04x\n", ios->clock, ios->bus_mode, ios->power_mode, ios->vdd);
 
-	switch (ios->bus_width) 
+    switch (ios->bus_width)
     {
-	case MMCSD_BUS_WIDTH_8:
+    case MMCSD_BUS_WIDTH_8:
         mmc_dbg("Enabling 8 bit mode\n");
-		host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT;
-		break;
-	case MMCSD_BUS_WIDTH_4:
+        host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT;
+        break;
+    case MMCSD_BUS_WIDTH_4:
         mmc_dbg("Enabling 4 bit mode\n");
-		host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT;
-		break;
-	case MMCSD_BUS_WIDTH_1:
+        host->mmcsd_regs->MMCCTL = (host->mmcsd_regs->MMCCTL & ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT;
+        break;
+    case MMCSD_BUS_WIDTH_1:
         mmc_dbg("Enabling 1 bit mode\n");
-		host->mmcsd_regs->MMCCTL = host->mmcsd_regs->MMCCTL & ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT);
-		break;
-	}
+        host->mmcsd_regs->MMCCTL = host->mmcsd_regs->MMCCTL & ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT);
+        break;
+    }
 
-	calculate_clk_divider(mmc, ios);
+    calculate_clk_divider(mmc, ios);
 
-	host->bus_mode = ios->bus_mode;
-	if (ios->power_mode == MMCSD_POWER_UP) 
+    host->bus_mode = ios->bus_mode;
+    if (ios->power_mode == MMCSD_POWER_UP)
     {
-		unsigned long timeout = rt_tick_get() + 500;
-		rt_bool_t lose = 1;
+        unsigned long timeout = rt_tick_get() + 500;
+        rt_bool_t lose = 1;
 
-		host->mmcsd_regs->MMCARGHL = 0;
-		host->mmcsd_regs->MMCCMD = MMCCMD_INITCK;
-		
-		while (rt_tick_get() < timeout) 
-		{
-			rt_uint32_t tmp = host->mmcsd_regs->MMCST0;
+        host->mmcsd_regs->MMCARGHL = 0;
+        host->mmcsd_regs->MMCCMD = MMCCMD_INITCK;
 
-			if (tmp & MMCST0_RSPDNE) 
-			{
-				lose = 0;
-				break;
-			}
-		}
-		if (lose)
-			mmc_dbg("powerup timeout\n");
-	}
+        while (rt_tick_get() < timeout)
+        {
+            rt_uint32_t tmp = host->mmcsd_regs->MMCST0;
+
+            if (tmp & MMCST0_RSPDNE)
+            {
+                lose = 0;
+                break;
+            }
+        }
+        if (lose)
+            mmc_dbg("powerup timeout\n");
+    }
 }
 
 /*******************************************************************************************************
 ** 函数名称: dm365_fifo_data_trans()
 ** 功能描述: 此函数是fifo模式传输
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
-**         n			->	传输字节数
+**
+** 输　入: host            ->  DM365 mmc host 句柄
+**         n            ->  传输字节数
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void dm365_fifo_data_trans(struct mmc_dm365_host *host, rt_uint32_t n)
 {
-	rt_uint8_t *p;
-	rt_uint32_t i;
+    rt_uint8_t *p;
+    rt_uint32_t i;
+
+    p = host->buffer;
 
-	p = host->buffer;
+    if (host->bytes_left < n)
+        n = host->bytes_left;
 
-	if (host->bytes_left < n)
-		n = host->bytes_left;
-	
-	host->bytes_left -= n;
+    host->bytes_left -= n;
 
-	/* NOTE:  we never transfer more than rw_threshold bytes
-	 * to/from the fifo here; there's no I/O overlap.
-	 * This also assumes that access width( i.e. ACCWD) is 4 bytes
-	 */
-	if (host->data_dir == DM365_MMC_DATADIR_WRITE) 
-	{
-		for (i = 0; i < (n >> 2); i++) 
-		{
-			host->mmcsd_regs->MMCDXR = *((rt_uint32_t *)p);
-			p = p + 4;
-		}
-		if (n & 3) 
-		{
-			rt_kprintf("to do ... \n");
-//			iowrite8_rep(host->base + MMCSD_MMCDXR, p, (n & 3));
-			p = p + (n & 3);
-		}
-	} 
-	else 
-	{		
-		for (i = 0; i < (n >> 2); i++) 
-		{
-			*((rt_uint32_t *)p) = host->mmcsd_regs->MMCDRR;	
-			p  = p + 4;
-		}
-		if (n & 3) 
-		{
+    /* NOTE:  we never transfer more than rw_threshold bytes
+     * to/from the fifo here; there's no I/O overlap.
+     * This also assumes that access width( i.e. ACCWD) is 4 bytes
+     */
+    if (host->data_dir == DM365_MMC_DATADIR_WRITE)
+    {
+        for (i = 0; i < (n >> 2); i++)
+        {
+            host->mmcsd_regs->MMCDXR = *((rt_uint32_t *)p);
+            p = p + 4;
+        }
+        if (n & 3)
+        {
+            rt_kprintf("to do ... \n");
+//          iowrite8_rep(host->base + MMCSD_MMCDXR, p, (n & 3));
+            p = p + (n & 3);
+        }
+    }
+    else
+    {
+        for (i = 0; i < (n >> 2); i++)
+        {
+            *((rt_uint32_t *)p) = host->mmcsd_regs->MMCDRR;
+            p  = p + 4;
+        }
+        if (n & 3)
+        {
             rt_kprintf("to do ... \n");
-//			ioread8_rep(host->base + MMCSD_MMCDRR, p, (n & 3));
-			p = p + (n & 3);
-		}
-	}
-	host->buffer = p;
+//          ioread8_rep(host->base + MMCSD_MMCDRR, p, (n & 3));
+            p = p + (n & 3);
+        }
+    }
+    host->buffer = p;
 }
 
 /*******************************************************************************************************
 ** 函数名称: mmc_dm365_start_command()
 ** 功能描述: 此函数是开始发送SD命令
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
-**         cmd			->	SD命令句柄
+**
+** 输　入: host            ->  DM365 mmc host 句柄
+**         cmd          ->  SD命令句柄
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void mmc_dm365_start_command(struct mmc_dm365_host *host, struct rt_mmcsd_cmd *cmd)
 {
-	rt_uint32_t cmd_reg = 0;
-	rt_uint32_t im_val;
-	
-	host->cmd = cmd;
+    rt_uint32_t cmd_reg = 0;
+    rt_uint32_t im_val;
+
+    host->cmd = cmd;
 
-	switch (resp_type(cmd)) 
-	{
-	case RESP_R1B:
-		/* There's some spec confusion about when R1B is
-		 * allowed, but if the card doesn't issue a BUSY
-		 * then it's harmless for us to allow it.
-		 */
-		cmd_reg |= MMCCMD_BSYEXP;
-		/* FALLTHROUGH */
-	case RESP_R1:		/* 48 bits, CRC */
+    switch (resp_type(cmd))
+    {
+    case RESP_R1B:
+        /* There's some spec confusion about when R1B is
+         * allowed, but if the card doesn't issue a BUSY
+         * then it's harmless for us to allow it.
+         */
+        cmd_reg |= MMCCMD_BSYEXP;
+        /* FALLTHROUGH */
+    case RESP_R1:       /* 48 bits, CRC */
     case RESP_R4:
-	case RESP_R5:
+    case RESP_R5:
     case RESP_R6:
-    case RESP_R7:        
-		cmd_reg |= MMCCMD_RSPFMT_R1456;
-		break;
-	case RESP_R2:		/* 136 bits, CRC */
-		cmd_reg |= MMCCMD_RSPFMT_R2;
-		break;
-	case RESP_R3:		/* 48 bits, no CRC */
-		cmd_reg |= MMCCMD_RSPFMT_R3;
-		break;
-	default:
-		cmd_reg |= MMCCMD_RSPFMT_NONE;
-		mmc_dbg("unknown resp_type %04x\n", resp_type(cmd));
-		break;
-	}
+    case RESP_R7:
+        cmd_reg |= MMCCMD_RSPFMT_R1456;
+        break;
+    case RESP_R2:       /* 136 bits, CRC */
+        cmd_reg |= MMCCMD_RSPFMT_R2;
+        break;
+    case RESP_R3:       /* 48 bits, no CRC */
+        cmd_reg |= MMCCMD_RSPFMT_R3;
+        break;
+    default:
+        cmd_reg |= MMCCMD_RSPFMT_NONE;
+        mmc_dbg("unknown resp_type %04x\n", resp_type(cmd));
+        break;
+    }
+
+    /* Set command index */
+    cmd_reg |= cmd->cmd_code;
+
+    /* Enable EDMA transfer triggers */
+    if (host->do_dma == RT_TRUE)
+        cmd_reg |= MMCCMD_DMATRIG;
 
-	/* Set command index */
-	cmd_reg |= cmd->cmd_code;
+    if (host->data != RT_NULL && host->data_dir == DM365_MMC_DATADIR_READ)
+        cmd_reg |= MMCCMD_DMATRIG;
 
-	/* Enable EDMA transfer triggers */
-	if (host->do_dma == RT_TRUE)
-		cmd_reg |= MMCCMD_DMATRIG;
+    /* Setting whether command involves data transfer or not */
+    if (cmd->data)
+        cmd_reg |= MMCCMD_WDATX;
 
-	if (host->data != RT_NULL && host->data_dir == DM365_MMC_DATADIR_READ)
-		cmd_reg |= MMCCMD_DMATRIG;
+    /* Setting whether stream or block transfer */
+    if (cmd->flags & MMC_DATA_STREAM)
+    {
+        mmc_dbg("to do\n");
+        cmd_reg |= MMCCMD_STRMTP;
+    }
 
-	/* Setting whether command involves data transfer or not */
-	if (cmd->data)
-		cmd_reg |= MMCCMD_WDATX;
+    /* Setting whether data read or write */
+    if (host->data_dir == DM365_MMC_DATADIR_WRITE)
+        cmd_reg |= MMCCMD_DTRW;
 
-	/* Setting whether stream or block transfer */
-	if (cmd->flags & MMC_DATA_STREAM)
-	{
-		mmc_dbg("to do\n");
-		cmd_reg |= MMCCMD_STRMTP;
-	}
+    if (host->bus_mode == MMCSD_BUSMODE_PUSHPULL)
+    {
+        cmd_reg |= MMCCMD_PPLEN;
+    }
 
-	/* Setting whether data read or write */
-	if (host->data_dir == DM365_MMC_DATADIR_WRITE)
-		cmd_reg |= MMCCMD_DTRW;
+    /* set Command timeout */
+    host->mmcsd_regs->MMCTOR = 0x1FFF;
 
-	if (host->bus_mode == MMCSD_BUSMODE_PUSHPULL)
-	{
-		cmd_reg |= MMCCMD_PPLEN;
-	}
-	
-	/* set Command timeout */
-	host->mmcsd_regs->MMCTOR = 0x1FFF;
-	
-	/* Enable interrupt (calculate here, defer until FIFO is stuffed). */
-	im_val =  MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS;
-	if (host->data_dir == DM365_MMC_DATADIR_WRITE) 
-	{
-		im_val |= MMCST0_DATDNE | MMCST0_CRCWR;
+    /* Enable interrupt (calculate here, defer until FIFO is stuffed). */
+    im_val =  MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS;
+    if (host->data_dir == DM365_MMC_DATADIR_WRITE)
+    {
+        im_val |= MMCST0_DATDNE | MMCST0_CRCWR;
 
-		if (host->do_dma == RT_FALSE)
-			im_val |= MMCST0_DXRDY;
-	} 
-	else if (host->data_dir == DM365_MMC_DATADIR_READ) 
-	{
-		im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD;
+        if (host->do_dma == RT_FALSE)
+            im_val |= MMCST0_DXRDY;
+    }
+    else if (host->data_dir == DM365_MMC_DATADIR_READ)
+    {
+        im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD;
 
-		if (host->do_dma == RT_FALSE)
-			im_val |= MMCST0_DRRDY;
-	}
+        if (host->do_dma == RT_FALSE)
+            im_val |= MMCST0_DRRDY;
+    }
 
-	/*
-	 * Before non-DMA WRITE commands the controller needs priming:
-	 * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size
-	 */
-	if ((host->do_dma == RT_FALSE) && (host->data_dir == DM365_MMC_DATADIR_WRITE))
-		dm365_fifo_data_trans(host, rw_threshold);
+    /*
+     * Before non-DMA WRITE commands the controller needs priming:
+     * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size
+     */
+    if ((host->do_dma == RT_FALSE) && (host->data_dir == DM365_MMC_DATADIR_WRITE))
+        dm365_fifo_data_trans(host, rw_threshold);
 
-	host->mmcsd_regs->MMCARGHL = cmd->arg;
-	host->mmcsd_regs->MMCCMD = cmd_reg;
-	host->mmcsd_regs->MMCIM = im_val;
+    host->mmcsd_regs->MMCARGHL = cmd->arg;
+    host->mmcsd_regs->MMCCMD = cmd_reg;
+    host->mmcsd_regs->MMCIM = im_val;
 }
 
 /*******************************************************************************************************
 ** 函数名称: dm365_abort_dma()
 ** 功能描述: 此函数终止DMA传输
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
+**
+** 输　入: host            ->  DM365 mmc host 句柄
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void dm365_abort_dma(struct mmc_dm365_host *host)
 {
-	int sync_dev;
+    int sync_dev;
 
-	if (host->data_dir == DM365_MMC_DATADIR_READ)
-		sync_dev = host->rxdma;
-	else
-		sync_dev = host->txdma;
+    if (host->data_dir == DM365_MMC_DATADIR_READ)
+        sync_dev = host->rxdma;
+    else
+        sync_dev = host->txdma;
 
-	//EDMA3DisableTransfer(EDMA0CC0_REG_BASE, sync_dev, EDMA3_TRIG_MODE_EVENT);
-	edma_stop(sync_dev);
-	edma_clean_channel(sync_dev);
+    //EDMA3DisableTransfer(EDMA0CC0_REG_BASE, sync_dev, EDMA3_TRIG_MODE_EVENT);
+    edma_stop(sync_dev);
+    edma_clean_channel(sync_dev);
 }
 
 /*******************************************************************************************************
 ** 函数名称: mmc_request_done()
 ** 功能描述: 此函数用于结束处理一个MMC请求
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
-**         mrq			->	request 句柄
+**
+** 输　入: host            ->  DM365 mmc host 句柄
+**         mrq          ->  request 句柄
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 void mmc_request_done(struct rt_mmcsd_host *host, struct rt_mmcsd_req *mrq)
 {
-	struct rt_mmcsd_cmd *cmd = mrq->cmd;
-	int err = cmd->err;
+    struct rt_mmcsd_cmd *cmd = mrq->cmd;
+    int err = cmd->err;
 
-	if (err && cmd->retries) 
-	{
-		mmc_dbg("req failed (CMD%u): %d, retrying...\n", cmd->cmd_code, err);
+    if (err && cmd->retries)
+    {
+        mmc_dbg("req failed (CMD%u): %d, retrying...\n", cmd->cmd_code, err);
 
-		cmd->retries--;
-		cmd->err = 0;
-		host->ops->request(host, mrq);
-	} 
-	else 
-	{
-		mmc_dbg("%s: req done (CMD%u): %d: %08x %08x %08x %08x\n",
-			"dm365 host", cmd->cmd_code, err,
-			cmd->resp[0], cmd->resp[1],
-			cmd->resp[2], cmd->resp[3]);
+        cmd->retries--;
+        cmd->err = 0;
+        host->ops->request(host, mrq);
+    }
+    else
+    {
+        mmc_dbg("%s: req done (CMD%u): %d: %08x %08x %08x %08x\n",
+            "dm365 host", cmd->cmd_code, err,
+            cmd->resp[0], cmd->resp[1],
+            cmd->resp[2], cmd->resp[3]);
 
-		if (mrq->data) 
-		{
-			mmc_dbg("%s:     %d bytes transferred: %d\n",
-				"dm365 host",
-				mrq->data->bytes_xfered, mrq->data->err);
-		}
+        if (mrq->data)
+        {
+            mmc_dbg("%s:     %d bytes transferred: %d\n",
+                "dm365 host",
+                mrq->data->bytes_xfered, mrq->data->err);
+        }
 
-		if (mrq->stop) 
-		{
-			mmc_dbg("%s:     (CMD%u): %d: %08x %08x %08x %08x\n",
-				"dm365 host", mrq->stop->cmd_code,
-				mrq->stop->err,
-				mrq->stop->resp[0], mrq->stop->resp[1],
-				mrq->stop->resp[2], mrq->stop->resp[3]);
-		}
+        if (mrq->stop)
+        {
+            mmc_dbg("%s:     (CMD%u): %d: %08x %08x %08x %08x\n",
+                "dm365 host", mrq->stop->cmd_code,
+                mrq->stop->err,
+                mrq->stop->resp[0], mrq->stop->resp[1],
+                mrq->stop->resp[2], mrq->stop->resp[3]);
+        }
 
-		mmcsd_req_complete(host);
-	}
+        mmcsd_req_complete(host);
+    }
 }
 
 /*******************************************************************************************************
 ** 函数名称: mmc_dm365_xfer_done()
 ** 功能描述: 数据传送结束调用此函数
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
-**         data			->	data 句柄
+**
+** 输　入: host            ->  DM365 mmc host 句柄
+**         data         ->  data 句柄
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void mmc_dm365_xfer_done(struct mmc_dm365_host *host, struct rt_mmcsd_data *data)
 {
-	host->data = RT_NULL;
+    host->data = RT_NULL;
+
+    if (host->mmc->flags & MMCSD_SUP_SDIO_IRQ) {
+        /*
+         * SDIO Interrupt Detection work-around as suggested by
+         * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata
+         * 2.1.6): Signal SDIO interrupt only if it is enabled by core
+         */
+        if (host->sdio_int && !(host->mmcsd_regs->SDIOST0 &
+                    SDIOST0_DAT1_HI)) {
+            host->mmcsd_regs->SDIOIST = SDIOIST_IOINT;
+            sdio_irq_wakeup(host->mmc);
+        }
+    }
 
-	if (host->mmc->flags & MMCSD_SUP_SDIO_IRQ) {
-		/*
-		 * SDIO Interrupt Detection work-around as suggested by
-		 * Davinci Errata (TMS320DM355 Silicon Revision 1.1 Errata
-		 * 2.1.6): Signal SDIO interrupt only if it is enabled by core
-		 */
-		if (host->sdio_int && !(host->mmcsd_regs->SDIOST0 &
-					SDIOST0_DAT1_HI)) {
-			host->mmcsd_regs->SDIOIST = SDIOIST_IOINT;
-			sdio_irq_wakeup(host->mmc);
-		}
-	}
+    if (host->do_dma == RT_TRUE)
+    {
+        dm365_abort_dma(host);
 
-	if (host->do_dma == RT_TRUE)
-	{
-		dm365_abort_dma(host);
+        if (data->flags & DATA_DIR_READ)
+        {
+            /* read operation */
+            if (host->use_dma_buffer == RT_TRUE)
+            {
+                /* copy DMA buffer to read buffer */
+                memcpy(data->buf, (void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->blks * data->blksize);
+            }
+            /*else
+            {
+                mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize);
+            }*/
+        }
 
-		if (data->flags & DATA_DIR_READ)
-		{
-			/* read operation */
-			if (host->use_dma_buffer == RT_TRUE)
-			{
-				/* copy DMA buffer to read buffer */
-				memcpy(data->buf, (void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->blks * data->blksize);
-			}
-			/*else
-			{
-				mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize);
-			}*/
-		}
+        host->do_dma = RT_FALSE;
+    }
 
-		host->do_dma = RT_FALSE;
-	}
-	
-	host->data_dir = DM365_MMC_DATADIR_NONE;
+    host->data_dir = DM365_MMC_DATADIR_NONE;
 
-	if (!data->stop || (host->cmd && host->cmd->err)) 
-	{
-		mmc_request_done(host->mmc, data->mrq);
-		host->mmcsd_regs->MMCIM = 0;
-	} 
-	else
-		mmc_dm365_start_command(host, data->stop);
+    if (!data->stop || (host->cmd && host->cmd->err))
+    {
+        mmc_request_done(host->mmc, data->mrq);
+        host->mmcsd_regs->MMCIM = 0;
+    }
+    else
+        mmc_dm365_start_command(host, data->stop);
 }
 
 static void mmc_dm365_dma_cb(unsigned channel, rt_uint16_t ch_status, void *data)
 {
-	if (DMA_COMPLETE != ch_status) {
-		struct mmc_dm365_host *host = data;
+    if (DMA_COMPLETE != ch_status) {
+        struct mmc_dm365_host *host = data;
 
-		/* Currently means:  DMA Event Missed, or "null" transfer
-		 * request was seen.  In the future, TC errors (like bad
-		 * addresses) might be presented too.
-		 */
-		mmc_dbg("DMA %s error\n",
-			(host->data->flags & MMC_DATA_WRITE)
-				? "write" : "read");
-		host->data->err = -RT_EIO;
-		mmc_dm365_xfer_done(host, host->data);
-	}
+        /* Currently means:  DMA Event Missed, or "null" transfer
+         * request was seen.  In the future, TC errors (like bad
+         * addresses) might be presented too.
+         */
+        mmc_dbg("DMA %s error\n",
+            (host->data->flags & MMC_DATA_WRITE)
+                ? "write" : "read");
+        host->data->err = -RT_EIO;
+        mmc_dm365_xfer_done(host, host->data);
+    }
 }
 
 
 /*******************************************************************************************************
 ** 函数名称: mmc_dm365_dma_setup()
 ** 功能描述: DMA 设置函数
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
-**         tx			->	布尔变量，用于判断Tx或者是Rx
-**         template		->	用于保存EDMA3CCPaRAMEntry机构数据
+**
+** 输　入: host            ->  DM365 mmc host 句柄
+**         tx           ->  布尔变量，用于判断Tx或者是Rx
+**         template     ->  用于保存EDMA3CCPaRAMEntry机构数据
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void mmc_dm365_dma_setup(struct mmc_dm365_host *host, rt_bool_t tx, struct edmacc_param *template)
 {
-	rt_uint32_t       sync_dev;
-	const rt_uint16_t acnt = 4;
-	const rt_uint16_t bcnt = rw_threshold >> 2;
-	const rt_uint16_t	ccnt = 0;
-	rt_uint32_t		src_port = 0;
-	rt_uint32_t		dst_port = 0;
-	rt_int16_t		src_bidx, dst_bidx;
-	rt_int16_t		src_cidx, dst_cidx;
+    rt_uint32_t       sync_dev;
+    const rt_uint16_t acnt = 4;
+    const rt_uint16_t bcnt = rw_threshold >> 2;
+    const rt_uint16_t   ccnt = 0;
+    rt_uint32_t     src_port = 0;
+    rt_uint32_t     dst_port = 0;
+    rt_int16_t      src_bidx, dst_bidx;
+    rt_int16_t      src_cidx, dst_cidx;
 
     //edmacc_param paramSet;
 
-	/*
-	 * A-B Sync transfer:  each DMA request is for one "frame" of
-	 * rw_threshold bytes, broken into "acnt"-size chunks repeated
-	 * "bcnt" times.  Each segment needs "ccnt" such frames; since
-	 * we tell the block layer our mmc->max_seg_size limit, we can
-	 * trust (later) that it's within bounds.
-	 *
-	 * The FIFOs are read/written in 4-byte chunks (acnt == 4) and
-	 * EDMA will optimize memory operations to use larger bursts.
-	 */
-	if (tx) 
-	{
-		sync_dev = host->txdma;
+    /*
+     * A-B Sync transfer:  each DMA request is for one "frame" of
+     * rw_threshold bytes, broken into "acnt"-size chunks repeated
+     * "bcnt" times.  Each segment needs "ccnt" such frames; since
+     * we tell the block layer our mmc->max_seg_size limit, we can
+     * trust (later) that it's within bounds.
+     *
+     * The FIFOs are read/written in 4-byte chunks (acnt == 4) and
+     * EDMA will optimize memory operations to use larger bursts.
+     */
+    if (tx)
+    {
+        sync_dev = host->txdma;
+
+        /* src_prt, ccnt, and link to be set up later */
+        /*paramSet.srcBIdx = acnt;
+        paramSet.srcCIdx = acnt * bcnt;
 
-		/* src_prt, ccnt, and link to be set up later */
-		/*paramSet.srcBIdx = acnt;
-		paramSet.srcCIdx = acnt * bcnt;
+        paramSet.destAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR);
+        paramSet.destBIdx = 0;
+        paramSet.destCIdx = 0;*/
+        /* src_prt, ccnt, and link to be set up later */
+        src_bidx = acnt;
+        src_cidx = acnt * bcnt;
 
-		paramSet.destAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR);
-		paramSet.destBIdx = 0;
-		paramSet.destCIdx = 0;*/
-		/* src_prt, ccnt, and link to be set up later */
-		src_bidx = acnt;
-		src_cidx = acnt * bcnt;
+        dst_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR);
+        dst_bidx = 0;
+        dst_cidx = 0;
+    }
+    else
+    {
+        sync_dev = host->rxdma;
 
-		dst_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDXR);
-		dst_bidx = 0;
-		dst_cidx = 0;
-	} 
-	else 
-	{
-		sync_dev = host->rxdma;
+        /* dst_prt, ccnt, and link to be set up later */
+        /*paramSet.srcAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR);
+        paramSet.srcBIdx = 0;
+        paramSet.srcCIdx = 0;
 
-		/* dst_prt, ccnt, and link to be set up later */
-		/*paramSet.srcAddr = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR);
-		paramSet.srcBIdx = 0;
-		paramSet.srcCIdx = 0;
+        paramSet.destBIdx = acnt;
+        paramSet.destCIdx = acnt * bcnt;*/
+        src_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR);
+        src_bidx = 0;
+        src_cidx = 0;
 
-		paramSet.destBIdx = acnt;
-		paramSet.destCIdx = acnt * bcnt;*/
-		src_port = (rt_uint32_t)&(host->mmcsd_regs->MMCDRR);
-		src_bidx = 0;
-		src_cidx = 0;
+        /* dst_prt, ccnt, and link to be set up later */
+        dst_bidx = acnt;
+        dst_cidx = acnt * bcnt;
+    }
+    /*
+     * We can't use FIFO mode for the FIFOs because MMC FIFO addresses
+     * are not 256-bit (32-byte) aligned.  So we use INCR, and the W8BIT
+     * parameter is ignored.
+     */
+    edma_set_src(sync_dev, src_port, INCR, W8BIT);
+    edma_set_dest(sync_dev, dst_port, INCR, W8BIT);
 
-		/* dst_prt, ccnt, and link to be set up later */
-		dst_bidx = acnt;
-		dst_cidx = acnt * bcnt;
-	}
-	/*
-	 * We can't use FIFO mode for the FIFOs because MMC FIFO addresses
-	 * are not 256-bit (32-byte) aligned.  So we use INCR, and the W8BIT
-	 * parameter is ignored.
-	 */
-	edma_set_src(sync_dev, src_port, INCR, W8BIT);
-	edma_set_dest(sync_dev, dst_port, INCR, W8BIT);
+    edma_set_src_index(sync_dev, src_bidx, src_cidx);
+    edma_set_dest_index(sync_dev, dst_bidx, dst_cidx);
 
-	edma_set_src_index(sync_dev, src_bidx, src_cidx);
-	edma_set_dest_index(sync_dev, dst_bidx, dst_cidx);
+    edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC);
 
-	edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC);
+    edma_read_slot(sync_dev, template);
 
-	edma_read_slot(sync_dev, template);
+    /* don't bother with irqs or chaining */
+    template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12;
 
-	/* don't bother with irqs or chaining */
-	template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12;
-	
 #if 0
-	paramSet.opt = 0u;
-	/* Src & Dest are in INCR modes */
-	paramSet.opt &= 0xFFFFFFFCu;
-	/* Program the TCC */
-	paramSet.opt |= ((sync_dev << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
-	
-	paramSet.aCnt = acnt;
-	paramSet.bCnt = bcnt;
-	
-	/* AB Sync Transfer Mode */
-	paramSet.opt |= (1 << EDMA3CC_OPT_SYNCDIM_SHIFT);
-	
-	/* Now, write the PaRAM Set. */
-	EDMA3SetPaRAM(EDMA0CC0_REG_BASE, sync_dev, &paramSet);
+    paramSet.opt = 0u;
+    /* Src & Dest are in INCR modes */
+    paramSet.opt &= 0xFFFFFFFCu;
+    /* Program the TCC */
+    paramSet.opt |= ((sync_dev << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC);
 
-	EDMA3GetPaRAM(EDMA0CC0_REG_BASE, sync_dev, template);
+    paramSet.aCnt = acnt;
+    paramSet.bCnt = bcnt;
+
+    /* AB Sync Transfer Mode */
+    paramSet.opt |= (1 << EDMA3CC_OPT_SYNCDIM_SHIFT);
+
+    /* Now, write the PaRAM Set. */
+    EDMA3SetPaRAM(EDMA0CC0_REG_BASE, sync_dev, &paramSet);
+
+    EDMA3GetPaRAM(EDMA0CC0_REG_BASE, sync_dev, template);
 #endif
 }
 
 /*******************************************************************************************************
 ** 函数名称: mmc_dm365_send_dma_request()
 ** 功能描述: 发送DMA请求
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
-**         data			->	DMA传送数据结构句柄
+**
+** 输　入: host            ->  DM365 mmc host 句柄
+**         data         ->  DMA传送数据结构句柄
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void mmc_dm365_send_dma_request(struct mmc_dm365_host *host, struct rt_mmcsd_data *data)
 {
-	//struct EDMA3CCPaRAMEntry *template;
-	struct edmacc_param	*template;
-	rt_uint32_t	buf_ptr;
-	rt_uint32_t	channel;
-	rt_uint32_t bytes_left = host->bytes_left;
-	rt_uint32_t count = host->bytes_left;	
-	const rt_uint32_t shift = ffs(rw_threshold) - 1;
+    //struct EDMA3CCPaRAMEntry *template;
+    struct edmacc_param *template;
+    rt_uint32_t buf_ptr;
+    rt_uint32_t channel;
+    rt_uint32_t bytes_left = host->bytes_left;
+    rt_uint32_t count = host->bytes_left;
+    const rt_uint32_t shift = ffs(rw_threshold) - 1;
 
-	if (host->use_dma_buffer == RT_TRUE)
-		buf_ptr = host->dma_buffer;//MMU_NOCACHE_ADDR(host->dma_buffer);
-	else
-		buf_ptr = (rt_uint32_t)data->buf;
+    if (host->use_dma_buffer == RT_TRUE)
+        buf_ptr = host->dma_buffer;//MMU_NOCACHE_ADDR(host->dma_buffer);
+    else
+        buf_ptr = (rt_uint32_t)data->buf;
 
-	if (host->data_dir == DM365_MMC_DATADIR_WRITE) 
-	{
-		template = &host->tx_template;
-		channel = host->txdma;
-	} 
-	else 
-	{
-		template = &host->rx_template;
-		channel = host->rxdma;
-	}
+    if (host->data_dir == DM365_MMC_DATADIR_WRITE)
+    {
+        template = &host->tx_template;
+        channel = host->txdma;
+    }
+    else
+    {
+        template = &host->rx_template;
+        channel = host->rxdma;
+    }
 
-	template->link_bcntrld = 0xffff;
-	//template->bCntReload = 0x0;
+    template->link_bcntrld = 0xffff;
+    //template->bCntReload = 0x0;
 
-	if (count > bytes_left)
-		count = bytes_left;
-	bytes_left -= count;
+    if (count > bytes_left)
+        count = bytes_left;
+    bytes_left -= count;
 
-	if (host->data_dir == DM365_MMC_DATADIR_WRITE)
-		template->src = buf_ptr;
-	else
-		template->dst = buf_ptr;
-	template->ccnt = count >> shift;
+    if (host->data_dir == DM365_MMC_DATADIR_WRITE)
+        template->src = buf_ptr;
+    else
+        template->dst = buf_ptr;
+    template->ccnt = count >> shift;
 
-	edma_write_slot(channel, template);
+    edma_write_slot(channel, template);
 
-	edma_clear_event(channel);
+    edma_clear_event(channel);
 
-	/*EDMA3SetPaRAM(EDMA0CC0_REG_BASE, channel, template);
-	EDMA3ClrEvt(EDMA0CC0_REG_BASE, channel);
-	EDMA3EnableTransfer(EDMA0CC0_REG_BASE, channel, EDMA3_TRIG_MODE_EVENT);*/
-	edma_start(channel);
+    /*EDMA3SetPaRAM(EDMA0CC0_REG_BASE, channel, template);
+    EDMA3ClrEvt(EDMA0CC0_REG_BASE, channel);
+    EDMA3EnableTransfer(EDMA0CC0_REG_BASE, channel, EDMA3_TRIG_MODE_EVENT);*/
+    edma_start(channel);
 }
 
 /*******************************************************************************************************
 ** 函数名称: mmc_dm365_start_dma_transfer()
 ** 功能描述: 开始DMA传输
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
-**         data			->	DMA传送数据结构句柄
+**
+** 输　入: host            ->  DM365 mmc host 句柄
+**         data         ->  DMA传送数据结构句柄
 **
 ** 输　出: DMA传输字节数
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static int mmc_dm365_start_dma_transfer(struct mmc_dm365_host *host, struct rt_mmcsd_data *data)
 {
-	/* set initial value */
-	host->use_dma_buffer = RT_FALSE;
+    /* set initial value */
+    host->use_dma_buffer = RT_FALSE;
 
-	if (!(data->flags & DATA_DIR_READ))
-	{
-		if ((rt_uint32_t)data->buf & (RT_ALIGN_SIZE - 1))
-		{
-			/* not align to basic size, use DMA buffer */
-			host->use_dma_buffer = RT_TRUE;
-			memcpy((void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->buf, data->blks * data->blksize);
-		}
-		else
-		{
-			rt_uint32_t addr;
-			addr = ((rt_uint32_t)data->buf & ~(CACHE_LINE_SIZE - 1));
-			/* write data case, always clean DCache */
-			mmu_clean_dcache(addr, (data->blks + 1)* data->blksize);
-		}
-	}
-	else
-	{
-		/* whether align to cache line in read operation */
-		if (((rt_uint32_t)data->buf) & (CACHE_LINE_SIZE - 1))
-			host->use_dma_buffer = RT_TRUE;
-		else
-			mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize);
-	}
+    if (!(data->flags & DATA_DIR_READ))
+    {
+        if ((rt_uint32_t)data->buf & (RT_ALIGN_SIZE - 1))
+        {
+            /* not align to basic size, use DMA buffer */
+            host->use_dma_buffer = RT_TRUE;
+            memcpy((void*)MMU_NOCACHE_ADDR(host->dma_buffer), data->buf, data->blks * data->blksize);
+        }
+        else
+        {
+            rt_uint32_t addr;
+            addr = ((rt_uint32_t)data->buf & ~(CACHE_LINE_SIZE - 1));
+            /* write data case, always clean DCache */
+            mmu_clean_dcache(addr, (data->blks + 1)* data->blksize);
+        }
+    }
+    else
+    {
+        /* whether align to cache line in read operation */
+        if (((rt_uint32_t)data->buf) & (CACHE_LINE_SIZE - 1))
+            host->use_dma_buffer = RT_TRUE;
+        else
+            mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blks * data->blksize);
+    }
 
-	host->do_dma = RT_TRUE;
-	mmc_dm365_send_dma_request(host, data);
+    host->do_dma = RT_TRUE;
+    mmc_dm365_send_dma_request(host, data);
 
-	return 0;
+    return 0;
 }
 
 #if 0
 /*******************************************************************************************************
 ** 函数名称: acquire_dma_channels()
 ** 功能描述: 获取DMA channel
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
+**
+** 输　入: host            ->  DM365 mmc host 句柄
 **
 ** 输　出: DMA 通道号
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static int acquire_dma_channels(struct mmc_dm365_host *host)
 {
-	int r;
+    int r;
 
-	/* Acquire master DMA write channel */
-	r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, host->txdma, EVT_QUEUE_NUM);
-	if (r < 0) 
-	{
-		rt_kprintf("alloc %s channel err %d\n", "tx", r);
-		return r;
-	}
-	mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template);
+    /* Acquire master DMA write channel */
+    r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, host->txdma, EVT_QUEUE_NUM);
+    if (r < 0)
+    {
+        rt_kprintf("alloc %s channel err %d\n", "tx", r);
+        return r;
+    }
+    mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template);
 
-	/* Acquire master DMA read channel */
-	r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->rxdma, host->rxdma, EVT_QUEUE_NUM);
-	if (r < 0) 
-	{
-		rt_kprintf("alloc %s channel err %d\n", "rx", r);
-		goto free_master_write;
-	}
-	mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template);
+    /* Acquire master DMA read channel */
+    r = EDMA3RequestChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->rxdma, host->rxdma, EVT_QUEUE_NUM);
+    if (r < 0)
+    {
+        rt_kprintf("alloc %s channel err %d\n", "rx", r);
+        goto free_master_write;
+    }
+    mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template);
 
-	return 0;
+    return 0;
 
 free_master_write:
-	EDMA3FreeChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, EDMA3_TRIG_MODE_EVENT, host->txdma, EVT_QUEUE_NUM);
+    EDMA3FreeChannel(EDMA0CC0_REG_BASE, EDMA3_CHANNEL_TYPE_DMA, host->txdma, EDMA3_TRIG_MODE_EVENT, host->txdma, EVT_QUEUE_NUM);
 
-	return r;
+    return r;
 }
 #endif
 static int acquire_dma_channels(struct mmc_dm365_host *host)
 {
-	//u32 link_size;
-	int r, i;
+    //u32 link_size;
+    int r, i;
 
-	/* Acquire master DMA write channel */
-	r = edma_alloc_channel(host->txdma, mmc_dm365_dma_cb, host,
-			EVENTQ_DEFAULT);
-	if (r < 0) {
-		mmc_dbg("alloc %s channel err %d\n",
-				"tx", r);
-		return r;
-	}
-	mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template);
+    /* Acquire master DMA write channel */
+    r = edma_alloc_channel(host->txdma, mmc_dm365_dma_cb, host,
+            EVENTQ_DEFAULT);
+    if (r < 0) {
+        mmc_dbg("alloc %s channel err %d\n",
+                "tx", r);
+        return r;
+    }
+    mmc_dm365_dma_setup(host, RT_TRUE, &host->tx_template);
 
-	/* Acquire master DMA read channel */
-	r = edma_alloc_channel(host->rxdma, mmc_dm365_dma_cb, host,
-			EVENTQ_DEFAULT);
-	if (r < 0) {
-		mmc_dbg("alloc %s channel err %d\n",
-				"rx", r);
-		goto free_master_write;
-	}
-	mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template);
+    /* Acquire master DMA read channel */
+    r = edma_alloc_channel(host->rxdma, mmc_dm365_dma_cb, host,
+            EVENTQ_DEFAULT);
+    if (r < 0) {
+        mmc_dbg("alloc %s channel err %d\n",
+                "rx", r);
+        goto free_master_write;
+    }
+    mmc_dm365_dma_setup(host, RT_FALSE, &host->rx_template);
 
-	/* Allocate parameter RAM slots, which will later be bound to a
-	 * channel as needed to handle a scatterlist.
-	 */
+    /* Allocate parameter RAM slots, which will later be bound to a
+     * channel as needed to handle a scatterlist.
+     */
 #if 0
-	link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links));
-	for (i = 0; i < link_size; i++) {
-		r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY);
-		if (r < 0) {
-			mmc_dbg("dma PaRAM alloc --> %d\n",
-				r);
-			break;
-		}
-		host->links[i] = r;
-	}
-	host->n_link = i;
+    link_size = min_t(unsigned, host->nr_sg, ARRAY_SIZE(host->links));
+    for (i = 0; i < link_size; i++) {
+        r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY);
+        if (r < 0) {
+            mmc_dbg("dma PaRAM alloc --> %d\n",
+                r);
+            break;
+        }
+        host->links[i] = r;
+    }
+    host->n_link = i;
 #endif
 
-	return 0;
+    return 0;
 
 free_master_write:
-	edma_free_channel(host->txdma);
+    edma_free_channel(host->txdma);
 
-	return r;
+    return r;
 }
 
 
 /*******************************************************************************************************
 ** 函数名称: mmc_dm365_prepare_data()
 ** 功能描述: 准备 DMA 数据
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
-**         req			->	SD request 结构句柄
+**
+** 输　入: host            ->  DM365 mmc host 句柄
+**         req          ->  SD request 结构句柄
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void mmc_dm365_prepare_data(struct mmc_dm365_host *host, struct rt_mmcsd_req *req)
 {
-	int timeout;
-	int fifo_lev;
-	struct rt_mmcsd_data *data = req->data;
+    int timeout;
+    int fifo_lev;
+    struct rt_mmcsd_data *data = req->data;
+
+    fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0;
 
-	fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0;
+    host->data = data;
+    if (data == RT_NULL)
+    {
+        host->data_dir = DM365_MMC_DATADIR_NONE;
+        host->mmcsd_regs->MMCBLEN = 0;
+        host->mmcsd_regs->MMCNBLK = 0;
+        return;
+    }
 
-	host->data = data;
-	if (data == RT_NULL) 
-	{
-		host->data_dir = DM365_MMC_DATADIR_NONE;
-		host->mmcsd_regs->MMCBLEN = 0;
-		host->mmcsd_regs->MMCNBLK = 0;
-		return;
-	}
+    mmc_dbg("%s %s, %d blocks of %d bytes\n",
+        (data->flags & DATA_STREAM) ? "stream" : "block",
+        (data->flags & DATA_DIR_WRITE) ? "write" : "read",
+        data->blks, data->blksize);
+    mmc_dbg("  DTO %d cycles + %d ns\n",
+        data->timeout_clks, data->timeout_ns);
+    timeout = data->timeout_clks + (data->timeout_ns / host->ns_in_one_cycle);
+    if (timeout > 0xffff)
+        timeout = 0xffff;
 
-	mmc_dbg("%s %s, %d blocks of %d bytes\n",
-		(data->flags & DATA_STREAM) ? "stream" : "block",
-		(data->flags & DATA_DIR_WRITE) ? "write" : "read",
-		data->blks, data->blksize);
-	mmc_dbg("  DTO %d cycles + %d ns\n",
-		data->timeout_clks, data->timeout_ns);
-	timeout = data->timeout_clks + (data->timeout_ns / host->ns_in_one_cycle);
-	if (timeout > 0xffff)
-		timeout = 0xffff;
+    host->mmcsd_regs->MMCTOD = timeout;
+    host->mmcsd_regs->MMCNBLK = data->blks;
+    host->mmcsd_regs->MMCBLEN = data->blksize;
 
-	host->mmcsd_regs->MMCTOD = timeout;
-	host->mmcsd_regs->MMCNBLK = data->blks;
-	host->mmcsd_regs->MMCBLEN = data->blksize;
-	
-	/* Configure the FIFO */
-	switch (data->flags & DATA_DIR_WRITE) 
-	{
-	case DATA_DIR_WRITE:
-		host->data_dir = DM365_MMC_DATADIR_WRITE;
-		host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST;
-		host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR;
-		break;
+    /* Configure the FIFO */
+    switch (data->flags & DATA_DIR_WRITE)
+    {
+    case DATA_DIR_WRITE:
+        host->data_dir = DM365_MMC_DATADIR_WRITE;
+        host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST;
+        host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_WR;
+        break;
 
-	default:
-		host->data_dir = DM365_MMC_DATADIR_READ;
-		host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST;
-		host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD;
-		break;
-	}
+    default:
+        host->data_dir = DM365_MMC_DATADIR_READ;
+        host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST;
+        host->mmcsd_regs->MMCFIFOCTL = fifo_lev | MMCFIFOCTL_FIFODIR_RD;
+        break;
+    }
 
-	host->buffer = RT_NULL;
-	host->bytes_left = data->blks * data->blksize;
+    host->buffer = RT_NULL;
+    host->bytes_left = data->blks * data->blksize;
 
-	/* For now we try to use DMA whenever we won't need partial FIFO
-	 * reads or writes, either for the whole transfer (as tested here)
-	 * or for any individual scatterlist segment (tested when we call
-	 * start_dma_transfer).
-	 *
-	 * While we *could* change that, unusual block sizes are rarely
-	 * used.  The occasional fallback to PIO should't hurt.
-	 */
-	if ((host->use_dma == RT_TRUE) && (host->bytes_left & (rw_threshold - 1)) == 0 &&
-			mmc_dm365_start_dma_transfer(host, data) == 0)
-	{
-		/* zero this to ensure we take no PIO paths */
-		host->bytes_left = 0;
-	} 
-	else 
-	{
-		/* Revert to CPU Copy */
-		host->buffer = (rt_uint8_t*)req->data->buf;
-	}
+    /* For now we try to use DMA whenever we won't need partial FIFO
+     * reads or writes, either for the whole transfer (as tested here)
+     * or for any individual scatterlist segment (tested when we call
+     * start_dma_transfer).
+     *
+     * While we *could* change that, unusual block sizes are rarely
+     * used.  The occasional fallback to PIO should't hurt.
+     */
+    if ((host->use_dma == RT_TRUE) && (host->bytes_left & (rw_threshold - 1)) == 0 &&
+            mmc_dm365_start_dma_transfer(host, data) == 0)
+    {
+        /* zero this to ensure we take no PIO paths */
+        host->bytes_left = 0;
+    }
+    else
+    {
+        /* Revert to CPU Copy */
+        host->buffer = (rt_uint8_t*)req->data->buf;
+    }
 }
 
 /*******************************************************************************************************
 ** 函数名称: mmc_dm365_request()
 ** 功能描述: 此函数实现SD request操作
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
-**         req			->	SD request 结构句柄
+**
+** 输　入: host            ->  DM365 mmc host 句柄
+**         req          ->  SD request 结构句柄
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void mmc_dm365_request(struct rt_mmcsd_host *mmc, struct rt_mmcsd_req *req)
 {
-	struct mmc_dm365_host *host = mmc_priv(mmc);
-	unsigned long timeout = rt_tick_get() + 900;
-	rt_uint32_t mmcst1 = 0;
+    struct mmc_dm365_host *host = mmc_priv(mmc);
+    unsigned long timeout = rt_tick_get() + 900;
+    rt_uint32_t mmcst1 = 0;
 
-	/* Card may still be sending BUSY after a previous operation,
-	 * typically some kind of write.  If so, we can't proceed yet.
-	 */
-	while (rt_tick_get() < timeout) 
+    /* Card may still be sending BUSY after a previous operation,
+     * typically some kind of write.  If so, we can't proceed yet.
+     */
+    while (rt_tick_get() < timeout)
     {
-		mmcst1  = host->mmcsd_regs->MMCST1;
-		if (!(mmcst1 & MMCST1_BUSY))
-			break;
-	}
-	if (mmcst1 & MMCST1_BUSY) 
+        mmcst1  = host->mmcsd_regs->MMCST1;
+        if (!(mmcst1 & MMCST1_BUSY))
+            break;
+    }
+    if (mmcst1 & MMCST1_BUSY)
     {
-		mmc_dbg("still BUSY? bad ... \n");
-		req->cmd->err = -RT_ETIMEOUT;
-		mmc_request_done(mmc, req);
-		return;
-	}
+        mmc_dbg("still BUSY? bad ... \n");
+        req->cmd->err = -RT_ETIMEOUT;
+        mmc_request_done(mmc, req);
+        return;
+    }
 
-	host->do_dma = RT_FALSE;
-	mmc_dm365_prepare_data(host, req);
-	mmc_dm365_start_command(host, req->cmd);
+    host->do_dma = RT_FALSE;
+    mmc_dm365_prepare_data(host, req);
+    mmc_dm365_start_command(host, req->cmd);
 }
 
 static void mmc_dm365_enable_sdio_irq(struct rt_mmcsd_host *mmc, rt_int32_t enable)
 {
-	struct mmc_dm365_host *host = mmc_priv(mmc);
+    struct mmc_dm365_host *host = mmc_priv(mmc);
 
-	if (enable) 
-	{
-		if (!(host->mmcsd_regs->SDIOST0 & SDIOST0_DAT1_HI)) 
-		{
-			host->mmcsd_regs->SDIOIST = SDIOIST_IOINT;
-			sdio_irq_wakeup(host->mmc);
-		} 
-		else 
-		{
-			host->sdio_int = RT_TRUE;
-			host->mmcsd_regs->SDIOIEN |= SDIOIEN_IOINTEN;
-		}
-	} 
-	else 
-	{
-		host->sdio_int = RT_FALSE;
-		host->mmcsd_regs->SDIOIEN &= ~SDIOIEN_IOINTEN;
-	}
+    if (enable)
+    {
+        if (!(host->mmcsd_regs->SDIOST0 & SDIOST0_DAT1_HI))
+        {
+            host->mmcsd_regs->SDIOIST = SDIOIST_IOINT;
+            sdio_irq_wakeup(host->mmc);
+        }
+        else
+        {
+            host->sdio_int = RT_TRUE;
+            host->mmcsd_regs->SDIOIEN |= SDIOIEN_IOINTEN;
+        }
+    }
+    else
+    {
+        host->sdio_int = RT_FALSE;
+        host->mmcsd_regs->SDIOIEN &= ~SDIOIEN_IOINTEN;
+    }
 }
 
 
-static const struct rt_mmcsd_host_ops mmc_dm365_ops = 
+static const struct rt_mmcsd_host_ops mmc_dm365_ops =
 {
-	mmc_dm365_request,
-	mmc_dm365_set_ios,
+    mmc_dm365_request,
+    mmc_dm365_set_ios,
     RT_NULL,
     mmc_dm365_enable_sdio_irq
 };
@@ -1059,409 +1059,409 @@ static const struct rt_mmcsd_host_ops mmc_dm365_ops =
 /*******************************************************************************************************
 ** 函数名称: mmc_dm365_reset_ctrl()
 ** 功能描述: 此函数用于reset mmc控制器
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
-**         val			->	判断做reset还是enable
+**
+** 输　入: host            ->  DM365 mmc host 句柄
+**         val          ->  判断做reset还是enable
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void mmc_dm365_reset_ctrl(struct mmc_dm365_host *host, int val)
 {
-	rt_uint32_t temp;
+    rt_uint32_t temp;
+
+    temp = host->mmcsd_regs->MMCCTL;
 
-	temp = host->mmcsd_regs->MMCCTL;
-	
-	if (val)	/* reset */
-		temp |= MMCCTL_CMDRST | MMCCTL_DATRST;
-	else		/* enable */
-		temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST);
+    if (val)    /* reset */
+        temp |= MMCCTL_CMDRST | MMCCTL_DATRST;
+    else        /* enable */
+        temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST);
 
-	host->mmcsd_regs->MMCCTL = temp;
+    host->mmcsd_regs->MMCCTL = temp;
 
-	delay_us(10);
+    delay_us(10);
 }
 
 /*******************************************************************************************************
 ** 函数名称: init_mmcsd_host()
 ** 功能描述: 此函数用于初始化DM365 MMCSD控制器
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
+**
+** 输　入: host            ->  DM365 mmc host 句柄
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void init_mmcsd_host(struct mmc_dm365_host *host)
 {
-	mmc_dm365_reset_ctrl(host, 1);
+    mmc_dm365_reset_ctrl(host, 1);
+
+    host->mmcsd_regs->MMCCLK = 0;
+    host->mmcsd_regs->MMCCLK = MMCCLK_CLKEN;
 
-	host->mmcsd_regs->MMCCLK = 0;
-	host->mmcsd_regs->MMCCLK = MMCCLK_CLKEN;
+    host->mmcsd_regs->MMCTOR = 0x1FFF;
+    host->mmcsd_regs->MMCTOD = 0xFFFF;
 
-	host->mmcsd_regs->MMCTOR = 0x1FFF;
-	host->mmcsd_regs->MMCTOD = 0xFFFF;
-	
-	mmc_dm365_reset_ctrl(host, 0);
+    mmc_dm365_reset_ctrl(host, 0);
 }
 
 /*******************************************************************************************************
 ** 函数名称: mmc_dm365_cmd_done()
 ** 功能描述: 结束SD 命令后调用此函数
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
-**         cmd			->	SD 命令结构句柄
+**
+** 输　入: host            ->  DM365 mmc host 句柄
+**         cmd          ->  SD 命令结构句柄
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void mmc_dm365_cmd_done(struct mmc_dm365_host *host, struct rt_mmcsd_cmd *cmd)
 {
-	host->cmd = RT_NULL;
+    host->cmd = RT_NULL;
 
-	if (resp_type(cmd) != RESP_NONE) 
-	{
-		if (resp_type(cmd) == RESP_R2) 
-		{
-			/* response type 2 */
-			cmd->resp[3] = host->mmcsd_regs->MMCRSP01;
-			cmd->resp[2] = host->mmcsd_regs->MMCRSP23;
-			cmd->resp[1] = host->mmcsd_regs->MMCRSP45;
-			cmd->resp[0] = host->mmcsd_regs->MMCRSP67;
-		} 
-		else 
-		{
-			/* response types 1, 1b, 3, 4, 5, 6 */
-			cmd->resp[0] = host->mmcsd_regs->MMCRSP67;
-		}
-	}
+    if (resp_type(cmd) != RESP_NONE)
+    {
+        if (resp_type(cmd) == RESP_R2)
+        {
+            /* response type 2 */
+            cmd->resp[3] = host->mmcsd_regs->MMCRSP01;
+            cmd->resp[2] = host->mmcsd_regs->MMCRSP23;
+            cmd->resp[1] = host->mmcsd_regs->MMCRSP45;
+            cmd->resp[0] = host->mmcsd_regs->MMCRSP67;
+        }
+        else
+        {
+            /* response types 1, 1b, 3, 4, 5, 6 */
+            cmd->resp[0] = host->mmcsd_regs->MMCRSP67;
+        }
+    }
 
-	if (host->data == RT_NULL || cmd->err) 
-	{
-		if (cmd->err == -RT_ETIMEOUT)
-			cmd->mrq->cmd->retries = 0;
-		mmc_request_done(host->mmc, cmd->mrq);
-		host->mmcsd_regs->MMCIM = 0;
-	}
+    if (host->data == RT_NULL || cmd->err)
+    {
+        if (cmd->err == -RT_ETIMEOUT)
+            cmd->mrq->cmd->retries = 0;
+        mmc_request_done(host->mmc, cmd->mrq);
+        host->mmcsd_regs->MMCIM = 0;
+    }
 }
 
 /*******************************************************************************************************
 ** 函数名称: dm365_abort_data()
 ** 功能描述: 此函数用于终止数据传输
-** 
-** 输　入: host			->	DM365 mmc host 句柄 
-**         data			->	data 结构句柄
+**
+** 输　入: host            ->  DM365 mmc host 句柄
+**         data         ->  data 结构句柄
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void dm365_abort_data(struct mmc_dm365_host *host, struct rt_mmcsd_data *data)
 {
-	mmc_dm365_reset_ctrl(host, 1);
-	mmc_dm365_reset_ctrl(host, 0);
+    mmc_dm365_reset_ctrl(host, 1);
+    mmc_dm365_reset_ctrl(host, 0);
 }
 
 static void mmc_dm365_sdio_irq(int irq, void *param)
 {
-	struct mmc_dm365_host *host = (struct mmc_dm365_host *)param;
-	rt_uint32_t status;
+    struct mmc_dm365_host *host = (struct mmc_dm365_host *)param;
+    rt_uint32_t status;
 
-	status = host->mmcsd_regs->SDIOIST;//readl(host->base + DAVINCI_SDIOIST);
-	if (status & SDIOIST_IOINT) {
-		mmc_dbg("SDIO interrupt status %x\n", status);
-		//writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
-		host->mmcsd_regs->SDIOIST = status | SDIOIST_IOINT;
-		sdio_irq_wakeup(host->mmc);
-	}
+    status = host->mmcsd_regs->SDIOIST;//readl(host->base + DAVINCI_SDIOIST);
+    if (status & SDIOIST_IOINT) {
+        mmc_dbg("SDIO interrupt status %x\n", status);
+        //writel(status | SDIOIST_IOINT, host->base + DAVINCI_SDIOIST);
+        host->mmcsd_regs->SDIOIST = status | SDIOIST_IOINT;
+        sdio_irq_wakeup(host->mmc);
+    }
 }
 
 
 /*******************************************************************************************************
 ** 函数名称: mmc_dm365_irq()
 ** 功能描述: MMCSD的中断处理程序
-** 
-** 输　入: irq	->中断向量号
+**
+** 输　入: irq ->中断向量号
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void mmc_dm365_irq(int irq, void *param)
 {
-	struct mmc_dm365_host *host = (struct mmc_dm365_host *)param;
-	rt_uint32_t status, qstatus;
-	int end_command = 0;
-	int end_transfer = 0;
-	struct rt_mmcsd_data *data = host->data;
+    struct mmc_dm365_host *host = (struct mmc_dm365_host *)param;
+    rt_uint32_t status, qstatus;
+    int end_command = 0;
+    int end_transfer = 0;
+    struct rt_mmcsd_data *data = host->data;
+
+    if (host->cmd == RT_NULL && host->data == RT_NULL)
+    {
+        status = host->mmcsd_regs->MMCST0;
+        mmc_dbg("Spurious interrupt 0x%04x\n", status);
+        /* Disable the interrupt from mmcsd */
+        host->mmcsd_regs->MMCIM = 0;
+        return;
+    }
 
-	if (host->cmd == RT_NULL && host->data == RT_NULL) 
-	{
-		status = host->mmcsd_regs->MMCST0;
-		mmc_dbg("Spurious interrupt 0x%04x\n", status);
-		/* Disable the interrupt from mmcsd */
-		host->mmcsd_regs->MMCIM = 0;
-		return;
-	}
+    status = host->mmcsd_regs->MMCST0;
+    qstatus = status;
 
-	status = host->mmcsd_regs->MMCST0;
-	qstatus = status;
-	
-	/* handle FIFO first when using PIO for data.
-	 * bytes_left will decrease to zero as I/O progress and status will
-	 * read zero over iteration because this controller status
-	 * register(MMCST0) reports any status only once and it is cleared
-	 * by read. So, it is not unbouned loop even in the case of
-	 * non-dma.
-	 */
-	while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) 
-	{
-		dm365_fifo_data_trans(host, rw_threshold);
-		status = host->mmcsd_regs->MMCST0;
-		if (!status)
-			break;
-		qstatus |= status;
-	}
+    /* handle FIFO first when using PIO for data.
+     * bytes_left will decrease to zero as I/O progress and status will
+     * read zero over iteration because this controller status
+     * register(MMCST0) reports any status only once and it is cleared
+     * by read. So, it is not unbouned loop even in the case of
+     * non-dma.
+     */
+    while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY)))
+    {
+        dm365_fifo_data_trans(host, rw_threshold);
+        status = host->mmcsd_regs->MMCST0;
+        if (!status)
+            break;
+        qstatus |= status;
+    }
 
-	if (qstatus & MMCST0_DATDNE) 
-	{
-		/* All blocks sent/received, and CRC checks passed */
-		if (data != RT_NULL) 
-		{
-			if ((host->do_dma == RT_FALSE) && (host->bytes_left > 0))
-			{
-				/* if datasize < rw_threshold
-				 * no RX ints are generated
-				 */
-				rt_kprintf("to do! host->bytes_left=0x%x\n", host->bytes_left);
-				dm365_fifo_data_trans(host, host->bytes_left);
-			}
-			end_transfer = 1;
-			data->bytes_xfered = data->blks* data->blksize;
-		} 
-		else 
-		{
-			mmc_dbg("DATDNE with no host->data\n");
-		}
-	}
+    if (qstatus & MMCST0_DATDNE)
+    {
+        /* All blocks sent/received, and CRC checks passed */
+        if (data != RT_NULL)
+        {
+            if ((host->do_dma == RT_FALSE) && (host->bytes_left > 0))
+            {
+                /* if datasize < rw_threshold
+                 * no RX ints are generated
+                 */
+                rt_kprintf("to do! host->bytes_left=0x%x\n", host->bytes_left);
+                dm365_fifo_data_trans(host, host->bytes_left);
+            }
+            end_transfer = 1;
+            data->bytes_xfered = data->blks* data->blksize;
+        }
+        else
+        {
+            mmc_dbg("DATDNE with no host->data\n");
+        }
+    }
 
-	if (qstatus & MMCST0_TOUTRD) 
-	{
-		/* Read data timeout */
-		data->err = -RT_ETIMEOUT;
-		end_transfer = 1;
+    if (qstatus & MMCST0_TOUTRD)
+    {
+        /* Read data timeout */
+        data->err = -RT_ETIMEOUT;
+        end_transfer = 1;
 
-		mmc_dbg("read data timeout, status %x\n", qstatus);
-		rt_kprintf("read data timeout, status %x\n", qstatus);
+        mmc_dbg("read data timeout, status %x\n", qstatus);
+        rt_kprintf("read data timeout, status %x\n", qstatus);
 
-		dm365_abort_data(host, data);
-	}
+        dm365_abort_data(host, data);
+    }
 
-	if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) 
-	{
-		/* Data CRC error */
-		data->err = -RT_ERROR;
-		end_transfer = 1;
+    if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD))
+    {
+        /* Data CRC error */
+        data->err = -RT_ERROR;
+        end_transfer = 1;
 
-		/* NOTE:  this controller uses CRCWR to report both CRC
-		 * errors and timeouts (on writes).  MMCDRSP values are
-		 * only weakly documented, but 0x9f was clearly a timeout
-		 * case and the two three-bit patterns in various SD specs
-		 * (101, 010) aren't part of it ...
-		 */
-		if (qstatus & MMCST0_CRCWR) 
-		{
-			rt_uint32_t temp = host->mmcsd_regs->MMCDRSP;
+        /* NOTE:  this controller uses CRCWR to report both CRC
+         * errors and timeouts (on writes).  MMCDRSP values are
+         * only weakly documented, but 0x9f was clearly a timeout
+         * case and the two three-bit patterns in various SD specs
+         * (101, 010) aren't part of it ...
+         */
+        if (qstatus & MMCST0_CRCWR)
+        {
+            rt_uint32_t temp = host->mmcsd_regs->MMCDRSP;
 
-			if (temp == 0x9f)
-				data->err = -RT_ETIMEOUT;
-		}
-		mmc_dbg("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC");
+            if (temp == 0x9f)
+                data->err = -RT_ETIMEOUT;
+        }
+        mmc_dbg("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC");
 
-		rt_kprintf("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC");
+        rt_kprintf("data %s %s error\n", (qstatus & MMCST0_CRCWR) ? "write" : "read", (data->err == -110) ? "timeout" : "CRC");
 
-		dm365_abort_data(host, data);
-	}
+        dm365_abort_data(host, data);
+    }
 
-	if (qstatus & MMCST0_TOUTRS) 
-	{
-		/* Command timeout */
-		if (host->cmd) 
-		{
-			mmc_dbg("CMD%d timeout, status %x\n", host->cmd->cmd_code, qstatus);
-			host->cmd->err = -RT_ETIMEOUT;
-			if (data) 
-			{
-				end_transfer = 1;
-				dm365_abort_data(host, data);
-			}
-			else
-				end_command = 1;
-		}
-	}
+    if (qstatus & MMCST0_TOUTRS)
+    {
+        /* Command timeout */
+        if (host->cmd)
+        {
+            mmc_dbg("CMD%d timeout, status %x\n", host->cmd->cmd_code, qstatus);
+            host->cmd->err = -RT_ETIMEOUT;
+            if (data)
+            {
+                end_transfer = 1;
+                dm365_abort_data(host, data);
+            }
+            else
+                end_command = 1;
+        }
+    }
 
-	if (qstatus & MMCST0_CRCRS) 
-	{
-		/* Command CRC error */
-		mmc_dbg("Command CRC error\n");
-		if (host->cmd) 
-		{
-			host->cmd->err = -RT_ERROR;
-			end_command = 1;
-		}
-	}
+    if (qstatus & MMCST0_CRCRS)
+    {
+        /* Command CRC error */
+        mmc_dbg("Command CRC error\n");
+        if (host->cmd)
+        {
+            host->cmd->err = -RT_ERROR;
+            end_command = 1;
+        }
+    }
 
-	if (qstatus & MMCST0_RSPDNE) 
-	{
-		/* End of command phase */
-		end_command = (int) host->cmd;
-	}
+    if (qstatus & MMCST0_RSPDNE)
+    {
+        /* End of command phase */
+        end_command = (int) host->cmd;
+    }
 
-	if (end_command)
-		mmc_dm365_cmd_done(host, host->cmd);
-	if (end_transfer)
-		mmc_dm365_xfer_done(host, data);
+    if (end_command)
+        mmc_dm365_cmd_done(host, host->cmd);
+    if (end_transfer)
+        mmc_dm365_xfer_done(host, data);
 
-	return;
+    return;
 }
 #if 0
 
 /*******************************************************************************************************
 ** 函数名称: rt_hw_edma_init()
 ** 功能描述: 此函数用于初始化EDMA3
-** 
+**
 ** 输　入: 无
 **
 ** 输　出: 无
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 static void rt_hw_edma_init(void)
 {
-	psc_transition(PSC0, DOMAIN0, LPSC_TPCC, PSC_ENABLE);
-	psc_transition(PSC0, DOMAIN0, LPSC_TPTC0, PSC_ENABLE);
+    psc_transition(PSC0, DOMAIN0, LPSC_TPCC, PSC_ENABLE);
+    psc_transition(PSC0, DOMAIN0, LPSC_TPTC0, PSC_ENABLE);
 
-    /* Initialization of EDMA3 */    
+    /* Initialization of EDMA3 */
     edma3_init(EDMA0CC0_REG_BASE, EVT_QUEUE_NUM);
-   
+
     /* Register EDMA3 Interrupts */
-//	ConfigureAINTCIntEDMA3();
+//  ConfigureAINTCIntEDMA3();
 }
 #endif
 /*******************************************************************************************************
 ** 函数名称: rt_hw_mmcsd_init()
 ** 功能描述: 此函数用于初始化MMC驱动模块
-** 
+**
 ** 输　入: 无
 **
 ** 输　出: 如果初始化成功，返回0；如果初始化失败，返回-RT_ENOMEM
-**         
-** 全局变量: 
+**
+** 全局变量:
 ** 调用模块: 无
 **
 ********************************************************************************************************/
 int rt_hw_mmcsd_init(void)
 {
-	struct clk  *clk;
-	struct mmc_dm365_host *dm365_host;
-	struct rt_mmcsd_host *mmc = RT_NULL;
+    struct clk  *clk;
+    struct mmc_dm365_host *dm365_host;
+    struct rt_mmcsd_host *mmc = RT_NULL;
 
-	mmc = mmcsd_alloc_host();
-	if (!mmc) 
-	{
-		mmc_dbg("alloc mmc failed\n");
-		return -RT_ERROR;
-	}
+    mmc = mmcsd_alloc_host();
+    if (!mmc)
+    {
+        mmc_dbg("alloc mmc failed\n");
+        return -RT_ERROR;
+    }
 
-	dm365_host = rt_malloc(sizeof(struct mmc_dm365_host));
-	if (!dm365_host) 
-	{
-		mmc_dbg("alloc mci failed\n");
-		goto err;
-	}
+    dm365_host = rt_malloc(sizeof(struct mmc_dm365_host));
+    if (!dm365_host)
+    {
+        mmc_dbg("alloc mci failed\n");
+        goto err;
+    }
 
-	rt_memset(dm365_host, 0, sizeof(struct mmc_dm365_host));
+    rt_memset(dm365_host, 0, sizeof(struct mmc_dm365_host));
 
 #ifdef RT_USING_MMCSD0
-	//psc_transition(PSC0, DOMAIN0, LPSC_MMCSD0, PSC_ENABLE);
-	//pinmux_config(PINMUX_MMCSD0_REG, PINMUX_MMCSD0_MASK, PINMUX_MMCSD0_VAL);
-	psc_change_state(DAVINCI_DM365_LPSC_MMC_SD0, PSC_ENABLE);
-	dm365_host->mmcsd_regs = (mmcsd_regs_t *)DM365_MMC_SD0_BASE;
+    //psc_transition(PSC0, DOMAIN0, LPSC_MMCSD0, PSC_ENABLE);
+    //pinmux_config(PINMUX_MMCSD0_REG, PINMUX_MMCSD0_MASK, PINMUX_MMCSD0_VAL);
+    psc_change_state(DAVINCI_DM365_LPSC_MMC_SD0, PSC_ENABLE);
+    dm365_host->mmcsd_regs = (mmcsd_regs_t *)DM365_MMC_SD0_BASE;
 #else
 #ifdef RT_USING_MMCSD1
-	psc_transition(PSC1, DOMAIN0, LPSC_MMCSD1, PSC_ENABLE);
-	pinmux_config(PINMUX_MMCSD1_REG, PINMUX_MMCSD1_MASK, PINMUX_MMCSD1_VAL);
-	dm365_host->mmcsd_regs = MMCSD1;
+    psc_transition(PSC1, DOMAIN0, LPSC_MMCSD1, PSC_ENABLE);
+    pinmux_config(PINMUX_MMCSD1_REG, PINMUX_MMCSD1_MASK, PINMUX_MMCSD1_VAL);
+    dm365_host->mmcsd_regs = MMCSD1;
 #endif
 #endif
 
-	//rt_hw_edma_init();
+    //rt_hw_edma_init();
 
-	clk = clk_get("MMCSDCLK0");
-	dm365_host->mmc_input_clk = clk_get_rate(clk);
-	dm365_host->rxdma = DM365_DMA_MMC0RXEVT;
-	dm365_host->txdma = DM365_DMA_MMC0TXEVT;
-	dm365_host->use_dma = use_dma;
-	if ((dm365_host->use_dma == RT_TRUE)&& acquire_dma_channels(dm365_host) != 0)
-	{
-		dm365_host->use_dma = RT_FALSE;
-	}
-	else
-	{
-		dm365_host->dma_buffer = (rt_uint8_t*)rt_malloc_align(64*1024, 32);
-		if (dm365_host->dma_buffer == RT_NULL)
-			dm365_host->use_dma = RT_FALSE;
-	}
+    clk = clk_get("MMCSDCLK0");
+    dm365_host->mmc_input_clk = clk_get_rate(clk);
+    dm365_host->rxdma = DM365_DMA_MMC0RXEVT;
+    dm365_host->txdma = DM365_DMA_MMC0TXEVT;
+    dm365_host->use_dma = use_dma;
+    if ((dm365_host->use_dma == RT_TRUE)&& acquire_dma_channels(dm365_host) != 0)
+    {
+        dm365_host->use_dma = RT_FALSE;
+    }
+    else
+    {
+        dm365_host->dma_buffer = (rt_uint8_t*)rt_malloc_align(64*1024, 32);
+        if (dm365_host->dma_buffer == RT_NULL)
+            dm365_host->use_dma = RT_FALSE;
+    }
 
-	mmc->ops = &mmc_dm365_ops;
-	mmc->freq_min = 312500;
-	mmc->freq_max = 25000000;
-	mmc->valid_ocr = VDD_32_33 | VDD_33_34;
-	mmc->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE;
-	mmc->flags |= MMCSD_SUP_SDIO_IRQ;
+    mmc->ops = &mmc_dm365_ops;
+    mmc->freq_min = 312500;
+    mmc->freq_max = 25000000;
+    mmc->valid_ocr = VDD_32_33 | VDD_33_34;
+    mmc->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE;
+    mmc->flags |= MMCSD_SUP_SDIO_IRQ;
 
-	dm365_host->mmc = mmc;
-	mmc->private_data = dm365_host;
+    dm365_host->mmc = mmc;
+    mmc->private_data = dm365_host;
 
-	/* install interrupt */
+    /* install interrupt */
 #ifdef RT_USING_MMCSD0
-	rt_hw_interrupt_install(IRQ_DM3XX_MMCINT0, mmc_dm365_irq, 
-							(void *)dm365_host, "MMC0");
-	rt_hw_interrupt_umask(IRQ_DM3XX_MMCINT0);
-	rt_hw_interrupt_install(IRQ_DM3XX_SDIOINT0, mmc_dm365_sdio_irq, 
-							(void *)dm365_host, "SDIO0");
-	rt_hw_interrupt_umask(IRQ_DM3XX_SDIOINT0);
+    rt_hw_interrupt_install(IRQ_DM3XX_MMCINT0, mmc_dm365_irq,
+                            (void *)dm365_host, "MMC0");
+    rt_hw_interrupt_umask(IRQ_DM3XX_MMCINT0);
+    rt_hw_interrupt_install(IRQ_DM3XX_SDIOINT0, mmc_dm365_sdio_irq,
+                            (void *)dm365_host, "SDIO0");
+    rt_hw_interrupt_umask(IRQ_DM3XX_SDIOINT0);
 #endif
 #ifdef RT_USING_MMCSD1
-	rt_hw_interrupt_install(MMCSD_INT1, mmc_dm365_irq, 
-							(void *)dm365_host, "MMC1");
-	rt_hw_interrupt_umask(MMCSD_INT1);
+    rt_hw_interrupt_install(MMCSD_INT1, mmc_dm365_irq,
+                            (void *)dm365_host, "MMC1");
+    rt_hw_interrupt_umask(MMCSD_INT1);
 #endif
 
-	init_mmcsd_host(dm365_host);
+    init_mmcsd_host(dm365_host);
 
-	mmcsd_change(mmc);
+    mmcsd_change(mmc);
 
-	return 0;
+    return 0;
 
 err:
-	mmcsd_free_host(mmc);
+    mmcsd_free_host(mmc);
 
-	return -RT_ENOMEM;
+    return -RT_ENOMEM;
 }
 
 INIT_DEVICE_EXPORT(rt_hw_mmcsd_init);
diff --git a/bsp/dm365/drivers/mmcsd.h b/bsp/dm365/drivers/mmcsd.h
index 70a57b87f3..812b44a72e 100644
--- a/bsp/dm365/drivers/mmcsd.h
+++ b/bsp/dm365/drivers/mmcsd.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 #ifndef __DAVINCI_MMC_H__
@@ -30,18 +30,18 @@
 #define MMCCLK_CLKRT_MASK     (0xFF << 0)
 
 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
-#define MMCST0_DATDNE         (1 << 0)	/* data done */
-#define MMCST0_BSYDNE         (1 << 1)	/* busy done */
-#define MMCST0_RSPDNE         (1 << 2)	/* command done */
-#define MMCST0_TOUTRD         (1 << 3)	/* data read timeout */
-#define MMCST0_TOUTRS         (1 << 4)	/* command response timeout */
-#define MMCST0_CRCWR          (1 << 5)	/* data write CRC error */
-#define MMCST0_CRCRD          (1 << 6)	/* data read CRC error */
-#define MMCST0_CRCRS          (1 << 7)	/* command response CRC error */
-#define MMCST0_DXRDY          (1 << 9)	/* data transmit ready (fifo empty) */
-#define MMCST0_DRRDY          (1 << 10)	/* data receive ready (data in fifo)*/
-#define MMCST0_DATED          (1 << 11)	/* DAT3 edge detect */
-#define MMCST0_TRNDNE         (1 << 12)	/* transfer done */
+#define MMCST0_DATDNE         (1 << 0)  /* data done */
+#define MMCST0_BSYDNE         (1 << 1)  /* busy done */
+#define MMCST0_RSPDNE         (1 << 2)  /* command done */
+#define MMCST0_TOUTRD         (1 << 3)  /* data read timeout */
+#define MMCST0_TOUTRS         (1 << 4)  /* command response timeout */
+#define MMCST0_CRCWR          (1 << 5)  /* data write CRC error */
+#define MMCST0_CRCRD          (1 << 6)  /* data read CRC error */
+#define MMCST0_CRCRS          (1 << 7)  /* command response CRC error */
+#define MMCST0_DXRDY          (1 << 9)  /* data transmit ready (fifo empty) */
+#define MMCST0_DRRDY          (1 << 10) /* data receive ready (data in fifo)*/
+#define MMCST0_DATED          (1 << 11) /* DAT3 edge detect */
+#define MMCST0_TRNDNE         (1 << 12) /* transfer done */
 
 /* DAVINCI_MMCST1 definitions */
 #define MMCST1_BUSY           (1 << 0)
@@ -86,44 +86,44 @@
 #define SDIOIST_RWS           (1 << 1)
 
 /* MMCSD Init clock in Hz in opendrain mode */
-#define MMCSD_INIT_CLOCK		200000
+#define MMCSD_INIT_CLOCK        200000
 
-#define MAX_CCNT	((1 << 16) - 1)
+#define MAX_CCNT    ((1 << 16) - 1)
 
-#define MAX_NR_SG	16
+#define MAX_NR_SG   16
 
-#define MMC_DATA_WRITE	(1 << 8)
-#define MMC_DATA_READ	(1 << 9)
-#define MMC_DATA_STREAM	(1 << 10)
+#define MMC_DATA_WRITE  (1 << 8)
+#define MMC_DATA_READ   (1 << 9)
+#define MMC_DATA_STREAM (1 << 10)
 
 typedef struct {
-	volatile rt_uint32_t MMCCTL;
-	volatile rt_uint32_t MMCCLK;
-	volatile rt_uint32_t MMCST0;
-	volatile rt_uint32_t MMCST1;
-	volatile rt_uint32_t MMCIM;
-	volatile rt_uint32_t MMCTOR;
-	volatile rt_uint32_t MMCTOD;
-	volatile rt_uint32_t MMCBLEN;
-	volatile rt_uint32_t MMCNBLK;
-	volatile rt_uint32_t MMCNBLC;
-	volatile rt_uint32_t MMCDRR;
-	volatile rt_uint32_t MMCDXR;
-	volatile rt_uint32_t MMCCMD;
-	volatile rt_uint32_t MMCARGHL;
-	volatile rt_uint32_t MMCRSP01;
-	volatile rt_uint32_t MMCRSP23;
-	volatile rt_uint32_t MMCRSP45;
-	volatile rt_uint32_t MMCRSP67;
-	volatile rt_uint32_t MMCDRSP;
-	volatile rt_uint32_t reserved0;
-	volatile rt_uint32_t MMCCIDX;
-	volatile rt_uint32_t reserved1[4];
-	volatile rt_uint32_t SDIOCTL;
-	volatile rt_uint32_t SDIOST0;
-	volatile rt_uint32_t SDIOIEN;
-	volatile rt_uint32_t SDIOIST;
-	volatile rt_uint32_t MMCFIFOCTL;
+    volatile rt_uint32_t MMCCTL;
+    volatile rt_uint32_t MMCCLK;
+    volatile rt_uint32_t MMCST0;
+    volatile rt_uint32_t MMCST1;
+    volatile rt_uint32_t MMCIM;
+    volatile rt_uint32_t MMCTOR;
+    volatile rt_uint32_t MMCTOD;
+    volatile rt_uint32_t MMCBLEN;
+    volatile rt_uint32_t MMCNBLK;
+    volatile rt_uint32_t MMCNBLC;
+    volatile rt_uint32_t MMCDRR;
+    volatile rt_uint32_t MMCDXR;
+    volatile rt_uint32_t MMCCMD;
+    volatile rt_uint32_t MMCARGHL;
+    volatile rt_uint32_t MMCRSP01;
+    volatile rt_uint32_t MMCRSP23;
+    volatile rt_uint32_t MMCRSP45;
+    volatile rt_uint32_t MMCRSP67;
+    volatile rt_uint32_t MMCDRSP;
+    volatile rt_uint32_t reserved0;
+    volatile rt_uint32_t MMCCIDX;
+    volatile rt_uint32_t reserved1[4];
+    volatile rt_uint32_t SDIOCTL;
+    volatile rt_uint32_t SDIOST0;
+    volatile rt_uint32_t SDIOIEN;
+    volatile rt_uint32_t SDIOIST;
+    volatile rt_uint32_t MMCFIFOCTL;
 }mmcsd_regs_t;
 
 extern int rt_hw_mmcsd_init(void);
diff --git a/bsp/dm365/drivers/spi-davinci.c b/bsp/dm365/drivers/spi-davinci.c
index 18425cdf72..35de558e14 100644
--- a/bsp/dm365/drivers/spi-davinci.c
+++ b/bsp/dm365/drivers/spi-davinci.c
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 #include <rthw.h>
@@ -20,13 +20,13 @@
 #define barrier() __asm__ __volatile__("": : :"memory")
 #define cpu_relax() barrier()
 
-#define SPI_DEBUG			0	
+#define SPI_DEBUG           0
 #if SPI_DEBUG
 #define spi_dbg(dev, fmt, ...) \
-	do { \
-		rt_kprintf("%s:", dev->parent.name); \
-		rt_kprintf(fmt, ##__VA_ARGS__); \
-	} while(0)
+    do { \
+        rt_kprintf("%s:", dev->parent.name); \
+        rt_kprintf(fmt, ##__VA_ARGS__); \
+    } while(0)
 #else
 #define spi_dbg(dev, fmt, ...)
 #endif
@@ -34,50 +34,50 @@
 #define SZ_64K 0x10000
 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
 
-#define SPI_NO_RESOURCE		((resource_size_t)-1)
+#define SPI_NO_RESOURCE     ((resource_size_t)-1)
 
-#define SPI_MAX_CHIPSELECT	2
+#define SPI_MAX_CHIPSELECT  2
 
-#define CS_DEFAULT	0xFF
+#define CS_DEFAULT  0xFF
 
 #define __iomem
-#define BIT(nr)			(1UL << (nr))
+#define BIT(nr)         (1UL << (nr))
 
-#define SPIFMT_PHASE_MASK	BIT(16)
-#define SPIFMT_POLARITY_MASK	BIT(17)
-#define SPIFMT_DISTIMER_MASK	BIT(18)
-#define SPIFMT_SHIFTDIR_MASK	BIT(20)
-#define SPIFMT_WAITENA_MASK	BIT(21)
-#define SPIFMT_PARITYENA_MASK	BIT(22)
-#define SPIFMT_ODD_PARITY_MASK	BIT(23)
-#define SPIFMT_WDELAY_MASK	0x3f000000u
-#define SPIFMT_WDELAY_SHIFT	24
-#define SPIFMT_PRESCALE_SHIFT	8
+#define SPIFMT_PHASE_MASK   BIT(16)
+#define SPIFMT_POLARITY_MASK    BIT(17)
+#define SPIFMT_DISTIMER_MASK    BIT(18)
+#define SPIFMT_SHIFTDIR_MASK    BIT(20)
+#define SPIFMT_WAITENA_MASK BIT(21)
+#define SPIFMT_PARITYENA_MASK   BIT(22)
+#define SPIFMT_ODD_PARITY_MASK  BIT(23)
+#define SPIFMT_WDELAY_MASK  0x3f000000u
+#define SPIFMT_WDELAY_SHIFT 24
+#define SPIFMT_PRESCALE_SHIFT   8
 
 /* SPIPC0 */
-#define SPIPC0_DIFUN_MASK	BIT(11)		/* MISO */
-#define SPIPC0_DOFUN_MASK	BIT(10)		/* MOSI */
-#define SPIPC0_CLKFUN_MASK	BIT(9)		/* CLK */
-#define SPIPC0_SPIENA_MASK	BIT(8)		/* nREADY */
+#define SPIPC0_DIFUN_MASK   BIT(11)     /* MISO */
+#define SPIPC0_DOFUN_MASK   BIT(10)     /* MOSI */
+#define SPIPC0_CLKFUN_MASK  BIT(9)      /* CLK */
+#define SPIPC0_SPIENA_MASK  BIT(8)      /* nREADY */
 
-#define SPIINT_MASKALL		0x0101035F
-#define SPIINT_MASKINT		0x0000015F
-#define SPI_INTLVL_1		0x000001FF
-#define SPI_INTLVL_0		0x00000000
+#define SPIINT_MASKALL      0x0101035F
+#define SPIINT_MASKINT      0x0000015F
+#define SPI_INTLVL_1        0x000001FF
+#define SPI_INTLVL_0        0x00000000
 
 /* SPIDAT1 (upper 16 bit defines) */
-#define SPIDAT1_CSHOLD_MASK	BIT(12)
+#define SPIDAT1_CSHOLD_MASK BIT(12)
 
 /* SPIGCR1 */
-#define SPIGCR1_CLKMOD_MASK	BIT(1)
+#define SPIGCR1_CLKMOD_MASK BIT(1)
 #define SPIGCR1_MASTER_MASK     BIT(0)
-#define SPIGCR1_POWERDOWN_MASK	BIT(8)
-#define SPIGCR1_LOOPBACK_MASK	BIT(16)
-#define SPIGCR1_SPIENA_MASK	BIT(24)
+#define SPIGCR1_POWERDOWN_MASK  BIT(8)
+#define SPIGCR1_LOOPBACK_MASK   BIT(16)
+#define SPIGCR1_SPIENA_MASK BIT(24)
 
 /* SPIBUF */
-#define SPIBUF_TXFULL_MASK	BIT(29)
-#define SPIBUF_RXEMPTY_MASK	BIT(31)
+#define SPIBUF_TXFULL_MASK  BIT(29)
+#define SPIBUF_RXEMPTY_MASK BIT(31)
 
 /* SPIDELAY */
 #define SPIDELAY_C2TDELAY_SHIFT 24
@@ -90,67 +90,67 @@
 #define SPIDELAY_C2EDELAY_MASK  0xFF
 
 /* Error Masks */
-#define SPIFLG_DLEN_ERR_MASK		BIT(0)
-#define SPIFLG_TIMEOUT_MASK		BIT(1)
-#define SPIFLG_PARERR_MASK		BIT(2)
-#define SPIFLG_DESYNC_MASK		BIT(3)
-#define SPIFLG_BITERR_MASK		BIT(4)
-#define SPIFLG_OVRRUN_MASK		BIT(6)
-#define SPIFLG_BUF_INIT_ACTIVE_MASK	BIT(24)
-#define SPIFLG_ERROR_MASK		(SPIFLG_DLEN_ERR_MASK \
-				| SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
-				| SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
-				| SPIFLG_OVRRUN_MASK)
+#define SPIFLG_DLEN_ERR_MASK        BIT(0)
+#define SPIFLG_TIMEOUT_MASK     BIT(1)
+#define SPIFLG_PARERR_MASK      BIT(2)
+#define SPIFLG_DESYNC_MASK      BIT(3)
+#define SPIFLG_BITERR_MASK      BIT(4)
+#define SPIFLG_OVRRUN_MASK      BIT(6)
+#define SPIFLG_BUF_INIT_ACTIVE_MASK BIT(24)
+#define SPIFLG_ERROR_MASK       (SPIFLG_DLEN_ERR_MASK \
+                | SPIFLG_TIMEOUT_MASK | SPIFLG_PARERR_MASK \
+                | SPIFLG_DESYNC_MASK | SPIFLG_BITERR_MASK \
+                | SPIFLG_OVRRUN_MASK)
 
-#define SPIINT_DMA_REQ_EN	BIT(16)
+#define SPIINT_DMA_REQ_EN   BIT(16)
 
 /* SPI Controller registers */
-#define SPIGCR0		0x00
-#define SPIGCR1		0x04
-#define SPIINT		0x08
-#define SPILVL		0x0c
-#define SPIFLG		0x10
-#define SPIPC0		0x14
-#define SPIDAT1		0x3c
-#define SPIBUF		0x40
-#define SPIDELAY	0x48
-#define SPIDEF		0x4c
-#define SPIFMT0		0x50
+#define SPIGCR0     0x00
+#define SPIGCR1     0x04
+#define SPIINT      0x08
+#define SPILVL      0x0c
+#define SPIFLG      0x10
+#define SPIPC0      0x14
+#define SPIDAT1     0x3c
+#define SPIBUF      0x40
+#define SPIDELAY    0x48
+#define SPIDEF      0x4c
+#define SPIFMT0     0x50
 
 /* We have 2 DMA channels per CS, one for RX and one for TX */
 struct davinci_spi_dma {
-	int			tx_channel;
-	int			rx_channel;
-	int			dummy_param_slot;
-	enum dma_event_q	eventq;
+    int         tx_channel;
+    int         rx_channel;
+    int         dummy_param_slot;
+    enum dma_event_q    eventq;
 };
 
 /* SPI Controller driver's private data. */
 struct davinci_spi {
-	struct rt_spi_bus parent;
-	struct clk		*clk;
+    struct rt_spi_bus parent;
+    struct clk      *clk;
 
-	u8			version;
-	void __iomem		*base;
-	u32			irq;
-	struct rt_completion	done;
+    u8          version;
+    void __iomem        *base;
+    u32         irq;
+    struct rt_completion    done;
 
-	const void		*tx;
-	void			*rx;
+    const void      *tx;
+    void            *rx;
 #define SMP_CACHE_BYTES 32
-#define SPI_TMP_BUFSZ	(SMP_CACHE_BYTES + 1)
-	u8			rx_tmp_buf[SPI_TMP_BUFSZ];
-	int			rcount;
-	int			wcount;
-	struct davinci_spi_dma	dma;
+#define SPI_TMP_BUFSZ   (SMP_CACHE_BYTES + 1)
+    u8          rx_tmp_buf[SPI_TMP_BUFSZ];
+    int         rcount;
+    int         wcount;
+    struct davinci_spi_dma  dma;
 
-	void			(*get_rx)(u32 rx_data, struct davinci_spi *);
-	u32			(*get_tx)(struct davinci_spi *);
+    void            (*get_rx)(u32 rx_data, struct davinci_spi *);
+    u32         (*get_tx)(struct davinci_spi *);
 
-	u8			bytes_per_word[SPI_MAX_CHIPSELECT];
-	u8			chip_sel[SPI_MAX_CHIPSELECT];
-	struct davinci_spi_config *controller_data;
-	int			cshold_bug;
+    u8          bytes_per_word[SPI_MAX_CHIPSELECT];
+    u8          chip_sel[SPI_MAX_CHIPSELECT];
+    struct davinci_spi_config *controller_data;
+    int         cshold_bug;
 };
 
 static struct davinci_spi_config davinci_spi_default_cfg;
@@ -160,58 +160,58 @@ extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size);
 
 static void davinci_spi_rx_buf_u8(u32 data, struct davinci_spi *dspi)
 {
-	if (dspi->rx) {
-		u8 *rx = dspi->rx;
-		*rx++ = (u8)data;
-		dspi->rx = rx;
-	}
+    if (dspi->rx) {
+        u8 *rx = dspi->rx;
+        *rx++ = (u8)data;
+        dspi->rx = rx;
+    }
 }
 
 static void davinci_spi_rx_buf_u16(u32 data, struct davinci_spi *dspi)
 {
-	if (dspi->rx) {
-		u16 *rx = dspi->rx;
-		*rx++ = (u16)data;
-		dspi->rx = rx;
-	}
+    if (dspi->rx) {
+        u16 *rx = dspi->rx;
+        *rx++ = (u16)data;
+        dspi->rx = rx;
+    }
 }
 
 static u32 davinci_spi_tx_buf_u8(struct davinci_spi *dspi)
 {
-	u32 data = 0;
-	if (dspi->tx) {
-		const u8 *tx = dspi->tx;
-		data = *tx++;
-		dspi->tx = tx;
-	}
-	return data;
+    u32 data = 0;
+    if (dspi->tx) {
+        const u8 *tx = dspi->tx;
+        data = *tx++;
+        dspi->tx = tx;
+    }
+    return data;
 }
 
 static u32 davinci_spi_tx_buf_u16(struct davinci_spi *dspi)
 {
-	u32 data = 0;
-	if (dspi->tx) {
-		const u16 *tx = dspi->tx;
-		data = *tx++;
-		dspi->tx = tx;
-	}
-	return data;
+    u32 data = 0;
+    if (dspi->tx) {
+        const u16 *tx = dspi->tx;
+        data = *tx++;
+        dspi->tx = tx;
+    }
+    return data;
 }
 
 static inline void set_io_bits(void __iomem *addr, u32 bits)
 {
-	u32 v = readl(addr);
+    u32 v = readl(addr);
 
-	v |= bits;
-	writel(v, addr);
+    v |= bits;
+    writel(v, addr);
 }
 
 static inline void clear_io_bits(void __iomem *addr, u32 bits)
 {
-	u32 v = readl(addr);
+    u32 v = readl(addr);
 
-	v &= ~bits;
-	writel(v, addr);
+    v &= ~bits;
+    writel(v, addr);
 }
 
 /*
@@ -219,39 +219,39 @@ static inline void clear_io_bits(void __iomem *addr, u32 bits)
  */
 static void davinci_spi_chipselect(struct rt_spi_device *spi, int value)
 {
-	struct davinci_spi *dspi;
-	u8 chip_sel = (u8)spi->parent.user_data;
-	u16 spidat1 = CS_DEFAULT;
-	bool gpio_chipsel = RT_FALSE;
+    struct davinci_spi *dspi;
+    u8 chip_sel = (u8)spi->parent.user_data;
+    u16 spidat1 = CS_DEFAULT;
+    bool gpio_chipsel = RT_FALSE;
 
-	dspi = spi->bus->parent.user_data;
+    dspi = spi->bus->parent.user_data;
 
-	if (chip_sel < SPI_MAX_CHIPSELECT &&
-				dspi->chip_sel[chip_sel] != SPI_INTERN_CS)
-		gpio_chipsel = RT_TRUE;
+    if (chip_sel < SPI_MAX_CHIPSELECT &&
+                dspi->chip_sel[chip_sel] != SPI_INTERN_CS)
+        gpio_chipsel = RT_TRUE;
 
-	/*
-	 * Board specific chip select logic decides the polarity and cs
-	 * line for the controller
-	 */
-	if (gpio_chipsel) {
-		if (value == 0)
-			gpio_set_value(dspi->chip_sel[chip_sel], 0);
-		else
-			gpio_set_value(dspi->chip_sel[chip_sel], 1);
-	} else {
-		spidat1 = readw(dspi->base + SPIDAT1 + 2);
-		if (value == 0) {
-			spidat1 |= SPIDAT1_CSHOLD_MASK;
-			spidat1 &= ~(0x1 << chip_sel);
-		} else {
-			spidat1 &= ~SPIDAT1_CSHOLD_MASK;
-			spidat1 |= 0x03;
-		}
-		rt_kprintf("0x%04x\n", spidat1);
+    /*
+     * Board specific chip select logic decides the polarity and cs
+     * line for the controller
+     */
+    if (gpio_chipsel) {
+        if (value == 0)
+            gpio_set_value(dspi->chip_sel[chip_sel], 0);
+        else
+            gpio_set_value(dspi->chip_sel[chip_sel], 1);
+    } else {
+        spidat1 = readw(dspi->base + SPIDAT1 + 2);
+        if (value == 0) {
+            spidat1 |= SPIDAT1_CSHOLD_MASK;
+            spidat1 &= ~(0x1 << chip_sel);
+        } else {
+            spidat1 &= ~SPIDAT1_CSHOLD_MASK;
+            spidat1 |= 0x03;
+        }
+        rt_kprintf("0x%04x\n", spidat1);
 
-		writew(spidat1, dspi->base + SPIDAT1 + 2);
-	}
+        writew(spidat1, dspi->base + SPIDAT1 + 2);
+    }
 }
 
 /**
@@ -265,25 +265,25 @@ static void davinci_spi_chipselect(struct rt_spi_device *spi, int value)
  * or negative error number if valid prescalar cannot be updated.
  */
 static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
-							u32 max_speed_hz)
+                            u32 max_speed_hz)
 {
-	int ret;
+    int ret;
 
-	ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
+    ret = DIV_ROUND_UP(clk_get_rate(dspi->clk), max_speed_hz);
 
-	if (ret < 3) {
-		rt_kprintf("spi clock freq too high\n");
-		ret = 3;
-	}
-	if (ret > 256) {
-		rt_kprintf("spi clock freq too litter\n");
-		ret = 256;
-	}
+    if (ret < 3) {
+        rt_kprintf("spi clock freq too high\n");
+        ret = 3;
+    }
+    if (ret > 256) {
+        rt_kprintf("spi clock freq too litter\n");
+        ret = 256;
+    }
 
-	/*if (ret < 3 || ret > 256)
-		return -RT_ERROR;*/
+    /*if (ret < 3 || ret > 256)
+        return -RT_ERROR;*/
 
-	return ret - 1;
+    return ret - 1;
 }
 
 /**
@@ -296,104 +296,104 @@ static inline int davinci_spi_get_prescale(struct davinci_spi *dspi,
  * SPI slave device freq.
  */
 static int davinci_spi_setup_transfer(struct rt_spi_device *spi,
-		struct rt_spi_configuration *cfg)
+        struct rt_spi_configuration *cfg)
 {
 
-	struct davinci_spi *dspi;
-	struct davinci_spi_config *spicfg;
-	u8 bits_per_word = 0;
-	u32 hz = 0, spifmt = 0, prescale = 0;
-	u8 chip_select = (u8)spi->parent.user_data;
+    struct davinci_spi *dspi;
+    struct davinci_spi_config *spicfg;
+    u8 bits_per_word = 0;
+    u32 hz = 0, spifmt = 0, prescale = 0;
+    u8 chip_select = (u8)spi->parent.user_data;
 
-	dspi = spi->bus->parent.user_data;
-	spicfg = (struct davinci_spi_config *)dspi->controller_data;
-	if (!spicfg)
-		spicfg = &davinci_spi_default_cfg;
+    dspi = spi->bus->parent.user_data;
+    spicfg = (struct davinci_spi_config *)dspi->controller_data;
+    if (!spicfg)
+        spicfg = &davinci_spi_default_cfg;
 
-	bits_per_word = cfg->data_width;
-	hz = cfg->max_hz;
+    bits_per_word = cfg->data_width;
+    hz = cfg->max_hz;
 
-	/*
-	 * Assign function pointer to appropriate transfer method
-	 * 8bit, 16bit or 32bit transfer
-	 */
-	if (bits_per_word <= 8 && bits_per_word >= 2) {
-		dspi->get_rx = davinci_spi_rx_buf_u8;
-		dspi->get_tx = davinci_spi_tx_buf_u8;
-		dspi->bytes_per_word[chip_select] = 1;
-	} else if (bits_per_word <= 16 && bits_per_word >= 2) {
-		dspi->get_rx = davinci_spi_rx_buf_u16;
-		dspi->get_tx = davinci_spi_tx_buf_u16;
-		dspi->bytes_per_word[chip_select] = 2;
-	} else
-		return -RT_ERROR;
+    /*
+     * Assign function pointer to appropriate transfer method
+     * 8bit, 16bit or 32bit transfer
+     */
+    if (bits_per_word <= 8 && bits_per_word >= 2) {
+        dspi->get_rx = davinci_spi_rx_buf_u8;
+        dspi->get_tx = davinci_spi_tx_buf_u8;
+        dspi->bytes_per_word[chip_select] = 1;
+    } else if (bits_per_word <= 16 && bits_per_word >= 2) {
+        dspi->get_rx = davinci_spi_rx_buf_u16;
+        dspi->get_tx = davinci_spi_tx_buf_u16;
+        dspi->bytes_per_word[chip_select] = 2;
+    } else
+        return -RT_ERROR;
 
-	/* Set up SPIFMTn register, unique to this chipselect. */
+    /* Set up SPIFMTn register, unique to this chipselect. */
 
-	prescale = davinci_spi_get_prescale(dspi, hz);
-	if (prescale < 0)
-		return prescale;
+    prescale = davinci_spi_get_prescale(dspi, hz);
+    if (prescale < 0)
+        return prescale;
 
-	spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
+    spifmt = (prescale << SPIFMT_PRESCALE_SHIFT) | (bits_per_word & 0x1f);
 
-	if (!(cfg->mode & RT_SPI_MSB))
-		spifmt |= SPIFMT_SHIFTDIR_MASK;
+    if (!(cfg->mode & RT_SPI_MSB))
+        spifmt |= SPIFMT_SHIFTDIR_MASK;
 
-	if (cfg->mode & RT_SPI_CPOL)
-		spifmt |= SPIFMT_POLARITY_MASK;
+    if (cfg->mode & RT_SPI_CPOL)
+        spifmt |= SPIFMT_POLARITY_MASK;
 
-	if (!(cfg->mode & RT_SPI_CPHA))
-		spifmt |= SPIFMT_PHASE_MASK;
+    if (!(cfg->mode & RT_SPI_CPHA))
+        spifmt |= SPIFMT_PHASE_MASK;
 
-	/*
-	 * Version 1 hardware supports two basic SPI modes:
-	 *  - Standard SPI mode uses 4 pins, with chipselect
-	 *  - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
-	 *	(distinct from SPI_3WIRE, with just one data wire;
-	 *	or similar variants without MOSI or without MISO)
-	 *
-	 * Version 2 hardware supports an optional handshaking signal,
-	 * so it can support two more modes:
-	 *  - 5 pin SPI variant is standard SPI plus SPI_READY
-	 *  - 4 pin with enable is (SPI_READY | SPI_NO_CS)
-	 */
+    /*
+     * Version 1 hardware supports two basic SPI modes:
+     *  - Standard SPI mode uses 4 pins, with chipselect
+     *  - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS)
+     *  (distinct from SPI_3WIRE, with just one data wire;
+     *  or similar variants without MOSI or without MISO)
+     *
+     * Version 2 hardware supports an optional handshaking signal,
+     * so it can support two more modes:
+     *  - 5 pin SPI variant is standard SPI plus SPI_READY
+     *  - 4 pin with enable is (SPI_READY | SPI_NO_CS)
+     */
 
-	if (dspi->version == SPI_VERSION_2) {
+    if (dspi->version == SPI_VERSION_2) {
 
-		u32 delay = 0;
+        u32 delay = 0;
 
-		spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
-							& SPIFMT_WDELAY_MASK);
+        spifmt |= ((spicfg->wdelay << SPIFMT_WDELAY_SHIFT)
+                            & SPIFMT_WDELAY_MASK);
 
-		if (spicfg->odd_parity)
-			spifmt |= SPIFMT_ODD_PARITY_MASK;
+        if (spicfg->odd_parity)
+            spifmt |= SPIFMT_ODD_PARITY_MASK;
 
-		if (spicfg->parity_enable)
-			spifmt |= SPIFMT_PARITYENA_MASK;
+        if (spicfg->parity_enable)
+            spifmt |= SPIFMT_PARITYENA_MASK;
 
-		if (spicfg->timer_disable) {
-			spifmt |= SPIFMT_DISTIMER_MASK;
-		} else {
-			delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
-						& SPIDELAY_C2TDELAY_MASK;
-			delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
-						& SPIDELAY_T2CDELAY_MASK;
-		}
+        if (spicfg->timer_disable) {
+            spifmt |= SPIFMT_DISTIMER_MASK;
+        } else {
+            delay |= (spicfg->c2tdelay << SPIDELAY_C2TDELAY_SHIFT)
+                        & SPIDELAY_C2TDELAY_MASK;
+            delay |= (spicfg->t2cdelay << SPIDELAY_T2CDELAY_SHIFT)
+                        & SPIDELAY_T2CDELAY_MASK;
+        }
 
-		if (cfg->mode & RT_SPI_READY) {
-			spifmt |= SPIFMT_WAITENA_MASK;
-			delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
-						& SPIDELAY_T2EDELAY_MASK;
-			delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
-						& SPIDELAY_C2EDELAY_MASK;
-		}
+        if (cfg->mode & RT_SPI_READY) {
+            spifmt |= SPIFMT_WAITENA_MASK;
+            delay |= (spicfg->t2edelay << SPIDELAY_T2EDELAY_SHIFT)
+                        & SPIDELAY_T2EDELAY_MASK;
+            delay |= (spicfg->c2edelay << SPIDELAY_C2EDELAY_SHIFT)
+                        & SPIDELAY_C2EDELAY_MASK;
+        }
 
-		writel(delay, dspi->base + SPIDELAY);
-	}
+        writel(delay, dspi->base + SPIDELAY);
+    }
 
-	writel(spifmt, dspi->base + SPIFMT0);
+    writel(spifmt, dspi->base + SPIFMT0);
 
-	return 0;
+    return 0;
 }
 
 #if 0
@@ -405,73 +405,73 @@ static int davinci_spi_setup_transfer(struct rt_spi_device *spi,
  */
 static int davinci_spi_setup(struct spi_device *spi)
 {
-	int retval = 0;
-	struct davinci_spi *dspi;
-	struct davinci_spi_platform_data *pdata;
+    int retval = 0;
+    struct davinci_spi *dspi;
+    struct davinci_spi_platform_data *pdata;
 
-	dspi = spi_master_get_devdata(spi->master);
-	pdata = dspi->pdata;
+    dspi = spi_master_get_devdata(spi->master);
+    pdata = dspi->pdata;
 
-	/* if bits per word length is zero then set it default 8 */
-	if (!spi->bits_per_word)
-		spi->bits_per_word = 8;
+    /* if bits per word length is zero then set it default 8 */
+    if (!spi->bits_per_word)
+        spi->bits_per_word = 8;
 
-	if (!(spi->mode & SPI_NO_CS)) {
-		if ((pdata->chip_sel == NULL) ||
-		    (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
-			set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
+    if (!(spi->mode & SPI_NO_CS)) {
+        if ((pdata->chip_sel == NULL) ||
+            (pdata->chip_sel[spi->chip_select] == SPI_INTERN_CS))
+            set_io_bits(dspi->base + SPIPC0, 1 << spi->chip_select);
 
-	}
+    }
 
-	if (spi->mode & SPI_READY)
-		set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
+    if (spi->mode & SPI_READY)
+        set_io_bits(dspi->base + SPIPC0, SPIPC0_SPIENA_MASK);
 
-	if (spi->mode & SPI_LOOP)
-		set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
-	else
-		clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
+    if (spi->mode & SPI_LOOP)
+        set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
+    else
+        clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);
 
-	return retval;
+    return retval;
 }
 #endif
 
 static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
 {
-	struct rt_device *sdev = &dspi->parent.parent;
+    struct rt_device *sdev = &dspi->parent.parent;
 
-	if (int_status & SPIFLG_TIMEOUT_MASK) {
-		spi_dbg(sdev, "SPI Time-out Error\n");
-		return -RT_ETIMEOUT;
-	}
-	if (int_status & SPIFLG_DESYNC_MASK) {
-		spi_dbg(sdev, "SPI Desynchronization Error\n");
-		return -RT_EIO;
-	}
-	if (int_status & SPIFLG_BITERR_MASK) {
-		spi_dbg(sdev, "SPI Bit error\n");
-		return -RT_EIO;
-	}
+    if (int_status & SPIFLG_TIMEOUT_MASK) {
+        spi_dbg(sdev, "SPI Time-out Error\n");
+        return -RT_ETIMEOUT;
+    }
+    if (int_status & SPIFLG_DESYNC_MASK) {
+        spi_dbg(sdev, "SPI Desynchronization Error\n");
+        return -RT_EIO;
+    }
+    if (int_status & SPIFLG_BITERR_MASK) {
+        spi_dbg(sdev, "SPI Bit error\n");
+        return -RT_EIO;
+    }
 
-	if (dspi->version == SPI_VERSION_2) {
-		if (int_status & SPIFLG_DLEN_ERR_MASK) {
-			spi_dbg(sdev, "SPI Data Length Error\n");
-			return -RT_EIO;
-		}
-		if (int_status & SPIFLG_PARERR_MASK) {
-			spi_dbg(sdev, "SPI Parity Error\n");
-			return -RT_EIO;
-		}
-		if (int_status & SPIFLG_OVRRUN_MASK) {
-			spi_dbg(sdev, "SPI Data Overrun error\n");
-			return -RT_EIO;
-		}
-		if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
-			spi_dbg(sdev, "SPI Buffer Init Active\n");
-			return -RT_EBUSY;
-		}
-	}
+    if (dspi->version == SPI_VERSION_2) {
+        if (int_status & SPIFLG_DLEN_ERR_MASK) {
+            spi_dbg(sdev, "SPI Data Length Error\n");
+            return -RT_EIO;
+        }
+        if (int_status & SPIFLG_PARERR_MASK) {
+            spi_dbg(sdev, "SPI Parity Error\n");
+            return -RT_EIO;
+        }
+        if (int_status & SPIFLG_OVRRUN_MASK) {
+            spi_dbg(sdev, "SPI Data Overrun error\n");
+            return -RT_EIO;
+        }
+        if (int_status & SPIFLG_BUF_INIT_ACTIVE_MASK) {
+            spi_dbg(sdev, "SPI Buffer Init Active\n");
+            return -RT_EBUSY;
+        }
+    }
 
-	return 0;
+    return 0;
 }
 
 /**
@@ -483,50 +483,50 @@ static int davinci_spi_check_error(struct davinci_spi *dspi, int int_status)
  */
 static int davinci_spi_process_events(struct davinci_spi *dspi)
 {
-	u32 buf, status, errors = 0, spidat1;
+    u32 buf, status, errors = 0, spidat1;
 
-	buf = readl(dspi->base + SPIBUF);
+    buf = readl(dspi->base + SPIBUF);
 
-	if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
-		dspi->get_rx(buf & 0xFFFF, dspi);
-		dspi->rcount--;
-	}
+    if (dspi->rcount > 0 && !(buf & SPIBUF_RXEMPTY_MASK)) {
+        dspi->get_rx(buf & 0xFFFF, dspi);
+        dspi->rcount--;
+    }
 
-	status = readl(dspi->base + SPIFLG);
+    status = readl(dspi->base + SPIFLG);
 
-	if (unlikely(status & SPIFLG_ERROR_MASK)) {
-		errors = status & SPIFLG_ERROR_MASK;
-		goto out;
-	}
+    if (unlikely(status & SPIFLG_ERROR_MASK)) {
+        errors = status & SPIFLG_ERROR_MASK;
+        goto out;
+    }
 
-	if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
-		spidat1 = readl(dspi->base + SPIDAT1);
-		dspi->wcount--;
-		spidat1 &= ~0xFFFF;
-		spidat1 |= 0xFFFF & dspi->get_tx(dspi);
-		writel(spidat1, dspi->base + SPIDAT1);
-	}
+    if (dspi->wcount > 0 && !(buf & SPIBUF_TXFULL_MASK)) {
+        spidat1 = readl(dspi->base + SPIDAT1);
+        dspi->wcount--;
+        spidat1 &= ~0xFFFF;
+        spidat1 |= 0xFFFF & dspi->get_tx(dspi);
+        writel(spidat1, dspi->base + SPIDAT1);
+    }
 
 out:
-	return errors;
+    return errors;
 }
 
 static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
 {
-	struct davinci_spi *dspi = data;
-	struct davinci_spi_dma *dma = &dspi->dma;
+    struct davinci_spi *dspi = data;
+    struct davinci_spi_dma *dma = &dspi->dma;
 
-	edma_stop(lch);
+    edma_stop(lch);
 
-	if (status == DMA_COMPLETE) {
-		if (lch == dma->rx_channel)
-			dspi->rcount = 0;
-		if (lch == dma->tx_channel)
-			dspi->wcount = 0;
-	}
+    if (status == DMA_COMPLETE) {
+        if (lch == dma->rx_channel)
+            dspi->rcount = 0;
+        if (lch == dma->tx_channel)
+            dspi->wcount = 0;
+    }
 
-	if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE))
-		rt_completion_done(&dspi->done);
+    if ((!dspi->wcount && !dspi->rcount) || (status != DMA_COMPLETE))
+        rt_completion_done(&dspi->done);
 }
 
 /**
@@ -540,186 +540,186 @@ static void davinci_spi_dma_callback(unsigned lch, u16 status, void *data)
  */
 static int davinci_spi_bufs(struct rt_spi_device *spi, struct rt_spi_message *msg)
 {
-	struct davinci_spi *dspi;
-	int data_type, ret;
-	u32 tx_data, spidat1;
-	u32 errors = 0;
-	struct davinci_spi_config *spicfg;
-	unsigned rx_buf_count;
-	struct rt_device *sdev;
-	u8 chip_select = (u8)spi->parent.user_data;
+    struct davinci_spi *dspi;
+    int data_type, ret;
+    u32 tx_data, spidat1;
+    u32 errors = 0;
+    struct davinci_spi_config *spicfg;
+    unsigned rx_buf_count;
+    struct rt_device *sdev;
+    u8 chip_select = (u8)spi->parent.user_data;
 
-	dspi = spi->bus->parent.user_data;
-	spicfg = (struct davinci_spi_config *)dspi->controller_data;
-	if (!spicfg)
-		spicfg = &davinci_spi_default_cfg;
-	sdev = &dspi->parent.parent;
+    dspi = spi->bus->parent.user_data;
+    spicfg = (struct davinci_spi_config *)dspi->controller_data;
+    if (!spicfg)
+        spicfg = &davinci_spi_default_cfg;
+    sdev = &dspi->parent.parent;
 
-	/* convert len to words based on bits_per_word */
-	data_type = dspi->bytes_per_word[chip_select];
+    /* convert len to words based on bits_per_word */
+    data_type = dspi->bytes_per_word[chip_select];
 
-	dspi->tx = msg->send_buf;
-	dspi->rx = msg->recv_buf;
-	dspi->wcount = msg->length / data_type;
-	dspi->rcount = dspi->wcount;
+    dspi->tx = msg->send_buf;
+    dspi->rx = msg->recv_buf;
+    dspi->wcount = msg->length / data_type;
+    dspi->rcount = dspi->wcount;
 
-	spidat1 = readl(dspi->base + SPIDAT1);
+    spidat1 = readl(dspi->base + SPIDAT1);
 
-	clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
-	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
+    clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
+    set_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
 
-	rt_completion_init(&(dspi->done));
+    rt_completion_init(&(dspi->done));
 
-	if (msg->cs_take)
-		davinci_spi_chipselect(spi, 0);
+    if (msg->cs_take)
+        davinci_spi_chipselect(spi, 0);
 
-	if (spicfg->io_type == SPI_IO_TYPE_INTR)
-		set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
+    if (spicfg->io_type == SPI_IO_TYPE_INTR)
+        set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
 
-	if (msg->length > 0) {
-		if (spicfg->io_type != SPI_IO_TYPE_DMA) {
-			/* start the transfer */
-			dspi->wcount--;
-			tx_data = dspi->get_tx(dspi);
-			spidat1 &= 0xFFFF0000;
-			spidat1 |= tx_data & 0xFFFF;
-			writel(spidat1, dspi->base + SPIDAT1);
-		} else {
-			struct davinci_spi_dma *dma;
-			unsigned long tx_reg, rx_reg;
-			struct edmacc_param param;
-			void *rx_buf;
-			int b, c;
+    if (msg->length > 0) {
+        if (spicfg->io_type != SPI_IO_TYPE_DMA) {
+            /* start the transfer */
+            dspi->wcount--;
+            tx_data = dspi->get_tx(dspi);
+            spidat1 &= 0xFFFF0000;
+            spidat1 |= tx_data & 0xFFFF;
+            writel(spidat1, dspi->base + SPIDAT1);
+        } else {
+            struct davinci_spi_dma *dma;
+            unsigned long tx_reg, rx_reg;
+            struct edmacc_param param;
+            void *rx_buf;
+            int b, c;
 
-			dma = &dspi->dma;
+            dma = &dspi->dma;
 
-			tx_reg = (unsigned long)dspi->base + SPIDAT1;
-			rx_reg = (unsigned long)dspi->base + SPIBUF;
+            tx_reg = (unsigned long)dspi->base + SPIDAT1;
+            rx_reg = (unsigned long)dspi->base + SPIBUF;
 
-			/*
-			 * Transmit DMA setup
-			 *
-			 * If there is transmit data, map the transmit buffer, set it
-			 * as the source of data and set the source B index to data
-			 * size. If there is no transmit data, set the transmit register
-			 * as the source of data, and set the source B index to zero.
-			 *
-			 * The destination is always the transmit register itself. And
-			 * the destination never increments.
-			 */
+            /*
+             * Transmit DMA setup
+             *
+             * If there is transmit data, map the transmit buffer, set it
+             * as the source of data and set the source B index to data
+             * size. If there is no transmit data, set the transmit register
+             * as the source of data, and set the source B index to zero.
+             *
+             * The destination is always the transmit register itself. And
+             * the destination never increments.
+             */
 
-			if (msg->send_buf) {
-				mmu_clean_dcache((rt_uint32_t)msg->send_buf, (rt_uint32_t)msg->length);
-			}
+            if (msg->send_buf) {
+                mmu_clean_dcache((rt_uint32_t)msg->send_buf, (rt_uint32_t)msg->length);
+            }
 
-			/*
-			 * If number of words is greater than 65535, then we need
-			 * to configure a 3 dimension transfer.  Use the BCNTRLD
-			 * feature to allow for transfers that aren't even multiples
-			 * of 65535 (or any other possible b size) by first transferring
-			 * the remainder amount then grabbing the next N blocks of
-			 * 65535 words.
-			 */
+            /*
+             * If number of words is greater than 65535, then we need
+             * to configure a 3 dimension transfer.  Use the BCNTRLD
+             * feature to allow for transfers that aren't even multiples
+             * of 65535 (or any other possible b size) by first transferring
+             * the remainder amount then grabbing the next N blocks of
+             * 65535 words.
+             */
 
-			c = dspi->wcount / (SZ_64K - 1);	/* N 65535 Blocks */
-			b = dspi->wcount - c * (SZ_64K - 1);	/* Remainder */
-			if (b)
-				c++;
-			else
-				b = SZ_64K - 1;
+            c = dspi->wcount / (SZ_64K - 1);    /* N 65535 Blocks */
+            b = dspi->wcount - c * (SZ_64K - 1);    /* Remainder */
+            if (b)
+                c++;
+            else
+                b = SZ_64K - 1;
 
-			param.opt = TCINTEN | EDMA_TCC(dma->tx_channel);
-			param.src = msg->send_buf ? msg->send_buf : tx_reg;
-			param.a_b_cnt = b << 16 | data_type;
-			param.dst = tx_reg;
-			param.src_dst_bidx = msg->send_buf ? data_type : 0;
-			param.link_bcntrld = 0xffffffff;
-			param.src_dst_cidx = msg->send_buf ? data_type : 0;
-			param.ccnt = c;
-			edma_write_slot(dma->tx_channel, &param);
-			edma_link(dma->tx_channel, dma->dummy_param_slot);
+            param.opt = TCINTEN | EDMA_TCC(dma->tx_channel);
+            param.src = msg->send_buf ? msg->send_buf : tx_reg;
+            param.a_b_cnt = b << 16 | data_type;
+            param.dst = tx_reg;
+            param.src_dst_bidx = msg->send_buf ? data_type : 0;
+            param.link_bcntrld = 0xffffffff;
+            param.src_dst_cidx = msg->send_buf ? data_type : 0;
+            param.ccnt = c;
+            edma_write_slot(dma->tx_channel, &param);
+            edma_link(dma->tx_channel, dma->dummy_param_slot);
 
-			/*
-			 * Receive DMA setup
-			 *
-			 * If there is receive buffer, use it to receive data. If there
-			 * is none provided, use a temporary receive buffer. Set the
-			 * destination B index to 0 so effectively only one byte is used
-			 * in the temporary buffer (address does not increment).
-			 *
-			 * The source of receive data is the receive data register. The
-			 * source address never increments.
-			 */
+            /*
+             * Receive DMA setup
+             *
+             * If there is receive buffer, use it to receive data. If there
+             * is none provided, use a temporary receive buffer. Set the
+             * destination B index to 0 so effectively only one byte is used
+             * in the temporary buffer (address does not increment).
+             *
+             * The source of receive data is the receive data register. The
+             * source address never increments.
+             */
 
-			if (msg->recv_buf) {
-				rx_buf = msg->recv_buf;
-				rx_buf_count = msg->length;
-			} else {
-				rx_buf = dspi->rx_tmp_buf;
-				rx_buf_count = sizeof(dspi->rx_tmp_buf);
-			}
+            if (msg->recv_buf) {
+                rx_buf = msg->recv_buf;
+                rx_buf_count = msg->length;
+            } else {
+                rx_buf = dspi->rx_tmp_buf;
+                rx_buf_count = sizeof(dspi->rx_tmp_buf);
+            }
 
-			mmu_invalidate_dcache((rt_uint32_t)rx_buf, (rt_uint32_t)rx_buf_count);
+            mmu_invalidate_dcache((rt_uint32_t)rx_buf, (rt_uint32_t)rx_buf_count);
 
-			param.opt = TCINTEN | EDMA_TCC(dma->rx_channel);
-			param.src = rx_reg;
-			param.a_b_cnt = b << 16 | data_type;
-			param.dst = rx_buf;
-			param.src_dst_bidx = (msg->recv_buf ? data_type : 0) << 16;
-			param.link_bcntrld = 0xffffffff;
-			param.src_dst_cidx = (msg->recv_buf ? data_type : 0) << 16;
-			param.ccnt = c;
-			edma_write_slot(dma->rx_channel, &param);
+            param.opt = TCINTEN | EDMA_TCC(dma->rx_channel);
+            param.src = rx_reg;
+            param.a_b_cnt = b << 16 | data_type;
+            param.dst = rx_buf;
+            param.src_dst_bidx = (msg->recv_buf ? data_type : 0) << 16;
+            param.link_bcntrld = 0xffffffff;
+            param.src_dst_cidx = (msg->recv_buf ? data_type : 0) << 16;
+            param.ccnt = c;
+            edma_write_slot(dma->rx_channel, &param);
 
-			if (dspi->cshold_bug)
-				writew(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
+            if (dspi->cshold_bug)
+                writew(spidat1 >> 16, dspi->base + SPIDAT1 + 2);
 
-			edma_start(dma->rx_channel);
-			edma_start(dma->tx_channel);
-			set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
-		}
+            edma_start(dma->rx_channel);
+            edma_start(dma->tx_channel);
+            set_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
+        }
 
-		/* Wait for the transfer to complete */
-		if (spicfg->io_type != SPI_IO_TYPE_POLL) {
-			rt_completion_wait(&(dspi->done), RT_WAITING_FOREVER);
-		} else {
-			while (dspi->rcount > 0 || dspi->wcount > 0) {
-				errors = davinci_spi_process_events(dspi);
-				if (errors)
-					break;
-				cpu_relax();
-			}
-		}
-	}
+        /* Wait for the transfer to complete */
+        if (spicfg->io_type != SPI_IO_TYPE_POLL) {
+            rt_completion_wait(&(dspi->done), RT_WAITING_FOREVER);
+        } else {
+            while (dspi->rcount > 0 || dspi->wcount > 0) {
+                errors = davinci_spi_process_events(dspi);
+                if (errors)
+                    break;
+                cpu_relax();
+            }
+        }
+    }
 
-	if (msg->cs_release)
-		davinci_spi_chipselect(spi, 1);
+    if (msg->cs_release)
+        davinci_spi_chipselect(spi, 1);
 
-	clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
-	if (spicfg->io_type == SPI_IO_TYPE_DMA) {
-		clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
-	}
+    clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
+    if (spicfg->io_type == SPI_IO_TYPE_DMA) {
+        clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
+    }
 
-	clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
-	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
+    clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
+    set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
 
-	/*
-	 * Check for bit error, desync error,parity error,timeout error and
-	 * receive overflow errors
-	 */
-	if (errors) {
-		ret = davinci_spi_check_error(dspi, errors);
-		rt_kprintf("%s: error reported but no error found!\n",
-							spi->bus->parent.parent.name);
-		return ret;
-	}
+    /*
+     * Check for bit error, desync error,parity error,timeout error and
+     * receive overflow errors
+     */
+    if (errors) {
+        ret = davinci_spi_check_error(dspi, errors);
+        rt_kprintf("%s: error reported but no error found!\n",
+                            spi->bus->parent.parent.name);
+        return ret;
+    }
 
-	if (dspi->rcount != 0 || dspi->wcount != 0) {
-		spi_dbg(sdev, "SPI data transfer error\n");
-		return -RT_EIO;
-	}
+    if (dspi->rcount != 0 || dspi->wcount != 0) {
+        spi_dbg(sdev, "SPI data transfer error\n");
+        return -RT_EIO;
+    }
 
-	return msg->length;
+    return msg->length;
 }
 
 /**
@@ -735,65 +735,65 @@ static int davinci_spi_bufs(struct rt_spi_device *spi, struct rt_spi_message *ms
  */
 static void davinci_spi_irq(int irq, void *data)
 {
-	struct davinci_spi *dspi = data;
-	int status;
+    struct davinci_spi *dspi = data;
+    int status;
 
-	status = davinci_spi_process_events(dspi);
-	if (unlikely(status != 0))
-		clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
+    status = davinci_spi_process_events(dspi);
+    if (unlikely(status != 0))
+        clear_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
 
-	if ((!dspi->rcount && !dspi->wcount) || status)
-		rt_completion_done(&dspi->done);
+    if ((!dspi->rcount && !dspi->wcount) || status)
+        rt_completion_done(&dspi->done);
 }
 
 static int davinci_spi_request_dma(struct davinci_spi *dspi)
 {
-	int r;
-	struct davinci_spi_dma *dma = &dspi->dma;
+    int r;
+    struct davinci_spi_dma *dma = &dspi->dma;
 
-	r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi,
-								dma->eventq);
-	if (r < 0) {
-		rt_kprintf("Unable to request DMA channel for SPI RX\n");
-		r = -RT_EFULL;
-		goto rx_dma_failed;
-	}
+    r = edma_alloc_channel(dma->rx_channel, davinci_spi_dma_callback, dspi,
+                                dma->eventq);
+    if (r < 0) {
+        rt_kprintf("Unable to request DMA channel for SPI RX\n");
+        r = -RT_EFULL;
+        goto rx_dma_failed;
+    }
 
-	r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi,
-								dma->eventq);
-	if (r < 0) {
-		rt_kprintf("Unable to request DMA channel for SPI TX\n");
-		r = -RT_EFULL;
-		goto tx_dma_failed;
-	}
+    r = edma_alloc_channel(dma->tx_channel, davinci_spi_dma_callback, dspi,
+                                dma->eventq);
+    if (r < 0) {
+        rt_kprintf("Unable to request DMA channel for SPI TX\n");
+        r = -RT_EFULL;
+        goto tx_dma_failed;
+    }
 
-	r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY);
-	if (r < 0) {
-		rt_kprintf("Unable to request SPI TX DMA param slot\n");
-		r = -RT_EFULL;
-		goto param_failed;
-	}
-	dma->dummy_param_slot = r;
-	edma_link(dma->dummy_param_slot, dma->dummy_param_slot);
+    r = edma_alloc_slot(EDMA_CTLR(dma->tx_channel), EDMA_SLOT_ANY);
+    if (r < 0) {
+        rt_kprintf("Unable to request SPI TX DMA param slot\n");
+        r = -RT_EFULL;
+        goto param_failed;
+    }
+    dma->dummy_param_slot = r;
+    edma_link(dma->dummy_param_slot, dma->dummy_param_slot);
 
-	return 0;
+    return 0;
 param_failed:
-	edma_free_channel(dma->tx_channel);
+    edma_free_channel(dma->tx_channel);
 tx_dma_failed:
-	edma_free_channel(dma->rx_channel);
+    edma_free_channel(dma->rx_channel);
 rx_dma_failed:
-	return r;
+    return r;
 }
 
 static rt_err_t configure(struct rt_spi_device *device,
                           struct rt_spi_configuration *configuration)
 {
-	return davinci_spi_setup_transfer(device, configuration);
+    return davinci_spi_setup_transfer(device, configuration);
 }
 
 static rt_uint32_t xfer(struct rt_spi_device *device, struct rt_spi_message *message)
 {
-	return davinci_spi_bufs(device, message);
+    return davinci_spi_bufs(device, message);
 };
 
 
@@ -806,29 +806,29 @@ static struct rt_spi_ops davinci_spi_ops =
 
 static void udelay (volatile rt_uint32_t us)
 {
-	volatile rt_int32_t i;
-	for (; us > 0; us--)
-	{
-		i = 5000;
-		while(i > 0)
-		{
-			i--;
-		}
-	}
+    volatile rt_int32_t i;
+    for (; us > 0; us--)
+    {
+        i = 5000;
+        while(i > 0)
+        {
+            i--;
+        }
+    }
 }
 
 void spi_pin_cfg(void)
 {
-	rt_uint32_t val;
+    rt_uint32_t val;
 
-	val = davinci_readl(PINMUX3);
-	val |= 0x80000000; /* SPI1 */
-	davinci_writel(val, PINMUX3);
+    val = davinci_readl(PINMUX3);
+    val |= 0x80000000; /* SPI1 */
+    davinci_writel(val, PINMUX3);
 
-	val = davinci_readl(PINMUX4);
-	val &= 0xffffffc0; /* SPI1 */
-	val |= 0x05;//0x00000015; /* SPI1 */
-	davinci_writel(val, PINMUX4);
+    val = davinci_readl(PINMUX4);
+    val &= 0xffffffc0; /* SPI1 */
+    val |= 0x05;//0x00000015; /* SPI1 */
+    davinci_writel(val, PINMUX4);
 }
 
 /**
@@ -844,87 +844,87 @@ void spi_pin_cfg(void)
  */
 static int davinci_spi_probe(struct davinci_spi *dspi, char *spi_bus_name)
 {
-	int i = 0, ret = 0;
-	u32 spipc0;
+    int i = 0, ret = 0;
+    u32 spipc0;
 
-	spi_pin_cfg();
-	psc_change_state(DAVINCI_DM365_LPSC_SPI1, PSC_ENABLE);
+    spi_pin_cfg();
+    psc_change_state(DAVINCI_DM365_LPSC_SPI1, PSC_ENABLE);
 
-	dspi->base = DM3XX_SPI1_BASE;//spi;
+    dspi->base = DM3XX_SPI1_BASE;//spi;
 
-	dspi->irq = IRQ_DM3XX_SPINT1_0;
+    dspi->irq = IRQ_DM3XX_SPINT1_0;
 
-	rt_hw_interrupt_install(dspi->irq, davinci_spi_irq, dspi, spi_bus_name);
-	rt_hw_interrupt_umask(dspi->irq);
+    rt_hw_interrupt_install(dspi->irq, davinci_spi_irq, dspi, spi_bus_name);
+    rt_hw_interrupt_umask(dspi->irq);
 
-	dspi->clk = clk_get("SPICLK");
+    dspi->clk = clk_get("SPICLK");
 
-	dspi->version = SPI_VERSION_1;
-	dspi->chip_sel[0] = 29;//SPI_INTERN_CS;
-	dspi->chip_sel[1] = 0;//GPIO0
+    dspi->version = SPI_VERSION_1;
+    dspi->chip_sel[0] = 29;//SPI_INTERN_CS;
+    dspi->chip_sel[1] = 0;//GPIO0
 
-	dspi->dma.rx_channel = 15;
-	dspi->dma.tx_channel = 14;
-	dspi->dma.eventq = EVENTQ_3;
+    dspi->dma.rx_channel = 15;
+    dspi->dma.tx_channel = 14;
+    dspi->dma.eventq = EVENTQ_3;
 
-	ret = davinci_spi_request_dma(dspi);
-	if (ret)
-		goto err;
+    ret = davinci_spi_request_dma(dspi);
+    if (ret)
+        goto err;
 
-	rt_kprintf("%s: DMA: supported\n", spi_bus_name);
-	rt_kprintf("%s: DMA: RX channel: %d, TX channel: %d, "
-			"event queue: %d\n", spi_bus_name, dspi->dma.rx_channel, 
-			dspi->dma.tx_channel, dspi->dma.eventq);
+    rt_kprintf("%s: DMA: supported\n", spi_bus_name);
+    rt_kprintf("%s: DMA: RX channel: %d, TX channel: %d, "
+            "event queue: %d\n", spi_bus_name, dspi->dma.rx_channel,
+            dspi->dma.tx_channel, dspi->dma.eventq);
 
-	dspi->get_rx = davinci_spi_rx_buf_u8;
-	dspi->get_tx = davinci_spi_tx_buf_u8;
+    dspi->get_rx = davinci_spi_rx_buf_u8;
+    dspi->get_tx = davinci_spi_tx_buf_u8;
 
-	rt_completion_init(&dspi->done);
+    rt_completion_init(&dspi->done);
 
-	/* Reset In/OUT SPI module */
-	writel(0, dspi->base + SPIGCR0);
-	udelay(100);
-	writel(1, dspi->base + SPIGCR0);
+    /* Reset In/OUT SPI module */
+    writel(0, dspi->base + SPIGCR0);
+    udelay(100);
+    writel(1, dspi->base + SPIGCR0);
 
-	/* Set up SPIPC0.  CS and ENA init is done in davinci_spi_setup */
-	spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
-	writel(spipc0, dspi->base + SPIPC0);
+    /* Set up SPIPC0.  CS and ENA init is done in davinci_spi_setup */
+    spipc0 = SPIPC0_DIFUN_MASK | SPIPC0_DOFUN_MASK | SPIPC0_CLKFUN_MASK;
+    writel(spipc0, dspi->base + SPIPC0);
 
-	/* initialize chip selects */
-	for (i = 0; i < SPI_MAX_CHIPSELECT; i++) {
-		if (dspi->chip_sel[i] != SPI_INTERN_CS)
-			gpio_direction_output(dspi->chip_sel[i], 1);
-	}
+    /* initialize chip selects */
+    for (i = 0; i < SPI_MAX_CHIPSELECT; i++) {
+        if (dspi->chip_sel[i] != SPI_INTERN_CS)
+            gpio_direction_output(dspi->chip_sel[i], 1);
+    }
 
-	if (0)
-		writel(SPI_INTLVL_1, dspi->base + SPILVL);
-	else
-		writel(SPI_INTLVL_0, dspi->base + SPILVL);
+    if (0)
+        writel(SPI_INTLVL_1, dspi->base + SPILVL);
+    else
+        writel(SPI_INTLVL_0, dspi->base + SPILVL);
 
-	writel(CS_DEFAULT, dspi->base + SPIDEF);
+    writel(CS_DEFAULT, dspi->base + SPIDEF);
 
-	/* master mode default */
-	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
-	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
-	set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
+    /* master mode default */
+    set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
+    set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
+    set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
 
-	//set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);//LOOP BACK mode
+    //set_io_bits(dspi->base + SPIGCR1, SPIGCR1_LOOPBACK_MASK);//LOOP BACK mode
 
-	rt_kprintf("%s: Controller at 0x%p\n", spi_bus_name, dspi->base);
+    rt_kprintf("%s: Controller at 0x%p\n", spi_bus_name, dspi->base);
 
-	dspi->parent.parent.user_data = dspi;
+    dspi->parent.parent.user_data = dspi;
 
-	return rt_spi_bus_register(&dspi->parent, spi_bus_name, &davinci_spi_ops);
+    return rt_spi_bus_register(&dspi->parent, spi_bus_name, &davinci_spi_ops);
 
-	return ret;
+    return ret;
 
 free_dma:
-	edma_free_channel(dspi->dma.tx_channel);
-	edma_free_channel(dspi->dma.rx_channel);
-	edma_free_slot(dspi->dma.dummy_param_slot);
+    edma_free_channel(dspi->dma.tx_channel);
+    edma_free_channel(dspi->dma.rx_channel);
+    edma_free_slot(dspi->dma.dummy_param_slot);
 
 err:
-	return ret;
+    return ret;
 }
 
 
@@ -933,15 +933,15 @@ int rt_hw_spi_init(void)
     /* register spi bus */
     {
         static struct davinci_spi dspi;
-		rt_memset(&dspi, 0, sizeof(dspi));
-		davinci_spi_probe(&dspi, "spi1");
+        rt_memset(&dspi, 0, sizeof(dspi));
+        davinci_spi_probe(&dspi, "spi1");
     }
     /* attach cs */
     {
         static struct rt_spi_device spi_device;
         rt_spi_bus_attach_device(&spi_device, "spi10", "spi1", (void *)0);
     }
-	{
+    {
         static struct rt_spi_device spi_device;
         rt_spi_bus_attach_device(&spi_device, "spi11", "spi1", (void *)1);
     }
diff --git a/bsp/dm365/drivers/spi-davinci.h b/bsp/dm365/drivers/spi-davinci.h
index 0aa0a7eac1..d1761e03f3 100644
--- a/bsp/dm365/drivers/spi-davinci.h
+++ b/bsp/dm365/drivers/spi-davinci.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
- * Date           Author		Notes
- * 2011-01-13     weety		first version
+ * Date           Author        Notes
+ * 2011-01-13     weety     first version
  */
 
 #ifndef __DAVINCI_SPI_H
@@ -16,46 +16,46 @@ typedef unsigned short u16;
 typedef unsigned char  u8;
 typedef unsigned int   bool;
 
-#define SPI_INTERN_CS	0xFF
+#define SPI_INTERN_CS   0xFF
 
 enum {
-	SPI_VERSION_1, /* For DM355/DM365/DM6467 */
-	SPI_VERSION_2, /* For DA8xx */
+    SPI_VERSION_1, /* For DM355/DM365/DM6467 */
+    SPI_VERSION_2, /* For DA8xx */
 };
 
 /**
  * davinci_spi_config - Per-chip-select configuration for SPI slave devices
  *
- * @wdelay:	amount of delay between transmissions. Measured in number of
- *		SPI module clocks.
- * @odd_parity:	polarity of parity flag at the end of transmit data stream.
- *		0 - odd parity, 1 - even parity.
+ * @wdelay: amount of delay between transmissions. Measured in number of
+ *      SPI module clocks.
+ * @odd_parity: polarity of parity flag at the end of transmit data stream.
+ *      0 - odd parity, 1 - even parity.
  * @parity_enable: enable transmission of parity at end of each transmit
- *		data stream.
- * @io_type:	type of IO transfer. Choose between polled, interrupt and DMA.
+ *      data stream.
+ * @io_type:    type of IO transfer. Choose between polled, interrupt and DMA.
  * @timer_disable: disable chip-select timers (setup and hold)
- * @c2tdelay:	chip-select setup time. Measured in number of SPI module clocks.
- * @t2cdelay:	chip-select hold time. Measured in number of SPI module clocks.
- * @t2edelay:	transmit data finished to SPI ENAn pin inactive time. Measured
- *		in number of SPI clocks.
- * @c2edelay:	chip-select active to SPI ENAn signal active time. Measured in
- *		number of SPI clocks.
+ * @c2tdelay:   chip-select setup time. Measured in number of SPI module clocks.
+ * @t2cdelay:   chip-select hold time. Measured in number of SPI module clocks.
+ * @t2edelay:   transmit data finished to SPI ENAn pin inactive time. Measured
+ *      in number of SPI clocks.
+ * @c2edelay:   chip-select active to SPI ENAn signal active time. Measured in
+ *      number of SPI clocks.
  */
 struct davinci_spi_config {
-	u8	wdelay;
-	u8	odd_parity;
-	u8	parity_enable;
-#define SPI_IO_TYPE_INTR	0
-#define SPI_IO_TYPE_POLL	1
-#define SPI_IO_TYPE_DMA		2
-	u8	io_type;
-	u8	timer_disable;
-	u8	c2tdelay;
-	u8	t2cdelay;
-	u8	t2edelay;
-	u8	c2edelay;
+    u8  wdelay;
+    u8  odd_parity;
+    u8  parity_enable;
+#define SPI_IO_TYPE_INTR    0
+#define SPI_IO_TYPE_POLL    1
+#define SPI_IO_TYPE_DMA     2
+    u8  io_type;
+    u8  timer_disable;
+    u8  c2tdelay;
+    u8  t2cdelay;
+    u8  t2edelay;
+    u8  c2edelay;
 };
 
 extern int rt_hw_spi_init(void);
 
-#endif	/* __DAVINCI_SPI_H */
+#endif  /* __DAVINCI_SPI_H */