Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5

[lts 3.1.x] format codes

5 files changed, 559 insertions, 559 deletions

diff --git a/bsp/lpc178x/drivers/board.c b/bsp/lpc178x/drivers/board.c
index df06d7f2f8..c07150e525 100644
--- a/bsp/lpc178x/drivers/board.c
+++ b/bsp/lpc178x/drivers/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/bsp/lpc178x/drivers/board.h b/bsp/lpc178x/drivers/board.h
index 1a6d82e4b7..3c0a7fad71 100644
--- a/bsp/lpc178x/drivers/board.h
+++ b/bsp/lpc178x/drivers/board.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -31,7 +31,7 @@
 //#define RT_USING_UART2
 
 // <string name="RT_CONSOLE_DEVICE_NAME" description="The device name for console" default="uart" />
-#define RT_CONSOLE_DEVICE_NAME	"uart0"
+#define RT_CONSOLE_DEVICE_NAME  "uart0"
 
 // </RDTConfigurator>
 
diff --git a/bsp/lpc178x/drivers/emac.c b/bsp/lpc178x/drivers/emac.c
index a16dc49770..ec48ea8833 100644
--- a/bsp/lpc178x/drivers/emac.c
+++ b/bsp/lpc178x/drivers/emac.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,20 +14,20 @@
 #include "lwipopts.h"
 #include <netif/ethernetif.h>
 
-#define EMAC_PHY_AUTO		0
-#define EMAC_PHY_10MBIT		1
-#define EMAC_PHY_100MBIT	2
+#define EMAC_PHY_AUTO       0
+#define EMAC_PHY_10MBIT     1
+#define EMAC_PHY_100MBIT    2
 
 #define MAX_ADDR_LEN 6
 struct lpc17xx_emac
 {
-	/* inherit from ethernet device */
-	struct eth_device parent;
+    /* inherit from ethernet device */
+    struct eth_device parent;
 
-	rt_uint8_t phy_mode;
+    rt_uint8_t phy_mode;
 
-	/* interface address info. */
-	rt_uint8_t  dev_addr[MAX_ADDR_LEN];		/* hw address	*/
+    /* interface address info. */
+    rt_uint8_t  dev_addr[MAX_ADDR_LEN];     /* hw address   */
 };
 static struct lpc17xx_emac lpc17xx_emac_device;
 static struct rt_semaphore sem_lock;
@@ -39,39 +39,39 @@ static rt_uint16_t read_PHY (rt_uint8_t PhyReg) ;
 
 void ENET_IRQHandler(void)
 {
-	rt_uint32_t status;
+    rt_uint32_t status;
 
     /* enter interrupt */
     rt_interrupt_enter();
 
-	status = LPC_EMAC->IntStatus;
+    status = LPC_EMAC->IntStatus;
 
-	if (status & INT_RX_DONE)
-	{
-		/* Disable EMAC RxDone interrupts. */
-		LPC_EMAC->IntEnable = INT_TX_DONE;
+    if (status & INT_RX_DONE)
+    {
+        /* Disable EMAC RxDone interrupts. */
+        LPC_EMAC->IntEnable = INT_TX_DONE;
 
-		/* a frame has been received */
-		eth_device_ready(&(lpc17xx_emac_device.parent));
-	}
-	else if (status & INT_TX_DONE)
-	{
-		/* set event */
-		rt_event_send(&tx_event, 0x01);
-	}
+        /* a frame has been received */
+        eth_device_ready(&(lpc17xx_emac_device.parent));
+    }
+    else if (status & INT_TX_DONE)
+    {
+        /* set event */
+        rt_event_send(&tx_event, 0x01);
+    }
 
-	if (status & INT_RX_OVERRUN)
-	{
-		rt_kprintf("rx overrun\n");
-	}
+    if (status & INT_RX_OVERRUN)
+    {
+        rt_kprintf("rx overrun\n");
+    }
 
-	if (status & INT_TX_UNDERRUN)
-	{
-		rt_kprintf("tx underrun\n");
-	}
+    if (status & INT_TX_UNDERRUN)
+    {
+        rt_kprintf("tx underrun\n");
+    }
 
-	/* Clear the interrupt. */
-	LPC_EMAC->IntClear = status;
+    /* Clear the interrupt. */
+    LPC_EMAC->IntClear = status;
 
     /* leave interrupt */
     rt_interrupt_leave();
@@ -80,84 +80,84 @@ void ENET_IRQHandler(void)
 /* phy write */
 static void write_PHY (rt_uint32_t PhyReg, rt_uint32_t Value)
 {
-	unsigned int tout;
+    unsigned int tout;
 
-	LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-	LPC_EMAC->MWTD = Value;
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MWTD = Value;
 
-	/* Wait utill operation completed */
-	tout = 0;
-	for (tout = 0; tout < MII_WR_TOUT; tout++)
-	{
-		if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
-		{
-			break;
-		}
-	}
+    /* Wait utill operation completed */
+    tout = 0;
+    for (tout = 0; tout < MII_WR_TOUT; tout++)
+    {
+        if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
+        {
+            break;
+        }
+    }
 }
 
 /* phy read */
 static rt_uint16_t read_PHY (rt_uint8_t PhyReg)
 {
-	rt_uint32_t tout;
+    rt_uint32_t tout;
 
-	LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
-	LPC_EMAC->MCMD = MCMD_READ;
+    LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
+    LPC_EMAC->MCMD = MCMD_READ;
 
-	/* Wait until operation completed */
-	tout = 0;
-	for (tout = 0; tout < MII_RD_TOUT; tout++)
-	{
-		if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
-		{
-			break;
-		}
-	}
-	LPC_EMAC->MCMD = 0;
-	return (LPC_EMAC->MRDD);
+    /* Wait until operation completed */
+    tout = 0;
+    for (tout = 0; tout < MII_RD_TOUT; tout++)
+    {
+        if ((LPC_EMAC->MIND & MIND_BUSY) == 0)
+        {
+            break;
+        }
+    }
+    LPC_EMAC->MCMD = 0;
+    return (LPC_EMAC->MRDD);
 }
 
 /* init rx descriptor */
 rt_inline void rx_descr_init (void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	for (i = 0; i < NUM_RX_FRAG; i++)
-	{
-		RX_DESC_PACKET(i)  = RX_BUF(i);
-		RX_DESC_CTRL(i)    = RCTRL_INT | (ETH_FRAG_SIZE-1);
-		RX_STAT_INFO(i)    = 0;
-		RX_STAT_HASHCRC(i) = 0;
-	}
+    for (i = 0; i < NUM_RX_FRAG; i++)
+    {
+        RX_DESC_PACKET(i)  = RX_BUF(i);
+        RX_DESC_CTRL(i)    = RCTRL_INT | (ETH_FRAG_SIZE-1);
+        RX_STAT_INFO(i)    = 0;
+        RX_STAT_HASHCRC(i) = 0;
+    }
 
-	/* Set EMAC Receive Descriptor Registers. */
-	LPC_EMAC->RxDescriptor    = RX_DESC_BASE;
-	LPC_EMAC->RxStatus        = RX_STAT_BASE;
-	LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
+    /* Set EMAC Receive Descriptor Registers. */
+    LPC_EMAC->RxDescriptor    = RX_DESC_BASE;
+    LPC_EMAC->RxStatus        = RX_STAT_BASE;
+    LPC_EMAC->RxDescriptorNumber = NUM_RX_FRAG-1;
 
-	/* Rx Descriptors Point to 0 */
-	LPC_EMAC->RxConsumeIndex  = 0;
+    /* Rx Descriptors Point to 0 */
+    LPC_EMAC->RxConsumeIndex  = 0;
 }
 
 /* init tx descriptor */
 rt_inline void tx_descr_init (void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	for (i = 0; i < NUM_TX_FRAG; i++)
-	{
-		TX_DESC_PACKET(i) = TX_BUF(i);
-		TX_DESC_CTRL(i)   = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
-		TX_STAT_INFO(i)   = 0;
-	}
+    for (i = 0; i < NUM_TX_FRAG; i++)
+    {
+        TX_DESC_PACKET(i) = TX_BUF(i);
+        TX_DESC_CTRL(i)   = (1ul<<31) | (1ul<<30) | (1ul<<29) | (1ul<<28) | (1ul<<26) | (ETH_FRAG_SIZE-1);
+        TX_STAT_INFO(i)   = 0;
+    }
 
-	/* Set EMAC Transmit Descriptor Registers. */
-	LPC_EMAC->TxDescriptor    = TX_DESC_BASE;
-	LPC_EMAC->TxStatus        = TX_STAT_BASE;
-	LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
+    /* Set EMAC Transmit Descriptor Registers. */
+    LPC_EMAC->TxDescriptor    = TX_DESC_BASE;
+    LPC_EMAC->TxStatus        = TX_STAT_BASE;
+    LPC_EMAC->TxDescriptorNumber = NUM_TX_FRAG-1;
 
-	/* Tx Descriptors Point to 0 */
-	LPC_EMAC->TxProduceIndex  = 0;
+    /* Tx Descriptors Point to 0 */
+    LPC_EMAC->TxProduceIndex  = 0;
 }
 
 /*
@@ -178,375 +178,375 @@ REF_CLK   P1_15
 */
 static rt_err_t lpc17xx_emac_init(rt_device_t dev)
 {
-	/* Initialize the EMAC ethernet controller. */
-	rt_uint32_t regv, tout;
+    /* Initialize the EMAC ethernet controller. */
+    rt_uint32_t regv, tout;
 
-	/* Power Up the EMAC controller. */
-	LPC_SC->PCONP |= (1UL<<30);
+    /* Power Up the EMAC controller. */
+    LPC_SC->PCONP |= (1UL<<30);
 
-	/* config RESET */
-	PINSEL_ConfigPin(3, 19, 0);
-	PINSEL_SetPinMode(3, 19, IOCON_MODE_PLAIN);
-	LPC_GPIO3->DIR |= 1<<19;
-	LPC_GPIO3->CLR = 1<<19;
+    /* config RESET */
+    PINSEL_ConfigPin(3, 19, 0);
+    PINSEL_SetPinMode(3, 19, IOCON_MODE_PLAIN);
+    LPC_GPIO3->DIR |= 1<<19;
+    LPC_GPIO3->CLR = 1<<19;
 
-	/* Enable P1 Ethernet Pins. */
-	PINSEL_ConfigPin(1, 0, 1);  /**< P1_0  ENET_TXD0 */
-	PINSEL_ConfigPin(1, 1, 1);  /**< P1_1  ENET_TXD1 */
-	PINSEL_ConfigPin(1, 4, 1);  /**< P1_4  ENET_TX_EN */
-	PINSEL_ConfigPin(1, 8, 1);  /**< P1_8  ENET_CRS_DV */
-	PINSEL_ConfigPin(1, 9, 1);  /**< P1_9  ENET_RXD0 */
-	PINSEL_ConfigPin(1, 10, 1); /**< P1_10 ENET_RXD1 */
-	PINSEL_ConfigPin(1, 14, 1); /**< P1_14 ENET_RX_ER */
-	PINSEL_ConfigPin(1, 15, 1); /**< P1_15 ENET_REF_CLK */
-	PINSEL_ConfigPin(1, 16, 1); /**< P1_16 ENET_MDC */
-	PINSEL_ConfigPin(1, 17, 1); /**< P1_17 ENET_MDIO */
+    /* Enable P1 Ethernet Pins. */
+    PINSEL_ConfigPin(1, 0, 1);  /**< P1_0  ENET_TXD0 */
+    PINSEL_ConfigPin(1, 1, 1);  /**< P1_1  ENET_TXD1 */
+    PINSEL_ConfigPin(1, 4, 1);  /**< P1_4  ENET_TX_EN */
+    PINSEL_ConfigPin(1, 8, 1);  /**< P1_8  ENET_CRS_DV */
+    PINSEL_ConfigPin(1, 9, 1);  /**< P1_9  ENET_RXD0 */
+    PINSEL_ConfigPin(1, 10, 1); /**< P1_10 ENET_RXD1 */
+    PINSEL_ConfigPin(1, 14, 1); /**< P1_14 ENET_RX_ER */
+    PINSEL_ConfigPin(1, 15, 1); /**< P1_15 ENET_REF_CLK */
+    PINSEL_ConfigPin(1, 16, 1); /**< P1_16 ENET_MDC */
+    PINSEL_ConfigPin(1, 17, 1); /**< P1_17 ENET_MDIO */
 
-	LPC_GPIO3->SET = 1<<19;
+    LPC_GPIO3->SET = 1<<19;
 
-	/* Reset all EMAC internal modules. */
-	LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
-				 MAC1_SIM_RES | MAC1_SOFT_RES;
-	LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
+    /* Reset all EMAC internal modules. */
+    LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
+                 MAC1_SIM_RES | MAC1_SOFT_RES;
+    LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
 
-	/* A short delay after reset. */
-	for (tout = 100; tout; tout--);
+    /* A short delay after reset. */
+    for (tout = 100; tout; tout--);
 
-	/* Initialize MAC control registers. */
-	LPC_EMAC->MAC1 = MAC1_PASS_ALL;
-	LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
-	LPC_EMAC->MAXF = ETH_MAX_FLEN;
-	LPC_EMAC->CLRT = CLRT_DEF;
-	LPC_EMAC->IPGR = IPGR_DEF;
+    /* Initialize MAC control registers. */
+    LPC_EMAC->MAC1 = MAC1_PASS_ALL;
+    LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
+    LPC_EMAC->MAXF = ETH_MAX_FLEN;
+    LPC_EMAC->CLRT = CLRT_DEF;
+    LPC_EMAC->IPGR = IPGR_DEF;
 
-	/* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
-	/* Enable Reduced MII interface. */
-	LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
-	for (tout = 100; tout; tout--);
-	LPC_EMAC->MCFG = MCFG_CLK_DIV20;
+    /* PCLK=18MHz, clock select=6, MDC=18/6=3MHz */
+    /* Enable Reduced MII interface. */
+    LPC_EMAC->MCFG = MCFG_CLK_DIV20 | MCFG_RES_MII;
+    for (tout = 100; tout; tout--);
+    LPC_EMAC->MCFG = MCFG_CLK_DIV20;
 
-	/* Enable Reduced MII interface. */
-	LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
+    /* Enable Reduced MII interface. */
+    LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM | CR_PASS_RX_FILT;
 
-	/* Reset Reduced MII Logic. */
-	LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
-	for (tout = 100; tout; tout--);
-	LPC_EMAC->SUPP = SUPP_SPEED;
+    /* Reset Reduced MII Logic. */
+    LPC_EMAC->SUPP = SUPP_RES_RMII | SUPP_SPEED;
+    for (tout = 100; tout; tout--);
+    LPC_EMAC->SUPP = SUPP_SPEED;
 
-	/* Put the PHY in reset mode */
-	write_PHY (PHY_REG_BMCR, 0x8000);
-	for (tout = 1000; tout; tout--);
+    /* Put the PHY in reset mode */
+    write_PHY (PHY_REG_BMCR, 0x8000);
+    for (tout = 1000; tout; tout--);
 
-//	/* Wait for hardware reset to end. */
-//	for (tout = 0; tout < 0x100000; tout++)
-//	{
-//		regv = read_PHY (PHY_REG_BMCR);
-//		if (!(regv & 0x8000))
-//		{
-//			/* Reset complete */
-//			break;
-//		}
-//	}
-//	if (tout >= 0x100000)
+//  /* Wait for hardware reset to end. */
+//  for (tout = 0; tout < 0x100000; tout++)
+//  {
+//      regv = read_PHY (PHY_REG_BMCR);
+//      if (!(regv & 0x8000))
+//      {
+//          /* Reset complete */
+//          break;
+//      }
+//  }
+//  if (tout >= 0x100000)
 //    {
 //        rt_kprintf("reset failed\r\n");
 //        return -RT_ERROR; /* reset failed */
 //    }
 
-//	/* Check if this is a DP83848C PHY. */
-//	id1 = read_PHY (PHY_REG_IDR1);
-//	id2 = read_PHY (PHY_REG_IDR2);
+//  /* Check if this is a DP83848C PHY. */
+//  id1 = read_PHY (PHY_REG_IDR1);
+//  id2 = read_PHY (PHY_REG_IDR2);
 //
-//	if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
-//		return -RT_ERROR;
+//  if (((id1 << 16) | (id2 & 0xFFF0)) != DP83848C_ID)
+//      return -RT_ERROR;
 
-	/* Configure the PHY device */
-	/* Configure the PHY device */
-	switch (lpc17xx_emac_device.phy_mode)
-	{
-	case EMAC_PHY_AUTO:
-		/* Use autonegotiation about the link speed. */
-		write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
-		/* Wait to complete Auto_Negotiation. */
-//		for (tout = 0; tout < 0x100000; tout++)
-//		{
-//			regv = read_PHY (PHY_REG_BMSR);
-//			if (regv & 0x0020)
-//			{
-//				/* Autonegotiation Complete. */
-//				break;
-//			}
-//		}
-		break;
-	case EMAC_PHY_10MBIT:
-		/* Connect at 10MBit */
-		write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
-		break;
-	case EMAC_PHY_100MBIT:
-		/* Connect at 100MBit */
-		write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
-		break;
-	}
-	if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
+    /* Configure the PHY device */
+    /* Configure the PHY device */
+    switch (lpc17xx_emac_device.phy_mode)
+    {
+    case EMAC_PHY_AUTO:
+        /* Use autonegotiation about the link speed. */
+        write_PHY (PHY_REG_BMCR, PHY_AUTO_NEG);
+        /* Wait to complete Auto_Negotiation. */
+//      for (tout = 0; tout < 0x100000; tout++)
+//      {
+//          regv = read_PHY (PHY_REG_BMSR);
+//          if (regv & 0x0020)
+//          {
+//              /* Autonegotiation Complete. */
+//              break;
+//          }
+//      }
+        break;
+    case EMAC_PHY_10MBIT:
+        /* Connect at 10MBit */
+        write_PHY (PHY_REG_BMCR, PHY_FULLD_10M);
+        break;
+    case EMAC_PHY_100MBIT:
+        /* Connect at 100MBit */
+        write_PHY (PHY_REG_BMCR, PHY_FULLD_100M);
+        break;
+    }
+    if (tout >= 0x100000) return -RT_ERROR; // auto_neg failed
 
-//	/* Check the link status. */
-//	for (tout = 0; tout < 0x10000; tout++)
-//	{
-//		regv = read_PHY (PHY_REG_STS);
-//		if (regv & 0x0001)
-//		{
-//			/* Link is on. */
-//			break;
-//		}
-//	}
-//	if (tout >= 0x10000) return -RT_ERROR;
+//  /* Check the link status. */
+//  for (tout = 0; tout < 0x10000; tout++)
+//  {
+//      regv = read_PHY (PHY_REG_STS);
+//      if (regv & 0x0001)
+//      {
+//          /* Link is on. */
+//          break;
+//      }
+//  }
+//  if (tout >= 0x10000) return -RT_ERROR;
 
-	regv = 0x0004;
-	/* Configure Full/Half Duplex mode. */
-	if (regv & 0x0004)
-	{
-		/* Full duplex is enabled. */
-		LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
-		LPC_EMAC->Command |= CR_FULL_DUP;
-		LPC_EMAC->IPGT     = IPGT_FULL_DUP;
-	}
-	else
-	{
-		/* Half duplex mode. */
-		LPC_EMAC->IPGT = IPGT_HALF_DUP;
-	}
+    regv = 0x0004;
+    /* Configure Full/Half Duplex mode. */
+    if (regv & 0x0004)
+    {
+        /* Full duplex is enabled. */
+        LPC_EMAC->MAC2    |= MAC2_FULL_DUP;
+        LPC_EMAC->Command |= CR_FULL_DUP;
+        LPC_EMAC->IPGT     = IPGT_FULL_DUP;
+    }
+    else
+    {
+        /* Half duplex mode. */
+        LPC_EMAC->IPGT = IPGT_HALF_DUP;
+    }
 
-	/* Configure 100MBit/10MBit mode. */
-	if (regv & 0x0002)
-	{
-		/* 10MBit mode. */
-		LPC_EMAC->SUPP = 0;
-	}
-	else
-	{
-		/* 100MBit mode. */
-		LPC_EMAC->SUPP = SUPP_SPEED;
-	}
+    /* Configure 100MBit/10MBit mode. */
+    if (regv & 0x0002)
+    {
+        /* 10MBit mode. */
+        LPC_EMAC->SUPP = 0;
+    }
+    else
+    {
+        /* 100MBit mode. */
+        LPC_EMAC->SUPP = SUPP_SPEED;
+    }
 
-	/* Set the Ethernet MAC Address registers */
-	LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
-	LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
-	LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
+    /* Set the Ethernet MAC Address registers */
+    LPC_EMAC->SA0 = (lpc17xx_emac_device.dev_addr[1]<<8) | lpc17xx_emac_device.dev_addr[0];
+    LPC_EMAC->SA1 = (lpc17xx_emac_device.dev_addr[3]<<8) | lpc17xx_emac_device.dev_addr[2];
+    LPC_EMAC->SA2 = (lpc17xx_emac_device.dev_addr[5]<<8) | lpc17xx_emac_device.dev_addr[4];
 
-	/* Initialize Tx and Rx DMA Descriptors */
-	rx_descr_init ();
-	tx_descr_init ();
+    /* Initialize Tx and Rx DMA Descriptors */
+    rx_descr_init ();
+    tx_descr_init ();
 
-	/* Receive Broadcast and Perfect Match Packets */
-	LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
+    /* Receive Broadcast and Perfect Match Packets */
+    LPC_EMAC->RxFilterCtrl = RFC_BCAST_EN | RFC_PERFECT_EN;
 
-	/* Reset all interrupts */
-	LPC_EMAC->IntClear  = 0xFFFF;
+    /* Reset all interrupts */
+    LPC_EMAC->IntClear  = 0xFFFF;
 
-	/* Enable EMAC interrupts. */
-	LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
+    /* Enable EMAC interrupts. */
+    LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
 
-	/* Enable receive and transmit mode of MAC Ethernet core */
-	LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);
-	LPC_EMAC->MAC1     |= MAC1_REC_EN;
+    /* Enable receive and transmit mode of MAC Ethernet core */
+    LPC_EMAC->Command  |= (CR_RX_EN | CR_TX_EN);
+    LPC_EMAC->MAC1     |= MAC1_REC_EN;
 
-	/* Enable the ENET Interrupt */
-	NVIC_EnableIRQ(ENET_IRQn);
+    /* Enable the ENET Interrupt */
+    NVIC_EnableIRQ(ENET_IRQn);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t lpc17xx_emac_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t lpc17xx_emac_close(rt_device_t dev)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t lpc17xx_emac_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_size_t lpc17xx_emac_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_set_errno(-RT_ENOSYS);
-	return 0;
+    rt_set_errno(-RT_ENOSYS);
+    return 0;
 }
 
 static rt_err_t lpc17xx_emac_control(rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-	case NIOCTL_GADDR:
-		/* get mac address */
-		if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
-		else return -RT_ERROR;
-		break;
+    switch (cmd)
+    {
+    case NIOCTL_GADDR:
+        /* get mac address */
+        if (args) rt_memcpy(args, lpc17xx_emac_device.dev_addr, 6);
+        else return -RT_ERROR;
+        break;
 
-	default :
-		break;
-	}
+    default :
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* EtherNet Device Interface */
 /* transmit packet. */
 rt_err_t lpc17xx_emac_tx( rt_device_t dev, struct pbuf* p)
 {
-	rt_uint32_t Index, IndexNext;
-	struct pbuf *q;
-	rt_uint8_t *ptr;
+    rt_uint32_t Index, IndexNext;
+    struct pbuf *q;
+    rt_uint8_t *ptr;
 
-	/* calculate next index */
-	IndexNext = LPC_EMAC->TxProduceIndex + 1;
-	if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
+    /* calculate next index */
+    IndexNext = LPC_EMAC->TxProduceIndex + 1;
+    if(IndexNext > LPC_EMAC->TxDescriptorNumber) IndexNext = 0;
 
-	/* check whether block is full */
-	while (IndexNext == LPC_EMAC->TxConsumeIndex)
-	{
-		rt_err_t result;
-		rt_uint32_t recved;
+    /* check whether block is full */
+    while (IndexNext == LPC_EMAC->TxConsumeIndex)
+    {
+        rt_err_t result;
+        rt_uint32_t recved;
 
-		/* there is no block yet, wait a flag */
-		result = rt_event_recv(&tx_event, 0x01,
-			RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
+        /* there is no block yet, wait a flag */
+        result = rt_event_recv(&tx_event, 0x01,
+            RT_EVENT_FLAG_AND | RT_EVENT_FLAG_CLEAR, RT_WAITING_FOREVER, &recved);
 
-		RT_ASSERT(result == RT_EOK);
-	}
+        RT_ASSERT(result == RT_EOK);
+    }
 
-	/* lock EMAC device */
-	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+    /* lock EMAC device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
-	/* get produce index */
-	Index = LPC_EMAC->TxProduceIndex;
+    /* get produce index */
+    Index = LPC_EMAC->TxProduceIndex;
 
-	/* calculate next index */
-	IndexNext = LPC_EMAC->TxProduceIndex + 1;
-	if(IndexNext > LPC_EMAC->TxDescriptorNumber)
-		IndexNext = 0;
+    /* calculate next index */
+    IndexNext = LPC_EMAC->TxProduceIndex + 1;
+    if(IndexNext > LPC_EMAC->TxDescriptorNumber)
+        IndexNext = 0;
 
-	/* copy data to tx buffer */
-	q = p;
-	ptr = (rt_uint8_t*)TX_BUF(Index);
-	while (q)
-	{
-		memcpy(ptr, q->payload, q->len);
-		ptr += q->len;
-		q = q->next;
-	}
+    /* copy data to tx buffer */
+    q = p;
+    ptr = (rt_uint8_t*)TX_BUF(Index);
+    while (q)
+    {
+        memcpy(ptr, q->payload, q->len);
+        ptr += q->len;
+        q = q->next;
+    }
 
-	TX_DESC_CTRL(Index) &= ~0x7ff;
-	TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
+    TX_DESC_CTRL(Index) &= ~0x7ff;
+    TX_DESC_CTRL(Index) |= (p->tot_len - 1) & 0x7ff;
 
-	/* change index to the next */
-	LPC_EMAC->TxProduceIndex = IndexNext;
+    /* change index to the next */
+    LPC_EMAC->TxProduceIndex = IndexNext;
 
-	/* unlock EMAC device */
-	rt_sem_release(&sem_lock);
+    /* unlock EMAC device */
+    rt_sem_release(&sem_lock);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /* reception packet. */
 struct pbuf *lpc17xx_emac_rx(rt_device_t dev)
 {
-	struct pbuf* p;
-	rt_uint32_t size;
-	rt_uint32_t Index;
+    struct pbuf* p;
+    rt_uint32_t size;
+    rt_uint32_t Index;
 
-	/* init p pointer */
-	p = RT_NULL;
+    /* init p pointer */
+    p = RT_NULL;
 
-	/* lock EMAC device */
-	rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
+    /* lock EMAC device */
+    rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
 
-	Index = LPC_EMAC->RxConsumeIndex;
-	if(Index != LPC_EMAC->RxProduceIndex)
-	{
-		size = (RX_STAT_INFO(Index) & 0x7ff)+1;
-		if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
+    Index = LPC_EMAC->RxConsumeIndex;
+    if(Index != LPC_EMAC->RxProduceIndex)
+    {
+        size = (RX_STAT_INFO(Index) & 0x7ff)+1;
+        if (size > ETH_FRAG_SIZE) size = ETH_FRAG_SIZE;
 
-		/* allocate buffer */
-		p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
-		if (p != RT_NULL)
-		{
-			struct pbuf* q;
-			rt_uint8_t *ptr;
+        /* allocate buffer */
+        p = pbuf_alloc(PBUF_LINK, size, PBUF_RAM);
+        if (p != RT_NULL)
+        {
+            struct pbuf* q;
+            rt_uint8_t *ptr;
 
-			ptr = (rt_uint8_t*)RX_BUF(Index);
-			for (q = p; q != RT_NULL; q= q->next)
-			{
-				memcpy(q->payload, ptr, q->len);
-				ptr += q->len;
-			}
-		}
+            ptr = (rt_uint8_t*)RX_BUF(Index);
+            for (q = p; q != RT_NULL; q= q->next)
+            {
+                memcpy(q->payload, ptr, q->len);
+                ptr += q->len;
+            }
+        }
 
-		/* move Index to the next */
-		if(++Index > LPC_EMAC->RxDescriptorNumber)
-			Index = 0;
+        /* move Index to the next */
+        if(++Index > LPC_EMAC->RxDescriptorNumber)
+            Index = 0;
 
-		/* set consume index */
-		LPC_EMAC->RxConsumeIndex = Index;
-	}
-	else
-	{
-		/* Enable RxDone interrupt */
-		LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
-	}
+        /* set consume index */
+        LPC_EMAC->RxConsumeIndex = Index;
+    }
+    else
+    {
+        /* Enable RxDone interrupt */
+        LPC_EMAC->IntEnable = INT_RX_DONE | INT_TX_DONE;
+    }
 
-	/* unlock EMAC device */
-	rt_sem_release(&sem_lock);
+    /* unlock EMAC device */
+    rt_sem_release(&sem_lock);
 
-	return p;
+    return p;
 }
 
 void lpc17xx_emac_hw_init(void)
 {
-	rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
-	rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
+    rt_event_init(&tx_event, "tx_event", RT_IPC_FLAG_FIFO);
+    rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
 
-	/* set autonegotiation mode */
-	lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
+    /* set autonegotiation mode */
+    lpc17xx_emac_device.phy_mode = EMAC_PHY_AUTO;
 
-	// OUI 00-60-37 NXP Semiconductors
-	lpc17xx_emac_device.dev_addr[0] = 0x00;
-	lpc17xx_emac_device.dev_addr[1] = 0x60;
-	lpc17xx_emac_device.dev_addr[2] = 0x37;
-	/* set mac address: (only for test) */
-	lpc17xx_emac_device.dev_addr[3] = 0x12;
-	lpc17xx_emac_device.dev_addr[4] = 0x34;
-	lpc17xx_emac_device.dev_addr[5] = 0x56;
+    // OUI 00-60-37 NXP Semiconductors
+    lpc17xx_emac_device.dev_addr[0] = 0x00;
+    lpc17xx_emac_device.dev_addr[1] = 0x60;
+    lpc17xx_emac_device.dev_addr[2] = 0x37;
+    /* set mac address: (only for test) */
+    lpc17xx_emac_device.dev_addr[3] = 0x12;
+    lpc17xx_emac_device.dev_addr[4] = 0x34;
+    lpc17xx_emac_device.dev_addr[5] = 0x56;
 
-	lpc17xx_emac_device.parent.parent.init		= lpc17xx_emac_init;
-	lpc17xx_emac_device.parent.parent.open		= lpc17xx_emac_open;
-	lpc17xx_emac_device.parent.parent.close		= lpc17xx_emac_close;
-	lpc17xx_emac_device.parent.parent.read		= lpc17xx_emac_read;
-	lpc17xx_emac_device.parent.parent.write		= lpc17xx_emac_write;
-	lpc17xx_emac_device.parent.parent.control	= lpc17xx_emac_control;
-	lpc17xx_emac_device.parent.parent.user_data	= RT_NULL;
+    lpc17xx_emac_device.parent.parent.init      = lpc17xx_emac_init;
+    lpc17xx_emac_device.parent.parent.open      = lpc17xx_emac_open;
+    lpc17xx_emac_device.parent.parent.close     = lpc17xx_emac_close;
+    lpc17xx_emac_device.parent.parent.read      = lpc17xx_emac_read;
+    lpc17xx_emac_device.parent.parent.write     = lpc17xx_emac_write;
+    lpc17xx_emac_device.parent.parent.control   = lpc17xx_emac_control;
+    lpc17xx_emac_device.parent.parent.user_data = RT_NULL;
 
-	lpc17xx_emac_device.parent.eth_rx			= lpc17xx_emac_rx;
-	lpc17xx_emac_device.parent.eth_tx			= lpc17xx_emac_tx;
+    lpc17xx_emac_device.parent.eth_rx           = lpc17xx_emac_rx;
+    lpc17xx_emac_device.parent.eth_tx           = lpc17xx_emac_tx;
 
-	eth_device_init(&(lpc17xx_emac_device.parent), "e0");
+    eth_device_init(&(lpc17xx_emac_device.parent), "e0");
 }
 
 #ifdef RT_USING_FINSH
 #include <finsh.h>
 void emac_dump()
 {
-	rt_kprintf("Command  : %08x\n", LPC_EMAC->Command);
-	rt_kprintf("Status   : %08x\n", LPC_EMAC->Status);
-	rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus);
-	rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus);
-	rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable);
-	rt_kprintf("IntStatus: %08x\n", LPC_EMAC->IntStatus);
+    rt_kprintf("Command  : %08x\n", LPC_EMAC->Command);
+    rt_kprintf("Status   : %08x\n", LPC_EMAC->Status);
+    rt_kprintf("RxStatus : %08x\n", LPC_EMAC->RxStatus);
+    rt_kprintf("TxStatus : %08x\n", LPC_EMAC->TxStatus);
+    rt_kprintf("IntEnable: %08x\n", LPC_EMAC->IntEnable);
+    rt_kprintf("IntStatus: %08x\n", LPC_EMAC->IntStatus);
 }
 FINSH_FUNCTION_EXPORT(emac_dump, dump emac register);
 #endif
diff --git a/bsp/lpc178x/drivers/lpc17xx_lcd.c b/bsp/lpc178x/drivers/lpc17xx_lcd.c
index cc488dfebb..f8f405a540 100644
--- a/bsp/lpc178x/drivers/lpc17xx_lcd.c
+++ b/bsp/lpc178x/drivers/lpc17xx_lcd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,8 +13,8 @@
 
 #include "drv_glcd.h"
 
-#define RT_HW_LCD_WIDTH		480
-#define RT_HW_LCD_HEIGHT	272
+#define RT_HW_LCD_WIDTH     480
+#define RT_HW_LCD_HEIGHT    272
 
 static struct rt_device_graphic_info _lcd_info;
 static struct rt_device  lcd;
@@ -23,38 +23,38 @@ static struct rt_device  lcd;
 static rt_err_t rt_lcd_init (rt_device_t dev)
 {
     PINSEL_ConfigPin(5, 4, 0);
-	LPC_GPIO5->DIR |= 1<<4;
-	LPC_GPIO5->CLR  = 1<<4;
-	LPC_GPIO5->SET  = 1<<4;
+    LPC_GPIO5->DIR |= 1<<4;
+    LPC_GPIO5->CLR  = 1<<4;
+    LPC_GPIO5->SET  = 1<<4;
 
-	/*Disable LCD controller*/
-	GLCD_Ctrl (FALSE);
-	/*Init LCD and copy picture in video RAM*/
-	GLCD_Init (_lcd_info.framebuffer);
-	/*Enable LCD*/
-	GLCD_Ctrl (TRUE);
+    /*Disable LCD controller*/
+    GLCD_Ctrl (FALSE);
+    /*Init LCD and copy picture in video RAM*/
+    GLCD_Init (_lcd_info.framebuffer);
+    /*Enable LCD*/
+    GLCD_Ctrl (TRUE);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_lcd_control (rt_device_t dev, int cmd, void *args)
 {
-	switch (cmd)
-	{
-	case RTGRAPHIC_CTRL_RECT_UPDATE:
-		break;
-	case RTGRAPHIC_CTRL_POWERON:
-		break;
-	case RTGRAPHIC_CTRL_POWEROFF:
-		break;
-	case RTGRAPHIC_CTRL_GET_INFO:
-		rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
-		break;
-	case RTGRAPHIC_CTRL_SET_MODE:
-		break;
-	}
+    switch (cmd)
+    {
+    case RTGRAPHIC_CTRL_RECT_UPDATE:
+        break;
+    case RTGRAPHIC_CTRL_POWERON:
+        break;
+    case RTGRAPHIC_CTRL_POWEROFF:
+        break;
+    case RTGRAPHIC_CTRL_GET_INFO:
+        rt_memcpy(args, &_lcd_info, sizeof(_lcd_info));
+        break;
+    case RTGRAPHIC_CTRL_SET_MODE:
+        break;
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 
@@ -63,27 +63,27 @@ void rt_hw_lcd_init(void)
 {
     rt_uint16_t * _rt_framebuffer = RT_NULL;
 
-	// _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT*RT_HW_LCD_WIDTH, 8);
-	// if (_rt_framebuffer == RT_NULL) return; /* no memory yet */
+    // _rt_framebuffer = rt_malloc_align(sizeof(rt_uint16_t)*RT_HW_LCD_HEIGHT*RT_HW_LCD_WIDTH, 8);
+    // if (_rt_framebuffer == RT_NULL) return; /* no memory yet */
 
-	_rt_framebuffer = (rt_uint16_t *)0xA0000000;
+    _rt_framebuffer = (rt_uint16_t *)0xA0000000;
 
-	_lcd_info.bits_per_pixel = 16;
-	_lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
-	_lcd_info.framebuffer = (void*)_rt_framebuffer;
-	_lcd_info.width = RT_HW_LCD_WIDTH;
-	_lcd_info.height = RT_HW_LCD_HEIGHT;
+    _lcd_info.bits_per_pixel = 16;
+    _lcd_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565;
+    _lcd_info.framebuffer = (void*)_rt_framebuffer;
+    _lcd_info.width = RT_HW_LCD_WIDTH;
+    _lcd_info.height = RT_HW_LCD_HEIGHT;
 
-	/* init device structure */
-	lcd.type = RT_Device_Class_Graphic;
-	lcd.init = rt_lcd_init;
-	lcd.open = RT_NULL;
-	lcd.close = RT_NULL;
-	lcd.control = rt_lcd_control;
-	lcd.user_data = (void*)&_lcd_info;
+    /* init device structure */
+    lcd.type = RT_Device_Class_Graphic;
+    lcd.init = rt_lcd_init;
+    lcd.open = RT_NULL;
+    lcd.close = RT_NULL;
+    lcd.control = rt_lcd_control;
+    lcd.user_data = (void*)&_lcd_info;
 
-	/* register lcd device to RT-Thread */
-	rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR);
+    /* register lcd device to RT-Thread */
+    rt_device_register(&lcd, "lcd", RT_DEVICE_FLAG_RDWR);
 }
 
 void lcd_fill(uint8_t * start, uint8_t * end, uint8_t pixel)
diff --git a/bsp/lpc178x/drivers/uart.c b/bsp/lpc178x/drivers/uart.c
index 0d92eb1fca..cb8e68d30c 100644
--- a/bsp/lpc178x/drivers/uart.c
+++ b/bsp/lpc178x/drivers/uart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -25,14 +25,14 @@
 
 struct rt_uart_lpc
 {
-	struct rt_device parent;
+    struct rt_device parent;
 
-	LPC_UART_TypeDef * UART;
-	IRQn_Type UART_IRQn;
+    LPC_UART_TypeDef * UART;
+    IRQn_Type UART_IRQn;
 
-	/* buffer for reception */
-	rt_uint8_t read_index, save_index;
-	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
+    /* buffer for reception */
+    rt_uint8_t read_index, save_index;
+    rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
 };
 
 #ifdef RT_USING_UART0
@@ -45,96 +45,96 @@ struct rt_uart_lpc uart1_device;
 #ifdef RT_USING_UART0
 void UART0_IRQHandler(void)
 {
-	rt_ubase_t level, iir;
+    rt_ubase_t level, iir;
     struct rt_uart_lpc* uart = &uart0_device;
 
-	/* enter interrupt */
-	rt_interrupt_enter();
+    /* enter interrupt */
+    rt_interrupt_enter();
 
     /* read IIR and clear it */
-	iir = uart->UART->IIR;
+    iir = uart->UART->IIR;
 
-	if (iir == UART_IIR_INTID_RDA)	    /* Receive Data Available */
-	{
-		/* Receive Data Available */
+    if (iir == UART_IIR_INTID_RDA)      /* Receive Data Available */
+    {
+        /* Receive Data Available */
         uart->rx_buffer[uart->save_index] = uart->UART->RBR;
 
         level = rt_hw_interrupt_disable();
-		uart->save_index ++;
+        uart->save_index ++;
         if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
             uart->save_index = 0;
         rt_hw_interrupt_enable(level);
 
-		/* invoke callback */
-		if(uart->parent.rx_indicate != RT_NULL)
-		{
-		    rt_size_t length;
-		    if (uart->read_index > uart->save_index)
+        /* invoke callback */
+        if(uart->parent.rx_indicate != RT_NULL)
+        {
+            rt_size_t length;
+            if (uart->read_index > uart->save_index)
                 length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
             else
                 length = uart->save_index - uart->read_index;
 
             uart->parent.rx_indicate(&uart->parent, length);
-		}
-	}
+        }
+    }
 
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* leave interrupt */
+    rt_interrupt_leave();
 
-	return;
+    return;
 }
 #endif
 
 #ifdef RT_USING_UART1
 void UART1_IRQHandler(void)
 {
-	rt_ubase_t level, iir;
+    rt_ubase_t level, iir;
     struct rt_uart_lpc* uart = &uart1_device;
 
-	/* enter interrupt */
-	rt_interrupt_enter();
+    /* enter interrupt */
+    rt_interrupt_enter();
 
     /* read IIR and clear it */
-	iir = uart->UART->IIR;
+    iir = uart->UART->IIR;
 
-	if (iir == UART_IIR_INTID_RDA)	    /* Receive Data Available */
-	{
-		/* Receive Data Available */
+    if (iir == UART_IIR_INTID_RDA)      /* Receive Data Available */
+    {
+        /* Receive Data Available */
         uart->rx_buffer[uart->save_index] = uart->UART->RBR;
 
         level = rt_hw_interrupt_disable();
-		uart->save_index ++;
+        uart->save_index ++;
         if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
             uart->save_index = 0;
         rt_hw_interrupt_enable(level);
 
-		/* invoke callback */
-		if(uart->parent.rx_indicate != RT_NULL)
-		{
-		    rt_size_t length;
-		    if (uart->read_index > uart->save_index)
+        /* invoke callback */
+        if(uart->parent.rx_indicate != RT_NULL)
+        {
+            rt_size_t length;
+            if (uart->read_index > uart->save_index)
                 length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
             else
                 length = uart->save_index - uart->read_index;
 
             uart->parent.rx_indicate(&uart->parent, length);
-		}
-	}
+        }
+    }
 
-	/* leave interrupt */
-	rt_interrupt_leave();
+    /* leave interrupt */
+    rt_interrupt_leave();
 
-	return;
+    return;
 }
 #endif
 
 static rt_err_t rt_uart_init (rt_device_t dev)
 {
-	struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
-	UART_CFG_Type UART_ConfigStruct;
+    struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
+    UART_CFG_Type UART_ConfigStruct;
 
 #ifdef RT_USING_UART0
-	if( uart->UART == LPC_UART0 )
+    if( uart->UART == LPC_UART0 )
     {
         /*
          * Initialize UART0 pin connect
@@ -184,170 +184,170 @@ static rt_err_t rt_uart_init (rt_device_t dev)
 #endif
 
 #ifdef RT_USING_UART2
-	if( uart->UART == LPC_UART2 )
+    if( uart->UART == LPC_UART2 )
     {
     }
 #endif
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
 {
     struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
 
-	RT_ASSERT(dev != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Enable the UART Interrupt */
-		NVIC_EnableIRQ( uart->UART_IRQn );
-	}
+    RT_ASSERT(dev != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* Enable the UART Interrupt */
+        NVIC_EnableIRQ( uart->UART_IRQn );
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_uart_close(rt_device_t dev)
 {
     struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
 
-	RT_ASSERT(dev != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Disable the UART Interrupt */
-		NVIC_DisableIRQ( uart->UART_IRQn );
-	}
+    RT_ASSERT(dev != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* Disable the UART Interrupt */
+        NVIC_DisableIRQ( uart->UART_IRQn );
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
-	RT_ASSERT(uart != RT_NULL);
+    rt_uint8_t* ptr;
+    struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
+    RT_ASSERT(uart != RT_NULL);
 
-	/* point to buffer */
-	ptr = (rt_uint8_t*) buffer;
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
+    /* point to buffer */
+    ptr = (rt_uint8_t*) buffer;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        while (size)
+        {
+            /* interrupt receive */
+            rt_base_t level;
 
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (uart->read_index != uart->save_index)
-			{
-				*ptr = uart->rx_buffer[uart->read_index];
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
+            if (uart->read_index != uart->save_index)
+            {
+                *ptr = uart->rx_buffer[uart->read_index];
 
-				uart->read_index ++;
-				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
-					uart->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
+                uart->read_index ++;
+                if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    uart->read_index = 0;
+            }
+            else
+            {
+                /* no data in rx buffer */
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
 
-			ptr ++;
-			size --;
-		}
+            ptr ++;
+            size --;
+        }
 
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
+        return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    }
 
-	return 0;
+    return 0;
 }
 
 static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
-	char *ptr;
-	ptr = (char*)buffer;
+    struct rt_uart_lpc *uart = (struct rt_uart_lpc*)dev;
+    char *ptr;
+    ptr = (char*)buffer;
 
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-			    while (!(uart->UART->LSR & UART_LSR_THRE));
+    if (dev->flag & RT_DEVICE_FLAG_STREAM)
+    {
+        /* stream mode */
+        while (size)
+        {
+            if (*ptr == '\n')
+            {
+                while (!(uart->UART->LSR & UART_LSR_THRE));
                 UART_SendByte( uart->UART,'\r');
-			}
+            }
 
-			while (!(uart->UART->LSR & UART_LSR_THRE));
-			UART_SendByte( uart->UART,*ptr);
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
+            while (!(uart->UART->LSR & UART_LSR_THRE));
+            UART_SendByte( uart->UART,*ptr);
+            ptr ++;
+            size --;
+        }
+    }
+    else
+    {
         UART_Send( uart->UART, (uint8_t *)buffer, size, BLOCKING);
     }
 
-	return (rt_size_t) ptr - (rt_size_t) buffer;
+    return (rt_size_t) ptr - (rt_size_t) buffer;
 }
 
 void rt_hw_uart_init(void)
 {
-	struct rt_uart_lpc* uart;
+    struct rt_uart_lpc* uart;
 
 #ifdef RT_USING_UART0
-	/* get uart device */
-	uart = &uart0_device;
-	uart0_device.UART = LPC_UART0;
-	uart0_device.UART_IRQn = UART0_IRQn;
+    /* get uart device */
+    uart = &uart0_device;
+    uart0_device.UART = LPC_UART0;
+    uart0_device.UART_IRQn = UART0_IRQn;
 
-	/* device initialization */
-	uart->parent.type = RT_Device_Class_Char;
-	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-	uart->read_index = uart->save_index = 0;
+    /* device initialization */
+    uart->parent.type = RT_Device_Class_Char;
+    rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+    uart->read_index = uart->save_index = 0;
 
-	/* device interface */
-	uart->parent.init 	    = rt_uart_init;
-	uart->parent.open 	    = rt_uart_open;
-	uart->parent.close      = rt_uart_close;
-	uart->parent.read 	    = rt_uart_read;
-	uart->parent.write      = rt_uart_write;
-	uart->parent.control    = RT_NULL;
-	uart->parent.user_data  = RT_NULL;
+    /* device interface */
+    uart->parent.init       = rt_uart_init;
+    uart->parent.open       = rt_uart_open;
+    uart->parent.close      = rt_uart_close;
+    uart->parent.read       = rt_uart_read;
+    uart->parent.write      = rt_uart_write;
+    uart->parent.control    = RT_NULL;
+    uart->parent.user_data  = RT_NULL;
 
-	rt_device_register(&uart->parent,
-		"uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
+    rt_device_register(&uart->parent,
+        "uart0", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
 #endif
 
 #ifdef RT_USING_UART1
-	/* get uart device */
-	uart = &uart1_device;
-	uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1;
-	uart1_device.UART_IRQn = UART1_IRQn;
+    /* get uart device */
+    uart = &uart1_device;
+    uart1_device.UART = (LPC_UART_TypeDef *)LPC_UART1;
+    uart1_device.UART_IRQn = UART1_IRQn;
 
-	/* device initialization */
-	uart->parent.type = RT_Device_Class_Char;
-	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-	uart->read_index = uart->save_index = 0;
+    /* device initialization */
+    uart->parent.type = RT_Device_Class_Char;
+    rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+    uart->read_index = uart->save_index = 0;
 
-	/* device interface */
-	uart->parent.init 	    = rt_uart_init;
-	uart->parent.open 	    = rt_uart_open;
-	uart->parent.close      = rt_uart_close;
-	uart->parent.read 	    = rt_uart_read;
-	uart->parent.write      = rt_uart_write;
-	uart->parent.control    = RT_NULL;
-	uart->parent.user_data  = RT_NULL;
+    /* device interface */
+    uart->parent.init       = rt_uart_init;
+    uart->parent.open       = rt_uart_open;
+    uart->parent.close      = rt_uart_close;
+    uart->parent.read       = rt_uart_read;
+    uart->parent.write      = rt_uart_write;
+    uart->parent.control    = RT_NULL;
+    uart->parent.user_data  = RT_NULL;
 
-	rt_device_register(&uart->parent,
-		"uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
+    rt_device_register(&uart->parent,
+        "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_STREAM | RT_DEVICE_FLAG_INT_RX);
 #endif
 }