Merge pull request #1 from RT-Thread/master

sync rtt

3 files changed, 248 insertions, 270 deletions

diff --git a/bsp/ls1bdev/drivers/board.c b/bsp/ls1bdev/drivers/board.c
index 307d8d28b0..e25c6267d5 100644
--- a/bsp/ls1bdev/drivers/board.c
+++ b/bsp/ls1bdev/drivers/board.c
@@ -11,6 +11,7 @@
  * Date           Author       Notes
  * 2010-06-25     Bernard      first version
  * 2011-08-08     lgnq         modified for Loongson LS1B
+ * 2019-12-04     Jiaxun Yang  Adapt new MIPS generic code
  */
 
 #include <rtthread.h>
@@ -20,6 +21,14 @@
 #include "uart.h"
 #include "ls1b.h"
 
+#ifdef RT_USING_RTGUI
+#include <rtgui/rtgui.h>
+rt_device_t dc;
+extern void rt_hw_dc_init(void);
+#endif
+
+extern unsigned char __bss_end;
+
 /**
  * @addtogroup Loongson LS1B
  */
@@ -27,85 +36,53 @@
 /*@{*/
 
 /**
- * This is the timer interrupt service routine.
- */
-void rt_hw_timer_handler(void)
-{
-	unsigned int count;
-
-	count = read_c0_compare();
-	write_c0_compare(count);
-	write_c0_count(0);
-
-	/* increase a OS tick */
-	rt_tick_increase();
-}
-
-/**
- * This function will initial OS timer
- */
-void rt_hw_timer_init(void)
-{
-	write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND);
-	write_c0_count(0);
-}
-
-/**
  * This function will initial sam7s64 board.
  */
 void rt_hw_board_init(void)
 {
-#ifdef RT_USING_UART
-	/* init hardware UART device */
-	rt_hw_uart_init();
+    /* init hardware interrupt */
+    rt_hw_exception_init();
+    
+    /* init hardware interrupt */
+    rt_hw_interrupt_init();
+    
+#ifdef RT_USING_HEAP
+    rt_system_heap_init((void*)&__bss_end, (void*)RT_HW_HEAP_END);
+#endif
+
+#ifdef RT_USING_SERIAL
+    /* init hardware UART device */
+    rt_hw_uart_init();
 #endif
 
 #ifdef RT_USING_CONSOLE
-	/* set console device */
-	rt_console_set_device("uart0");
+    /* set console device */
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
 #endif
+    /* init operating system timer */
+    rt_hw_timer_init();
 
-	/* init operating system timer */
-	rt_hw_timer_init();
+#ifdef RT_USING_FPU
+    /* init hardware fpu */
+    rt_hw_fpu_init();
+#endif
 
-	rt_kprintf("current sr: 0x%08x\n", read_c0_status());
-}
+#ifdef RT_USING_RTGUI
+    rt_device_t dc;
 
-#define __raw_out_put(unr) \
-	while (*ptr) \
-	{ \
-		if (*ptr == '\n') \
-		{ \
-			/* FIFO status, contain valid data */ \
-			while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
-			/* write data */ \
-			UART_DAT(UART##unr##_BASE) = '\r'; \
-		} \
-		/* FIFO status, contain valid data */ \
-		while (!(UART_LSR(UART##unr##_BASE) & (UARTLSR_TE | UARTLSR_TFE))); \
-		/* write data */ \
-		UART_DAT(UART##unr##_BASE) = *ptr; \
-		ptr ++; \
-	}
+    /* init Display Controller */
+    rt_hw_dc_init();
 
-/* UART line status register value */
-#define UARTLSR_ERROR	(1 << 7)
-#define UARTLSR_TE		(1 << 6)
-#define UARTLSR_TFE		(1 << 5)
-#define UARTLSR_BI		(1 << 4)
-#define UARTLSR_FE		(1 << 3)
-#define UARTLSR_PE		(1 << 2)
-#define UARTLSR_OE		(1 << 1)
-#define UARTLSR_DR		(1 << 0)
-void rt_hw_console_output(const char *ptr)
-{
-#if defined(RT_USING_UART0)
-    __raw_out_put(0);
-#elif defined(RT_USING_UART1)
-    __raw_out_put(1);
-#elif defined(RT_USING_UART3)
-    __raw_out_put(3);
+    /* find Display Controller device */
+    dc = rt_device_find("dc");
+
+    /* set Display Controller device as rtgui graphic driver */
+    rtgui_graphic_set_device(dc);
 #endif
-}
 
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+}
 /*@}*/
diff --git a/bsp/ls1bdev/drivers/uart.c b/bsp/ls1bdev/drivers/uart.c
index c4ddb581e6..e920d33057 100644
--- a/bsp/ls1bdev/drivers/uart.c
+++ b/bsp/ls1bdev/drivers/uart.c
@@ -23,257 +23,257 @@
 
 /*@{*/
 
-#if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
+#if defined(RT_USING_DEVICE)
 
 struct rt_uart_ls1b
 {
-	struct rt_device parent;
+    struct rt_device parent;
 
-	rt_uint32_t hw_base;
-	rt_uint32_t irq;
+    rt_uint32_t hw_base;
+    rt_uint32_t irq;
 
-	/* buffer for reception */
-	rt_uint8_t read_index, save_index;
-	rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
+    /* buffer for reception */
+    rt_uint8_t read_index, save_index;
+    rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE];
 }uart_device;
 
 static void rt_uart_irqhandler(int irqno, void *param)
 {
-	rt_ubase_t level;
-	rt_uint8_t isr;
-	struct rt_uart_ls1b *uart = &uart_device;
+    rt_ubase_t level;
+    rt_uint8_t isr;
+    struct rt_uart_ls1b *uart = &uart_device;
 
-	/* read interrupt status and clear it */
-	isr = UART_IIR(uart->hw_base);
-	isr = (isr >> 1) & 0x3;
+    /* read interrupt status and clear it */
+    isr = UART_IIR(uart->hw_base);
+    isr = (isr >> 1) & 0x3;
 
-	/* receive data available */
-	if (isr & 0x02)
-	{
-		/* Receive Data Available */
-		while (UART_LSR(uart->hw_base) & UARTLSR_DR)
-		{
-			uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
+    /* receive data available */
+    if (isr & 0x02)
+    {
+        /* Receive Data Available */
+        while (UART_LSR(uart->hw_base) & UARTLSR_DR)
+        {
+            uart->rx_buffer[uart->save_index] = UART_DAT(uart->hw_base);
 
-			level = rt_hw_interrupt_disable();
-			uart->save_index ++;
-			if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
-				uart->save_index = 0;
-			rt_hw_interrupt_enable(level);
-		}
+            level = rt_hw_interrupt_disable();
+            uart->save_index ++;
+            if (uart->save_index >= RT_UART_RX_BUFFER_SIZE)
+                uart->save_index = 0;
+            rt_hw_interrupt_enable(level);
+        }
 
-		/* invoke callback */
-		if (uart->parent.rx_indicate != RT_NULL)
-		{
-			rt_size_t length;
-			if (uart->read_index > uart->save_index)
-				length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
-			else
-				length = uart->save_index - uart->read_index;
+        /* invoke callback */
+        if (uart->parent.rx_indicate != RT_NULL)
+        {
+            rt_size_t length;
+            if (uart->read_index > uart->save_index)
+                length = RT_UART_RX_BUFFER_SIZE - uart->read_index + uart->save_index;
+            else
+                length = uart->save_index - uart->read_index;
 
-			uart->parent.rx_indicate(&uart->parent, length);
-		}
-	}
+            uart->parent.rx_indicate(&uart->parent, length);
+        }
+    }
 
-	return;
+    return;
 }
 
 static rt_err_t rt_uart_init(rt_device_t dev)
 {
-	rt_uint32_t baud_div;
-	struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+    rt_uint32_t baud_div;
+    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
 
-	RT_ASSERT(uart != RT_NULL);
+    RT_ASSERT(uart != RT_NULL);
 
 #if 0
-	/* init UART Hardware */
-	UART_IER(uart->hw_base) = 0; /* clear interrupt */
-	UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
+    /* init UART Hardware */
+    UART_IER(uart->hw_base) = 0; /* clear interrupt */
+    UART_FCR(uart->hw_base) = 0x60; /* reset UART Rx/Tx */
 
-	/* enable UART clock */
-	/* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
-	UART_LCR(uart->hw_base) = 0x3;
+    /* enable UART clock */
+    /* set databits, stopbits and parity. (8-bit data, 1 stopbit, no parity) */
+    UART_LCR(uart->hw_base) = 0x3;
 
-	/* set baudrate */
-	baud_div = DEV_CLK / 16 / UART_BAUDRATE;
-	UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
+    /* set baudrate */
+    baud_div = DEV_CLK / 16 / UART_BAUDRATE;
+    UART_LCR(uart->hw_base) |= UARTLCR_DLAB;
 
-	UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
-	UART_LSB(uart->hw_base) = baud_div & 0xff;
+    UART_MSB(uart->hw_base) = (baud_div >> 8) & 0xff;
+    UART_LSB(uart->hw_base) = baud_div & 0xff;
 
-	UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
+    UART_LCR(uart->hw_base) &= ~UARTLCR_DLAB;
 
-	/* Enable UART unit, enable and clear FIFO */
-	UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
+    /* Enable UART unit, enable and clear FIFO */
+    UART_FCR(uart->hw_base) = UARTFCR_UUE | UARTFCR_FE | UARTFCR_TFLS | UARTFCR_RFLS;
 #endif
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_uart_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
 
-	RT_ASSERT(uart != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Enable the UART Interrupt */
-		UART_IER(uart->hw_base) |= UARTIER_IRXE;
+    RT_ASSERT(uart != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* Enable the UART Interrupt */
+        UART_IER(uart->hw_base) |= UARTIER_IRXE;
 
-		/* install interrupt */
-		rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
-		rt_hw_interrupt_umask(uart->irq);
-	}
-	return RT_EOK;
+        /* install interrupt */
+        rt_hw_interrupt_install(uart->irq, rt_uart_irqhandler, RT_NULL, "UART");
+        rt_hw_interrupt_umask(uart->irq);
+    }
+    return RT_EOK;
 }
 
 static rt_err_t rt_uart_close(rt_device_t dev)
 {
-	struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
 
-	RT_ASSERT(uart != RT_NULL);
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* Disable the UART Interrupt */
-		UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
-	}
+    RT_ASSERT(uart != RT_NULL);
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* Disable the UART Interrupt */
+        UART_IER(uart->hw_base) &= ~(UARTIER_IRXE);
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_uart_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size)
 {
-	rt_uint8_t *ptr;
-	struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+    rt_uint8_t *ptr;
+    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
 
-	RT_ASSERT(uart != RT_NULL);
+    RT_ASSERT(uart != RT_NULL);
 
-	/* point to buffer */
-	ptr = (rt_uint8_t *)buffer;
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
+    /* point to buffer */
+    ptr = (rt_uint8_t *)buffer;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        while (size)
+        {
+            /* interrupt receive */
+            rt_base_t level;
 
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (uart->read_index != uart->save_index)
-			{
-				*ptr = uart->rx_buffer[uart->read_index];
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
+            if (uart->read_index != uart->save_index)
+            {
+                *ptr = uart->rx_buffer[uart->read_index];
 
-				uart->read_index ++;
-				if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
-					uart->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
+                uart->read_index ++;
+                if (uart->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    uart->read_index = 0;
+            }
+            else
+            {
+                /* no data in rx buffer */
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
 
-			ptr ++;
-			size --;
-		}
+            ptr ++;
+            size --;
+        }
 
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
+        return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    }
 
-	return 0;
+    return 0;
 }
 
 static rt_size_t rt_uart_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size)
 {
-	char *ptr;
-	struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
+    char *ptr;
+    struct rt_uart_ls1b *uart = (struct rt_uart_ls1b *)dev;
 
-	RT_ASSERT(uart != RT_NULL);
+    RT_ASSERT(uart != RT_NULL);
 
-	ptr = (char *)buffer;
+    ptr = (char *)buffer;
 
-	if (dev->flag & RT_DEVICE_FLAG_STREAM)
-	{
-		/* stream mode */
-		while (size)
-		{
-			if (*ptr == '\n')
-			{
-				/* FIFO status, contain valid data */
-				while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
-				/* write data */
-				UART_DAT(uart->hw_base) = '\r';
-			}
+    if (dev->flag & RT_DEVICE_FLAG_STREAM)
+    {
+        /* stream mode */
+        while (size)
+        {
+            if (*ptr == '\n')
+            {
+                /* FIFO status, contain valid data */
+                while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
+                /* write data */
+                UART_DAT(uart->hw_base) = '\r';
+            }
 
-			/* FIFO status, contain valid data */
-			while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
-			/* write data */
-			UART_DAT(uart->hw_base) = *ptr;
+            /* FIFO status, contain valid data */
+            while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
+            /* write data */
+            UART_DAT(uart->hw_base) = *ptr;
 
-			ptr ++;
-			size --;
-		}
-	}
-	else
-	{
-		while (size != 0)
-		{
-			/* FIFO status, contain valid data */
-			while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
+            ptr ++;
+            size --;
+        }
+    }
+    else
+    {
+        while (size != 0)
+        {
+            /* FIFO status, contain valid data */
+            while (!(UART_LSR(uart->hw_base) & (UARTLSR_TE | UARTLSR_TFE)));
 
-			/* write data */
-			UART_DAT(uart->hw_base) = *ptr;
+            /* write data */
+            UART_DAT(uart->hw_base) = *ptr;
 
-			ptr++;
-			size--;
-		}
-	}
+            ptr++;
+            size--;
+        }
+    }
 
-	return (rt_size_t)ptr - (rt_size_t)buffer;
+    return (rt_size_t)ptr - (rt_size_t)buffer;
 }
 
 void rt_hw_uart_init(void)
 {
-	struct rt_uart_ls1b *uart;
+    struct rt_uart_ls1b *uart;
 
-	/* get uart device */
-	uart = &uart_device;
+    /* get uart device */
+    uart = &uart_device;
 
-	/* device initialization */
-	uart->parent.type = RT_Device_Class_Char;
-	rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
-	uart->read_index = uart->save_index = 0;
+    /* device initialization */
+    uart->parent.type = RT_Device_Class_Char;
+    rt_memset(uart->rx_buffer, 0, sizeof(uart->rx_buffer));
+    uart->read_index = uart->save_index = 0;
 
 #if defined(RT_USING_UART0)
-	uart->hw_base = UART0_BASE;
-	uart->irq = LS1B_UART0_IRQ;
+    uart->hw_base = UART0_BASE;
+    uart->irq = LS1B_UART0_IRQ;
 #elif defined(RT_USING_UART1)
-	uart->hw_base = UART1_BASE;
-	uart->irq = LS1B_UART1_IRQ;
+    uart->hw_base = UART1_BASE;
+    uart->irq = LS1B_UART1_IRQ;
 #elif defined(RT_USING_UART3)
-	uart->hw_base = UART3_BASE;
-	uart->irq = LS1B_UART3_IRQ;
+    uart->hw_base = UART3_BASE;
+    uart->irq = LS1B_UART3_IRQ;
 #endif
 
-	/* device interface */
-	uart->parent.init       = rt_uart_init;
-	uart->parent.open       = rt_uart_open;
-	uart->parent.close      = rt_uart_close;
-	uart->parent.read       = rt_uart_read;
-	uart->parent.write      = rt_uart_write;
-	uart->parent.control    = RT_NULL;
-	uart->parent.user_data  = RT_NULL;
+    /* device interface */
+    uart->parent.init       = rt_uart_init;
+    uart->parent.open       = rt_uart_open;
+    uart->parent.close      = rt_uart_close;
+    uart->parent.read       = rt_uart_read;
+    uart->parent.write      = rt_uart_write;
+    uart->parent.control    = RT_NULL;
+    uart->parent.user_data  = RT_NULL;
 
-	rt_device_register(&uart->parent, "uart0",
-						RT_DEVICE_FLAG_RDWR |
-						RT_DEVICE_FLAG_STREAM |
-						RT_DEVICE_FLAG_INT_RX);
+    rt_device_register(&uart->parent, "uart0",
+                        RT_DEVICE_FLAG_RDWR |
+                        RT_DEVICE_FLAG_STREAM |
+                        RT_DEVICE_FLAG_INT_RX);
 }
 #endif /* end of UART */
 
diff --git a/bsp/ls1bdev/drivers/uart.h b/bsp/ls1bdev/drivers/uart.h
index 2aae7e9ef5..bec660b740 100644
--- a/bsp/ls1bdev/drivers/uart.h
+++ b/bsp/ls1bdev/drivers/uart.h
@@ -16,8 +16,9 @@
 #define __UART_H__
 
 #include "ls1b.h"
+#include <rthw.h>
 
-#define UART0_BASE			0xBFE40000
+#define UART0_BASE		    0xBFE40000
 #define UART0_1_BASE		0xBFE41000
 #define UART0_2_BASE		0xBFE42000
 #define UART0_3_BASE		0xBFE43000
@@ -31,43 +32,43 @@
 #define UART5_BASE			0xBFE7C000
 
 /* UART registers */
-#define UART_DAT(base)		__REG8(base + 0x00)
-#define UART_IER(base)		__REG8(base + 0x01)
-#define UART_IIR(base)		__REG8(base + 0x02)
-#define UART_FCR(base)		__REG8(base + 0x02)
-#define UART_LCR(base)		__REG8(base + 0x03)
-#define UART_MCR(base)		__REG8(base + 0x04)
-#define UART_LSR(base)		__REG8(base + 0x05)
-#define UART_MSR(base)		__REG8(base + 0x06)
+#define UART_DAT(base)		HWREG8(base + 0x00)
+#define UART_IER(base)		HWREG8(base + 0x01)
+#define UART_IIR(base)		HWREG8(base + 0x02)
+#define UART_FCR(base)		HWREG8(base + 0x02)
+#define UART_LCR(base)		HWREG8(base + 0x03)
+#define UART_MCR(base)		HWREG8(base + 0x04)
+#define UART_LSR(base)		HWREG8(base + 0x05)
+#define UART_MSR(base)		HWREG8(base + 0x06)
 
-#define UART_LSB(base)		__REG8(base + 0x00)
-#define UART_MSB(base)		__REG8(base + 0x01)
+#define UART_LSB(base)		HWREG8(base + 0x00)
+#define UART_MSB(base)		HWREG8(base + 0x01)
 
 /* UART0 registers */
-#define UART0_DAT			__REG8(UART0_BASE + 0x00)
-#define UART0_IER			__REG8(UART0_BASE + 0x01)
-#define UART0_IIR			__REG8(UART0_BASE + 0x02)
-#define UART0_FCR			__REG8(UART0_BASE + 0x02)
-#define UART0_LCR			__REG8(UART0_BASE + 0x03)
-#define UART0_MCR			__REG8(UART0_BASE + 0x04)
-#define UART0_LSR			__REG8(UART0_BASE + 0x05)
-#define UART0_MSR			__REG8(UART0_BASE + 0x06)
+#define UART0_DAT			HWREG8(UART0_BASE + 0x00)
+#define UART0_IER			HWREG8(UART0_BASE + 0x01)
+#define UART0_IIR			HWREG8(UART0_BASE + 0x02)
+#define UART0_FCR			HWREG8(UART0_BASE + 0x02)
+#define UART0_LCR			HWREG8(UART0_BASE + 0x03)
+#define UART0_MCR			HWREG8(UART0_BASE + 0x04)
+#define UART0_LSR			HWREG8(UART0_BASE + 0x05)
+#define UART0_MSR			HWREG8(UART0_BASE + 0x06)
 
-#define UART0_LSB			__REG8(UART0_BASE + 0x00)
-#define UART0_MSB			__REG8(UART0_BASE + 0x01)
+#define UART0_LSB			HWREG8(UART0_BASE + 0x00)
+#define UART0_MSB			HWREG8(UART0_BASE + 0x01)
 
 /* UART1 registers */
-#define UART1_DAT			__REG8(UART1_BASE + 0x00)
-#define UART1_IER			__REG8(UART1_BASE + 0x01)
-#define UART1_IIR			__REG8(UART1_BASE + 0x02)
-#define UART1_FCR			__REG8(UART1_BASE + 0x02)
-#define UART1_LCR			__REG8(UART1_BASE + 0x03)
-#define UART1_MCR			__REG8(UART1_BASE + 0x04)
-#define UART1_LSR			__REG8(UART1_BASE + 0x05)
-#define UART1_MSR			__REG8(UART1_BASE + 0x06)
+#define UART1_DAT			HWREG8(UART1_BASE + 0x00)
+#define UART1_IER			HWREG8(UART1_BASE + 0x01)
+#define UART1_IIR			HWREG8(UART1_BASE + 0x02)
+#define UART1_FCR			HWREG8(UART1_BASE + 0x02)
+#define UART1_LCR			HWREG8(UART1_BASE + 0x03)
+#define UART1_MCR			HWREG8(UART1_BASE + 0x04)
+#define UART1_LSR			HWREG8(UART1_BASE + 0x05)
+#define UART1_MSR			HWREG8(UART1_BASE + 0x06)
 
-#define UART1_LSB			__REG8(UART1_BASE + 0x00)
-#define UART1_MSB			__REG8(UART1_BASE + 0x01)
+#define UART1_LSB			HWREG8(UART1_BASE + 0x00)
+#define UART1_MSB			HWREG8(UART1_BASE + 0x01)
 
 /* UART interrupt enable register value */
 #define UARTIER_IME		(1 << 3)