[bsp][w60x] 更新驱动，添加加解密及配网功能，增强稳定性。

1. 新增 crypto, onchip_Flash, soft_i2c 驱动
2. 新增 oneshot 配网功能
3. 完善 I2C, UART, SPI, WIFI 等基本驱动
4. 更新 Kconfig 配置，用户交互更加友好
5. 屏蔽 末尾 80 内存，无法作为栈使用。

21 files changed, 1553 insertions, 246 deletions

diff --git a/bsp/w60x/drivers/Kconfig b/bsp/w60x/drivers/Kconfig
index 047ce06cbf..e38a312b65 100644
--- a/bsp/w60x/drivers/Kconfig
+++ b/bsp/w60x/drivers/Kconfig
@@ -4,30 +4,43 @@ config BSP_USING_WM_LIBRARIES
     select PKG_USING_WM_LIBRARIES
     default y
 
-
 menu "W60x Device config"
     choice
-        prompt "Device type"
-        default SOC_W600-A8xx
+        prompt "SOC type"
+        default SOC_W600_A8xx
         config SOC_W600_A8xx
             bool "W600-A8xx"
         config SOC_W601_A8xx
             bool "W601-A8xx"
     endchoice
+
+    choice
+        prompt "Board type"
+        if SOC_W600_A8xx
+            config W600_EV_BOARD
+                bool "W600_EV BOARD"
+        endif
+        if SOC_W601_A8xx
+            config W601_IOT_BOARD
+                bool "W601 IoT Board"
+        endif
+        config W60X_CUSTOM_BOARD
+            bool "Custom Board"
+    endchoice
 endmenu
 
-menu "Hardware Drivers Config"
-    menu "On-chip Peripheral Drivers"
-        menuconfig BSP_USING_UART
-            bool "Using UART"
-            select RT_USING_SERIAL
-            default y
+menu "On-chip Peripheral Drivers"
+    menuconfig BSP_USING_UART
+        bool "Using UART"
+        select RT_USING_SERIAL
+        default y
 
-            if BSP_USING_UART
-                config BSP_USING_UART0
-                bool "Enabel UART 0"
-                default y
+        if BSP_USING_UART
+            config BSP_USING_UART0
+            bool "Enabel UART 0"
+            default y
 
+            if W600_EV_BOARD || W60X_CUSTOM_BOARD
                 config BSP_USING_UART1
                     bool "Enabel UART 1"
                     default n
@@ -36,14 +49,10 @@ menu "Hardware Drivers Config"
                     config WM_UART1_BAUDRATE
                         int "UART1 baudrate"
                         default 115200
-                    config WM_UART1_RX_PIN
-                        int "UART1 RX pin number"
-                        default 31
-                    config WM_UART1_TX_PIN
-                        int "UART1 TX pin number"
-                        default 32
                 endif
+            endif
 
+            if W601_IOT_BOARD || W60X_CUSTOM_BOARD
                 config BSP_USING_UART2
                     bool "Enabel UART 2"
                     default n
@@ -52,192 +61,208 @@ menu "Hardware Drivers Config"
                     config WM_UART2_BAUDRATE
                         int "UART2 baudrate"
                         default 115200
-                    config WM_UART2_RX_PIN
-                        int "UART2 RX pin number"
-                        default 13
-                    config WM_UART2_TX_PIN
-                        int "UART2 TX pin number"
-                        default 14
                 endif
             endif
-
-        config BSP_USING_PIN
-            bool "Using PIN"
-            select RT_USING_PIN
-            default y
-
-        config BSP_USING_WIFI
-            bool "Using WIFI"
-            select RT_USING_WIFI
-            select RT_USING_LWIP
-            default y
-
-        if SOC_W601_A8xx
-            menuconfig BSP_USING_ADC
-                bool "Enable ADC"
-                select RT_USING_ADC
-                default n
-
-            if BSP_USING_ADC
-                config USING_CPU_TEMP
-                    bool "Enable CPU Temperature"
-                config USING_ADC_CH1
-                    bool "Enable ADC Channel 1"
-                config USING_ADC_CH2
-                    bool "Enable ADC Channel 2"
-                config USING_ADC_CH3
-                    bool "Enable ADC Channel 3"
-                config USING_ADC_CH4
-                    bool "Enable ADC Channel 4"
-                config USING_ADC_CH5
-                    bool "Enable ADC Channel 5"
-                config USING_ADC_CH6
-                    bool "Enable ADC Channel 6"
-                config USING_ADC_CH7
-                    bool "Enable ADC Channel 7"
-                config USING_ADC_CH8
-                    bool "Enable ADC Channel 8"
-            endif
         endif
 
-        menuconfig BSP_USING_HWTIMER
-            bool "Enable HWTIMER"
-            select RT_USING_HWTIMER
-            default n
+    config BSP_USING_PIN
+        bool "Using PIN"
+        select RT_USING_PIN
+        default y
 
-        if  BSP_USING_HWTIMER
-            config USING_HW_TIMER1
-                bool "Enable hw timer1"
-            config USING_HW_TIMER2
-                bool "Enable hw timer2"
-            config USING_HW_TIMER3
-                bool "Enable hw timer3"
-            config USING_HW_TIMER4
-                bool "Enable hw timer4"
-            config USING_HW_TIMER5
-                bool "Enable hw timer5"
-        endif
+    config BSP_USING_WIFI
+        bool "Using WIFI"
+        select RT_USING_WIFI
+        select RT_USING_LWIP
+        select PKG_USING_NETUTILS
+        select PKG_NETUTILS_NTP
+        select RT_USING_RTC
+        select RT_USING_SOFT_RTC if !BSP_USING_RTC
+        default y
 
-        menuconfig BSP_USING_PWM
-            bool "Enable PWM"
-            select RT_USING_PWM
+    if SOC_W601_A8xx
+        menuconfig BSP_USING_ADC
+            bool "Enable ADC"
+            select RT_USING_ADC
             default n
 
-        if BSP_USING_PWM
-            config USING_PWM_CH1
-                bool "Enable pwm channel 1"
-                default n
-                if USING_PWM_CH1
-                    config WM_PWM_CH1_PIN
-                    int "wm pwm channel 1 pin number"
-                    default 23
-                endif
-            config USING_PWM_CH2
-                bool "Enable pwm channel 2"
-                default n
-                if USING_PWM_CH2
-                    config WM_PWM_CH2_PIN
-                    int "wm pwm channel 2 pin number"
-                    default 22
-                endif
-            config USING_PWM_CH3
-                bool "Enable pwm channel 3"
-                default n
-                if USING_PWM_CH3
-                    config WM_PWM_CH3_PIN
-                    int "wm pwm channel 3 pin number"
-                    default 21
-                endif
-            config USING_PWM_CH4
-                bool "Enable pwm channel 4"
-                default n
-                if USING_PWM_CH4
-                    config WM_PWM_CH4_PIN
-                    int "wm pwm channel 4 pin number"
-                    default 20
-                endif
-            config USING_PWM_CH5
-                bool "Enable pwm channel 5"
-                default n
-                if USING_PWM_CH5
-                    config WM_PWM_CH5_PIN
-                    int "wm pwm channel 5 pin number"
-                    default 19
-                endif
+        if BSP_USING_ADC
+            config USING_CPU_TEMP
+                bool "Enable CPU Temperature"
+            config USING_ADC_CH1
+                bool "Enable ADC Channel 1"
+            config USING_ADC_CH2
+                bool "Enable ADC Channel 2"
+            config USING_ADC_CH3
+                bool "Enable ADC Channel 3"
+            config USING_ADC_CH4
+                bool "Enable ADC Channel 4"
+            config USING_ADC_CH5
+                bool "Enable ADC Channel 5"
+            config USING_ADC_CH6
+                bool "Enable ADC Channel 6"
+            config USING_ADC_CH7
+                bool "Enable ADC Channel 7"
+            config USING_ADC_CH8
+                bool "Enable ADC Channel 8"
         endif
+    endif
 
-        menuconfig BSP_USING_I2C
-            bool "Enable I2C"
-            select RT_USING_I2C
-            default n
+    menuconfig BSP_USING_HWTIMER
+        bool "Enable HWTIMER"
+        select RT_USING_HWTIMER
+        default n
 
-        if BSP_USING_I2C
-            config WM_HW_I2C_FREQ
-                int "wm hardware I2C frequency(HZ)"
-                default 200000
-            config WM_I2C_DAT_PIN
-                int "wm I2C DAT pin number"
-                default 19
-            config WM_I2C_SCL_PIN
-                int "wm I2C SCL pin number"
-                default 18
-        endif
+    if  BSP_USING_HWTIMER
+        config USING_HW_TIMER1
+            bool "Enable hw timer1"
+        config USING_HW_TIMER2
+            bool "Enable hw timer2"
+        config USING_HW_TIMER3
+            bool "Enable hw timer3"
+        config USING_HW_TIMER4
+            bool "Enable hw timer4"
+        config USING_HW_TIMER5
+            bool "Enable hw timer5"
+    endif
 
-        menuconfig BSP_USING_SPI
-            bool "Enable SPI"
-            select RT_USING_SPI
+    menuconfig BSP_USING_PWM
+        bool "Enable PWM"
+        select RT_USING_PWM
+        default n
+
+    if BSP_USING_PWM
+        config USING_PWM_CH1
+            bool "Enable pwm channel 1"
             default n
-        
-        if BSP_USING_SPI
-            config WM_SPI_CK_PIN
-                int "wm SPI CK pin number"
-                default 21
-            config WM_SPI_DO_PIN
-                int "wm SPI DO pin number"
+            if USING_PWM_CH1
+                config WM_PWM_CH1_PIN
+                int "wm pwm channel 1 pin number"
                 default 23
-            config WM_SPI_DI_PIN
-                int "wm SPI DI pin number"
+            endif
+        config USING_PWM_CH2
+            bool "Enable pwm channel 2"
+            default n
+            if USING_PWM_CH2
+                config WM_PWM_CH2_PIN
+                int "wm pwm channel 2 pin number"
                 default 22
-        endif
-
-        config BSP_USING_WDT
-            bool "Enable WDT"
-            select RT_USING_WDT
+            endif
+        config USING_PWM_CH3
+            bool "Enable pwm channel 3"
             default n
-
-        menuconfig BSP_USING_RTC
-            bool "Enable RTC"
-            select RT_USING_RTC
+            if USING_PWM_CH3
+                config WM_PWM_CH3_PIN
+                int "wm pwm channel 3 pin number"
+                default 21
+            endif
+        config USING_PWM_CH4
+            bool "Enable pwm channel 4"
             default n
+            if USING_PWM_CH4
+                config WM_PWM_CH4_PIN
+                int "wm pwm channel 4 pin number"
+                default 37
+            endif
+        config USING_PWM_CH5
+            bool "Enable pwm channel 5"
+            default n
+            if USING_PWM_CH5
+                config WM_PWM_CH5_PIN
+                int "wm pwm channel 5 pin number"
+                default 19
+            endif
+    endif
+    
+    config BSP_USING_I2C
+        bool "Enable I2C"
+        select RT_USING_I2C
+        default n
+
+    if BSP_USING_I2C
+        config WM_HW_I2C_FREQ
+            int "wm hardware I2C frequency(HZ)"
+            default 200000
+    endif
 
-        if BSP_USING_RTC
-            config BSP_USING_ALARM
-                bool "Enable Alarm"
-                select RT_USING_ALARM
+    menuconfig BSP_USING_SOFT_I2C
+        bool "Enable SOFT I2C"
+        select RT_USING_I2C
+        select RT_USING_I2C_BITOPS
+        default n
+
+        if BSP_USING_SOFT_I2C
+            config BSP_USING_SOFT_I2C1
+                bool "Enabel SOFT I2C1"
                 default n
+        endif   
+
+        if BSP_USING_SOFT_I2C
+            config BSP_USING_SOFT_I2C2
+                bool "Enabel SOFT I2C2"
+                default n      
         endif
 
-        config BSP_USING_STANDBY
-            bool "Enable standby"
-            default n
+    menuconfig BSP_USING_SPI
+        bool "Enable SPI"
+        select RT_USING_SPI
+        default n
 
-    endmenu
+    if BSP_USING_SPI
+        config WM_SPI_BUS_NAME
+            string "Set SPI BUS name"
+            default "spi0"
+    endif
 
-    menu "Offboard Peripheral Drivers"
-        menuconfig BSP_USING_FLASH
-            bool "Enable Flash"
-            select RT_USING_SFUD
-            select BSP_USING_SPI
+    config BSP_USING_WDT
+        bool "Enable WDT"
+        select RT_USING_WDT
+        default n
+
+    menuconfig BSP_USING_RTC
+        bool "Enable RTC"
+        select RT_USING_RTC
+        default n
+
+    if BSP_USING_RTC
+        config BSP_USING_ALARM
+            bool "Enable Alarm"
+            select RT_USING_ALARM
             default n
+    endif
 
-        if BSP_USING_FLASH
-            config SPI_Flash_BUS_NAME
-                string "SPI BUS Name"
-                default "spi0"
+    config BSP_USING_CRYPTO
+        bool "Enable Hardware Crypto"
+        select RT_USING_HWCRYPTO
+        select RT_HWCRYPTO_USING_AES
+        select RT_HWCRYPTO_USING_AES_ECB
+        select RT_HWCRYPTO_USING_AES_CBC
+        select RT_HWCRYPTO_USING_MD5
+        select RT_HWCRYPTO_USING_SHA1
+        select RT_HWCRYPTO_USING_RNG
+        select RT_HWCRYPTO_USING_CRC
+        select RT_HWCRYPTO_USING_CRC_07
+        select RT_HWCRYPTO_USING_CRC_8005
+        select RT_HWCRYPTO_USING_CRC_1021
+        select RT_HWCRYPTO_USING_CRC_04C11DB7
+        select RT_HWCRYPTO_USING_BIGNUM
+        select RT_HWCRYPTO_USING_BIGNUM_EXPTMOD
+        default n
 
-            config SPI_Flash_CS_PIN
-                int "SPI Flash CS pin number"
-                default 20
-        endif
-    endmenu
+    config BSP_USING_STANDBY
+        bool "Enable standby"
+        default n
+endmenu
+
+menu "External Libraries"
+    config WM_USING_ONESHOT
+        bool "Using winner micro Oneshot"
+        select RT_USING_WIFI
+        default y
+
+    if WM_USING_ONESHOT
+        config WM_USING_ONESHOT_DEMO
+            bool "Using Oneshot Demo"
+            default y
+    endif
 endmenu
diff --git a/bsp/w60x/drivers/SConscript b/bsp/w60x/drivers/SConscript
index 133f94d561..ef076132c3 100644
--- a/bsp/w60x/drivers/SConscript
+++ b/bsp/w60x/drivers/SConscript
@@ -7,6 +7,7 @@ objs = []
 src = Split('''
         board.c
         drv_uart.c
+        drv_flash.c
         pin_map.c
         ''')
 
@@ -19,17 +20,11 @@ if GetDepend(['BSP_USING_WIFI']):
 if GetDepend('BSP_USING_PIN'):
     src += ['drv_pin.c']
 
-if GetDepend('BSP_USING_SDIO'):
-    src += ['drv_sdio.c']
-
-if GetDepend('BSP_USING_CAN'):
-    src += ['drv_can.c']
-
 if GetDepend('BSP_USING_HWTIMER'):
     src += ['drv_hw_timer.c']
 
-if GetDepend('BSP_USING_CPUTIME'):
-    src += ['drv_cputime.c']
+if GetDepend('BSP_USING_SOFT_I2C'):
+    src += ['drv_soft_i2c.c']
 
 if GetDepend('BSP_USING_I2C'):
     src += ['drv_i2c.c']
@@ -37,12 +32,6 @@ if GetDepend('BSP_USING_I2C'):
 if GetDepend('BSP_USING_SPI'):
     src += ['drv_spi.c']
 
-if GetDepend(['BSP_USING_FLASH']):
-    src += ['drv_spiflash.c']
-
-if GetDepend('BSP_USING_LCD'):
-    src += ['drv_lcd.c']
-
 if GetDepend('BSP_USING_PWM'):
     src += ['drv_pwm.c']
 
@@ -55,6 +44,9 @@ if GetDepend('BSP_USING_WDT'):
 if GetDepend('BSP_USING_STANDBY'):
     src += ['drv_standby.c']
 
+if GetDepend('BSP_USING_CRYPTO'):
+    src += ['drv_crypto.c']
+
 CPPPATH = [cwd]
 
 group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
diff --git a/bsp/w60x/drivers/board.c b/bsp/w60x/drivers/board.c
index eedf113fa2..c104733d5b 100644
--- a/bsp/w60x/drivers/board.c
+++ b/bsp/w60x/drivers/board.c
@@ -133,6 +133,21 @@ static void _idle_hook_callback(void)
 #endif
 }
 
+static void _thread_inited_hook(rt_thread_t thread)
+{
+    rt_uint32_t stack_size, stk_start;
+
+    stack_size = (rt_uint32_t)thread->stack_size;
+    stk_start = (rt_uint32_t)thread->stack_addr;
+
+    if ((stk_start + stack_size) >= TASK_STACK_USING_MEM_UPPER_RANGE)
+    {
+        rt_kprintf("thread[%s] stack only between 0x%08x and 0x%08x, please use rt_create_thread()!!\n",
+                   thread->name, TASK_STACK_USING_MEM_LOWER_RANGE, TASK_STACK_USING_MEM_UPPER_RANGE);
+    }
+    RT_ASSERT((stk_start + stack_size) < TASK_STACK_USING_MEM_UPPER_RANGE);
+}
+
 void wm_sys_clk_config(void)
 {
     tls_sys_clk sysclk;
@@ -188,6 +203,14 @@ void rt_hw_board_init(void)
 
     NVIC_SystemLPConfig(NVIC_LP_SLEEPDEEP, ENABLE);
     rt_thread_idle_sethook(_idle_hook_callback);
+    rt_thread_inited_sethook(_thread_inited_hook);
+}
+
+#include <wm_watchdog.h>
+void rt_hw_cpu_reset(void)
+{
+    extern void tls_sys_reset(void);
+    tls_sys_reset();
 }
 
 #ifdef RT_USING_FINSH
diff --git a/bsp/w60x/drivers/board.h b/bsp/w60x/drivers/board.h
index 65442c0a3b..d35391ebf8 100644
--- a/bsp/w60x/drivers/board.h
+++ b/bsp/w60x/drivers/board.h
@@ -22,7 +22,10 @@ extern int __bss_end__;
 #define HEAP_BEGIN    (&__bss_end__)
 #endif
 
-#define HEAP_END           (0x20038000UL)
+#define HEAP_END           (0x20028000UL)
+
+#define HARDWARE_VERSION 0x0003U
+#include "pin_config.h"
 
 void rt_hw_board_init(void);
 
diff --git a/bsp/w60x/drivers/drv_crypto.c b/bsp/w60x/drivers/drv_crypto.c
new file mode 100644
index 0000000000..4335e42b50
--- /dev/null
+++ b/bsp/w60x/drivers/drv_crypto.c
@@ -0,0 +1,738 @@
+/*
+ * Copyright (c) 2019 Winner Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-05-17     tyx          1st version
+ */
+
+#include <rtthread.h>
+#include <rtdevice.h>
+#include <stdlib.h>
+#include <string.h>
+#include "drv_crypto.h"
+#include "wm_crypto_hard.h"
+
+// #define WM_HWCRYPTO_NOT_LOCK
+// #define WM_HWCRYPTO_NOT_ALIGN_CHECK
+
+extern u32 tls_crypto_crc_update_adv(u32 crc_val, CRYPTO_CRC_TYPE type, u8 mode, const unsigned char *in, u32 len);
+extern int tls_crypto_des_encrypt_decrypt_adv(unsigned char *key, unsigned char *IV, const unsigned char *in, unsigned char *out, u32 len, CRYPTO_MODE cbc, CRYPTO_WAY dec);
+extern int tls_crypto_3des_encrypt_decrypt_adv(unsigned char *key, unsigned char *IV, const unsigned char *in, unsigned char *out, u32 len, CRYPTO_MODE cbc, CRYPTO_WAY dec);
+extern int tls_crypto_aes_encrypt_decrypt_adv(unsigned char *key, unsigned char *IV, const unsigned char *in, unsigned char *out, u32 len, CRYPTO_MODE cbc, CRYPTO_WAY dec);
+extern int tls_crypto_rc4_adv(unsigned char *key, u32 keylen, const unsigned char *in, unsigned char *out, u32 len);
+
+struct wm_hwcrypto_device
+{
+    struct rt_hwcrypto_device dev;
+    struct rt_mutex mutex;
+};
+
+struct hash_ctx_des
+{
+    psDigestContext_t contex;
+};
+
+static rt_uint32_t _rng_rand(struct hwcrypto_rng *ctx)
+{
+    rt_uint32_t rand_num;
+    struct wm_hwcrypto_device *_hwcrypto = (struct wm_hwcrypto_device *)ctx->parent.device;
+
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_take(&_hwcrypto->mutex, RT_WAITING_FOREVER);
+#endif
+    tls_crypto_random_init((u32)rt_tick_get(), CRYPTO_RNG_SWITCH_32);
+    tls_crypto_random_bytes((unsigned char *)&rand_num, sizeof(rand_num));
+    tls_crypto_random_stop();
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_release(&_hwcrypto->mutex);
+#endif
+
+    return rand_num;
+}
+
+static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length)
+{
+    rt_uint32_t crc_result;
+    CRYPTO_CRC_TYPE type;
+    u8 mode = 0;
+    struct wm_hwcrypto_device *_hwcrypto = (struct wm_hwcrypto_device *)ctx->parent.device;
+    unsigned char align_flag = 0;
+
+#if !defined(WM_HWCRYPTO_NOT_ALIGN_CHECK)
+    if (((rt_uint32_t)in % 4) != 0)
+    {
+        void *temp;
+        temp = rt_malloc(length);
+        if (temp)
+        {
+            memcpy(temp, in, length);
+            in = temp;
+            align_flag = 1;
+        }
+        else
+        {
+            return 0;
+        }
+    }
+#endif
+
+    switch (ctx->crc_cfg.poly)
+    {
+    case 0x04C11DB7:
+        type = CRYPTO_CRC_TYPE_32;
+        break;
+    case 0x00001021:
+        type = CRYPTO_CRC_TYPE_16_CCITT;
+        break;
+    case 0x00008005:
+        type = CRYPTO_CRC_TYPE_16_MODBUS;
+        break;
+    case 0x00000007:
+    case 0x00000207:
+        type = CRYPTO_CRC_TYPE_8;
+        break;
+    default:
+        return 0;
+    }
+
+    mode |= ctx->crc_cfg.flags & CRC_FLAG_REFOUT ? OUTPUT_REFLECT : 0;
+    mode |= ctx->crc_cfg.flags & CRC_FLAG_REFIN ? INPUT_REFLECT : 0;
+
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_take(&_hwcrypto->mutex, RT_WAITING_FOREVER);
+#endif
+    crc_result = tls_crypto_crc_update_adv(ctx->crc_cfg.last_val, type, mode, in, length);
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_release(&_hwcrypto->mutex);
+#endif
+
+#if !defined(WM_HWCRYPTO_NOT_ALIGN_CHECK)
+    if (align_flag)
+    {
+        rt_free((rt_uint8_t *)in);
+    }
+#endif
+
+    ctx->crc_cfg.last_val = crc_result;
+    return crc_result ^ 0x00 ^ ctx->crc_cfg.xorout;
+}
+
+static rt_err_t _hash_update(struct hwcrypto_hash *ctx, const rt_uint8_t *in, rt_size_t length)
+{
+    rt_err_t err = RT_EOK;
+    struct wm_hwcrypto_device *_hwcrypto = (struct wm_hwcrypto_device *)ctx->parent.device;
+    unsigned char align_flag = 0;
+
+#if !defined(WM_HWCRYPTO_NOT_ALIGN_CHECK)
+    if (((rt_uint32_t)in % 4) != 0)
+    {
+        void *temp;
+        temp = rt_malloc(length);
+        if (temp)
+        {
+            memcpy(temp, in, length);
+            in = temp;
+            align_flag = 1;
+        }
+        else
+        {
+            return -RT_ENOMEM;
+        }
+    }
+#endif
+
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_take(&_hwcrypto->mutex, RT_WAITING_FOREVER);
+#endif
+    switch (ctx->parent.type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+    case HWCRYPTO_TYPE_MD5:
+        tls_crypto_md5_update(&((struct hash_ctx_des *)(ctx->parent.contex))->contex, in, length);
+        break;
+    case HWCRYPTO_TYPE_SHA1:
+        tls_crypto_sha1_update(&((struct hash_ctx_des *)(ctx->parent.contex))->contex, in, length);
+        break;
+    default:
+        err = -RT_ERROR;
+        break;
+    }
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_release(&_hwcrypto->mutex);
+#endif
+
+#if !defined(WM_HWCRYPTO_NOT_ALIGN_CHECK)
+    if (align_flag)
+    {
+        rt_free((rt_uint8_t *)in);
+    }
+#endif
+
+    return err;
+}
+
+static rt_err_t _hash_finish(struct hwcrypto_hash *ctx, rt_uint8_t *out, rt_size_t length)
+{
+    rt_err_t err = RT_EOK;
+    struct wm_hwcrypto_device *_hwcrypto = (struct wm_hwcrypto_device *)ctx->parent.device;
+
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_take(&_hwcrypto->mutex, RT_WAITING_FOREVER);
+#endif
+    switch (ctx->parent.type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+    case HWCRYPTO_TYPE_MD5:
+        tls_crypto_md5_final(&((struct hash_ctx_des *)(ctx->parent.contex))->contex, out);
+        break;
+    case HWCRYPTO_TYPE_SHA1:
+        tls_crypto_sha1_final(&((struct hash_ctx_des *)(ctx->parent.contex))->contex, out);
+        break;
+    default:
+        err = -RT_ERROR;
+        break;
+    }
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_release(&_hwcrypto->mutex);
+#endif
+
+    return err;
+}
+
+static rt_err_t _des_crypt(struct hwcrypto_symmetric *symmetric_ctx, struct hwcrypto_symmetric_info *symmetric_info)
+{
+    CRYPTO_WAY mode;
+    CRYPTO_MODE cbc;
+    struct wm_hwcrypto_device *_hwcrypto = (struct wm_hwcrypto_device *)symmetric_ctx->parent.device;
+    unsigned char *in, *out, align_flag = 0;
+
+    if ((symmetric_ctx->key_bitlen >> 3) != 8
+            || (symmetric_info->length % 8) != 0)
+    {
+        return -RT_EINVAL;
+    }
+
+    in = (unsigned char *)symmetric_info->in;
+    out = (unsigned char *)symmetric_info->out;
+
+#if !defined(WM_HWCRYPTO_NOT_ALIGN_CHECK)
+    if (((rt_uint32_t)in % 4) != 0 || ((rt_uint32_t)out % 4) != 0)
+    {
+        in = rt_malloc(symmetric_info->length);
+        if (in)
+        {
+            memcpy(in, symmetric_info->in, symmetric_info->length);
+            out = in;
+            align_flag = 1;
+        }
+        else
+        {
+            return -RT_ENOMEM;
+        }
+    }
+#endif
+
+    mode = symmetric_info->mode == HWCRYPTO_MODE_ENCRYPT ? CRYPTO_WAY_ENCRYPT : CRYPTO_WAY_DECRYPT;
+
+    switch (symmetric_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
+    {
+    case HWCRYPTO_TYPE_DES_ECB:
+        cbc = CRYPTO_MODE_ECB;
+        break;
+    case HWCRYPTO_TYPE_DES_CBC:
+        cbc = CRYPTO_MODE_CBC;
+        break;
+    default :
+        return -RT_ERROR;
+    }
+
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_take(&_hwcrypto->mutex, RT_WAITING_FOREVER);
+#endif
+    tls_crypto_des_encrypt_decrypt_adv(symmetric_ctx->key, symmetric_ctx->iv,
+                                       symmetric_info->in, symmetric_info->out,
+                                       symmetric_info->length, cbc, mode);
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_release(&_hwcrypto->mutex);
+#endif
+
+#if !defined(WM_HWCRYPTO_NOT_ALIGN_CHECK)
+    if (align_flag)
+    {
+        memcpy(symmetric_info->out, out, symmetric_info->length);
+        rt_free(in);
+    }
+#endif
+
+    return RT_EOK;
+}
+
+static rt_err_t _des3_crypt(struct hwcrypto_symmetric *symmetric_ctx, struct hwcrypto_symmetric_info *symmetric_info)
+{
+    CRYPTO_WAY mode;
+    CRYPTO_MODE cbc;
+    struct wm_hwcrypto_device *_hwcrypto = (struct wm_hwcrypto_device *)symmetric_ctx->parent.device;
+    unsigned char *in, *out, align_flag = 0;
+
+    if ((symmetric_ctx->key_bitlen >> 3) != 24
+            || (symmetric_info->length % 8) != 0)
+    {
+        return -RT_EINVAL;
+    }
+
+    in = (unsigned char *)symmetric_info->in;
+    out = (unsigned char *)symmetric_info->out;
+
+#if !defined(WM_HWCRYPTO_NOT_ALIGN_CHECK)
+    if (((rt_uint32_t)in % 4) != 0 || ((rt_uint32_t)out % 4) != 0)
+    {
+        in = rt_malloc(symmetric_info->length);
+        if (in)
+        {
+            memcpy(in, symmetric_info->in, symmetric_info->length);
+            out = in;
+            align_flag = 1;
+        }
+        else
+        {
+            return -RT_ENOMEM;
+        }
+    }
+#endif
+
+    mode = symmetric_info->mode == HWCRYPTO_MODE_ENCRYPT ? CRYPTO_WAY_ENCRYPT : CRYPTO_WAY_DECRYPT;
+
+    switch (symmetric_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
+    {
+    case HWCRYPTO_TYPE_3DES_ECB:
+        cbc = CRYPTO_MODE_ECB;
+        break;
+    case HWCRYPTO_TYPE_3DES_CBC:
+        cbc = CRYPTO_MODE_CBC;
+        break;
+    default :
+        return -RT_ERROR;
+    }
+
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_take(&_hwcrypto->mutex, RT_WAITING_FOREVER);
+#endif
+    tls_crypto_3des_encrypt_decrypt_adv(symmetric_ctx->key, symmetric_ctx->iv,
+                                        symmetric_info->in, symmetric_info->out,
+                                        symmetric_info->length, cbc, mode);
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_release(&_hwcrypto->mutex);
+#endif
+
+#if !defined(WM_HWCRYPTO_NOT_ALIGN_CHECK)
+    if (align_flag)
+    {
+        memcpy(symmetric_info->out, out, symmetric_info->length);
+        rt_free(in);
+    }
+#endif
+
+    return RT_EOK;
+}
+
+static rt_err_t _rc4_crypt(struct hwcrypto_symmetric *symmetric_ctx, struct hwcrypto_symmetric_info *symmetric_info)
+{
+    struct wm_hwcrypto_device *_hwcrypto = (struct wm_hwcrypto_device *)symmetric_ctx->parent.device;
+    unsigned char *in, *out, align_flag = 0;
+
+    if ((symmetric_ctx->key_bitlen >> 3) != 16)
+    {
+        return -RT_EINVAL;
+    }
+
+    in = (unsigned char *)symmetric_info->in;
+    out = (unsigned char *)symmetric_info->out;
+
+#if !defined(WM_HWCRYPTO_NOT_ALIGN_CHECK)
+    if (((rt_uint32_t)in % 4) != 0 || ((rt_uint32_t)out % 4) != 0)
+    {
+        in = rt_malloc(symmetric_info->length);
+        if (in)
+        {
+            memcpy(in, symmetric_info->in, symmetric_info->length);
+            out = in;
+            align_flag = 1;
+        }
+        else
+        {
+            return -RT_ENOMEM;
+        }
+    }
+#endif
+
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_take(&_hwcrypto->mutex, RT_WAITING_FOREVER);
+#endif
+    tls_crypto_rc4_adv(symmetric_ctx->key, symmetric_ctx->key_bitlen >> 3,
+                       (unsigned char *)symmetric_info->in,
+                       symmetric_info->out,
+                       symmetric_info->length);
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_release(&_hwcrypto->mutex);
+#endif
+
+#if !defined(WM_HWCRYPTO_NOT_ALIGN_CHECK)
+    if (align_flag)
+    {
+        memcpy(symmetric_info->out, out, symmetric_info->length);
+        rt_free(in);
+    }
+#endif
+
+    return RT_EOK;
+}
+
+static rt_err_t _aes_crypt(struct hwcrypto_symmetric *symmetric_ctx, struct hwcrypto_symmetric_info *symmetric_info)
+{
+    CRYPTO_WAY mode;
+    CRYPTO_MODE cbc;
+    struct wm_hwcrypto_device *_hwcrypto = (struct wm_hwcrypto_device *)symmetric_ctx->parent.device;
+    unsigned char *in, *out, align_flag = 0;
+
+    if ((symmetric_ctx->key_bitlen >> 3) != 16
+            || (symmetric_info->length % 16) != 0)
+    {
+        return -RT_EINVAL;
+    }
+
+    in = (unsigned char *)symmetric_info->in;
+    out = (unsigned char *)symmetric_info->out;
+
+#if !defined(WM_HWCRYPTO_NOT_ALIGN_CHECK)
+    if (((rt_uint32_t)in % 4) != 0 || ((rt_uint32_t)out % 4) != 0)
+    {
+        in = rt_malloc(symmetric_info->length);
+        if (in)
+        {
+            memcpy(in, symmetric_info->in, symmetric_info->length);
+            out = in;
+            align_flag = 1;
+        }
+        else
+        {
+            return -RT_ENOMEM;
+        }
+    }
+#endif
+
+    mode = symmetric_info->mode == HWCRYPTO_MODE_ENCRYPT ? CRYPTO_WAY_ENCRYPT : CRYPTO_WAY_DECRYPT;
+
+    switch (symmetric_ctx->parent.type & (HWCRYPTO_MAIN_TYPE_MASK | HWCRYPTO_SUB_TYPE_MASK))
+    {
+    case HWCRYPTO_TYPE_AES_ECB:
+        cbc = CRYPTO_MODE_ECB;
+        break;
+    case HWCRYPTO_TYPE_AES_CBC:
+        cbc = CRYPTO_MODE_CBC;
+        break;
+    case HWCRYPTO_TYPE_AES_CTR:
+        cbc = CRYPTO_MODE_CTR;
+        break;
+    default :
+        return -RT_ERROR;
+    }
+
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_take(&_hwcrypto->mutex, RT_WAITING_FOREVER);
+#endif
+    tls_crypto_aes_encrypt_decrypt_adv(symmetric_ctx->key, symmetric_ctx->iv,
+                                       in, out, symmetric_info->length, cbc, mode);
+#if !defined(WM_HWCRYPTO_NOT_LOCK)
+    rt_mutex_release(&_hwcrypto->mutex);
+#endif
+
+#if !defined(WM_HWCRYPTO_NOT_ALIGN_CHECK)
+    if (align_flag)
+    {
+        memcpy(symmetric_info->out, out, symmetric_info->length);
+        rt_free(in);
+    }
+#endif
+
+    return RT_EOK;
+}
+
+/**< a = b ^ c (mod d) */
+static rt_err_t _bignum_exptmod(struct hwcrypto_bignum *bignum_ctx,
+                    struct hw_bignum_mpi *x,
+                    const struct hw_bignum_mpi *a,
+                    const struct hw_bignum_mpi *b,
+                    const struct hw_bignum_mpi *c)
+{
+	pstm_int pa, pb, pm, pres;
+    u32 * buff_a = NULL;
+	u32 * buff_b = NULL;
+	u32 * buff_m = NULL;
+	int err = -1;
+    void *buff;
+    int buff_len;
+
+    pstm_init(NULL, &pres);
+
+    buff_a = tls_mem_alloc(a->total);
+	if(buff_a == NULL)
+		goto out;
+	buff_b = tls_mem_alloc(b->total);
+	if(buff_b == NULL)
+		goto out;
+	buff_m = tls_mem_alloc(c->total);
+	if(buff_m == NULL)
+		goto out;
+
+    memset(buff_a, 0, a->total);
+    memset(buff_b, 0, b->total);
+    memset(buff_m, 0, c->total);
+
+    memcpy(buff_a, a->p, a->total);
+    memcpy(buff_b, b->p, b->total);
+    memcpy(buff_m, c->p, c->total);
+
+    pstm_reverse((unsigned char *)buff_a, a->total);
+	pstm_reverse((unsigned char *)buff_b, b->total);
+	pstm_reverse((unsigned char *)buff_m, c->total);
+
+//    *((volatile unsigned int *)0x40000710) = *((volatile unsigned int *)0x40000710) | (0x1 << 28);
+
+	if ((err = pstm_init_for_read_unsigned_bin(NULL, &pa, a->total)) != PS_SUCCESS){
+		goto out;
+	}
+	if ((err = pstm_read_unsigned_bin(&pa, (unsigned char *)buff_a, a->total)) != PS_SUCCESS) {
+		goto out;
+	}
+	if ((err = pstm_init_for_read_unsigned_bin(NULL, &pb, b->total)) != PS_SUCCESS){
+		goto out;
+	}
+	if ((err = pstm_read_unsigned_bin(&pb, (unsigned char *)buff_b, b->total)) != PS_SUCCESS) {
+		goto out;
+	}
+	if ((err = pstm_init_for_read_unsigned_bin(NULL, &pm, c->total)) != PS_SUCCESS){
+		goto out;
+	}
+	if ((err = pstm_read_unsigned_bin(&pm, (unsigned char *)buff_m, c->total)) != PS_SUCCESS) {
+		goto out;
+	}
+
+    tls_crypto_exptmod(&pa, &pb, &pm, &pres);
+    buff_len = pstm_unsigned_bin_size(&pres);
+    buff = rt_malloc(buff_len);
+    pstm_to_unsigned_bin_nr(NULL, &pres, buff);
+    x->sign = pres.sign;
+    x->p = buff;
+    x->total = buff_len;
+
+out:
+    if(buff_a)
+		tls_mem_free(buff_a);
+	if(buff_b)
+		tls_mem_free(buff_b);
+	if(buff_m)
+		tls_mem_free(buff_m);
+
+	pstm_clear(&pa);
+	pstm_clear(&pb);
+	pstm_clear(&pm);
+	pstm_clear(&pres);
+
+    if (a->sign < 0)
+    {
+        rt_kprintf("a->sign < 0\n");
+    }
+
+    return err == PS_SUCCESS ? RT_EOK : -RT_ERROR;
+}
+
+static const struct hwcrypto_symmetric_ops aes_ops =
+{
+    .crypt = _aes_crypt,
+};
+
+static const struct hwcrypto_symmetric_ops rc4_ops =
+{
+    .crypt = _rc4_crypt,
+};
+
+static const struct hwcrypto_symmetric_ops des_ops =
+{
+    .crypt = _des_crypt,
+};
+
+static const struct hwcrypto_symmetric_ops des3_ops =
+{
+    .crypt = _des3_crypt,
+};
+
+static const struct hwcrypto_hash_ops hash_ops =
+{
+    .update = _hash_update,
+    .finish = _hash_finish,
+};
+
+static const struct hwcrypto_rng_ops rng_ops =
+{
+    .update = _rng_rand,
+};
+
+static const struct hwcrypto_crc_ops crc_ops =
+{
+    .update = _crc_update,
+};
+
+static const struct hwcrypto_bignum_ops bignum_ops = 
+{
+    .add = RT_NULL,
+    .sub = RT_NULL,
+    .mul = RT_NULL,
+    .mulmod = RT_NULL,
+    .exptmod = _bignum_exptmod,
+};
+
+static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx)
+{
+    rt_err_t res = RT_EOK;
+    void *contex;
+
+    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+    case HWCRYPTO_TYPE_AES :
+        ctx->contex = RT_NULL;
+        ((struct hwcrypto_symmetric *)ctx)->ops = &aes_ops;
+        break;
+    case HWCRYPTO_TYPE_RC4 :
+        ctx->contex = RT_NULL;
+        ((struct hwcrypto_symmetric *)ctx)->ops = &rc4_ops;
+        break;
+    case HWCRYPTO_TYPE_MD5:
+    case HWCRYPTO_TYPE_SHA1:
+        contex = rt_malloc(sizeof(struct hash_ctx_des));
+        if (contex == RT_NULL)
+        {
+            return -RT_ENOMEM;
+        }
+        memset(contex, 0, sizeof(struct hash_ctx_des));
+        ctx->contex = contex;
+        ((struct hwcrypto_hash *)ctx)->ops = &hash_ops;
+        if ((ctx->type & HWCRYPTO_MAIN_TYPE_MASK) == HWCRYPTO_TYPE_MD5)
+        {
+            tls_crypto_md5_init(&((struct hash_ctx_des *)contex)->contex);
+        }
+        else
+        {
+            tls_crypto_sha1_init(&((struct hash_ctx_des *)contex)->contex);
+        }
+        break;
+    case HWCRYPTO_TYPE_DES:
+        ctx->contex = RT_NULL;
+        ((struct hwcrypto_symmetric *)ctx)->ops = &des_ops;
+        break;
+    case HWCRYPTO_TYPE_3DES:
+        ctx->contex = RT_NULL;
+        ((struct hwcrypto_symmetric *)ctx)->ops = &des3_ops;
+        break;
+    case HWCRYPTO_TYPE_RNG:
+        ctx->contex = RT_NULL;
+        ((struct hwcrypto_rng *)ctx)->ops = &rng_ops;
+        ctx->contex = RT_NULL;
+        break;
+    case HWCRYPTO_TYPE_CRC:
+        ctx->contex = RT_NULL;
+        ((struct hwcrypto_crc *)ctx)->ops = &crc_ops;
+        break;
+    case HWCRYPTO_TYPE_BIGNUM:
+        ((struct hwcrypto_bignum *)ctx)->ops = &bignum_ops;
+        break;
+    default:
+        res = -RT_ERROR;
+        break;
+    }
+
+    return res;
+}
+
+static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx)
+{
+    rt_free(ctx->contex);
+}
+
+static rt_err_t _crypto_clone(struct rt_hwcrypto_ctx *des, const struct rt_hwcrypto_ctx *src)
+{
+    rt_err_t res = RT_EOK;
+
+    switch (src->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+    case HWCRYPTO_TYPE_AES:
+    case HWCRYPTO_TYPE_RC4:
+    case HWCRYPTO_TYPE_RNG:
+    case HWCRYPTO_TYPE_CRC:
+    case HWCRYPTO_TYPE_BIGNUM:
+        break;
+    case HWCRYPTO_TYPE_MD5:
+    case HWCRYPTO_TYPE_SHA1:
+        if (des->contex && src->contex)
+        {
+            rt_memcpy(des->contex, src->contex, sizeof(struct hash_ctx_des));
+        }
+        break;
+    default:
+        res = -RT_ERROR;
+        break;
+    }
+
+    return res;
+}
+
+static void _crypto_reset(struct rt_hwcrypto_ctx *ctx)
+{
+    switch (ctx->type & HWCRYPTO_MAIN_TYPE_MASK)
+    {
+    case HWCRYPTO_TYPE_AES:
+    case HWCRYPTO_TYPE_RC4:
+    case HWCRYPTO_TYPE_RNG:
+    case HWCRYPTO_TYPE_CRC:
+        break;
+    case HWCRYPTO_TYPE_MD5:
+        tls_crypto_md5_init(&((struct hash_ctx_des *)(ctx->contex))->contex);
+        break;
+    case HWCRYPTO_TYPE_SHA1:
+        tls_crypto_sha1_init(&((struct hash_ctx_des *)(ctx->contex))->contex);
+        break;
+    default:
+        break;
+    }
+}
+
+static const struct rt_hwcrypto_ops _ops =
+{
+    .create = _crypto_create,
+    .destroy = _crypto_destroy,
+    .copy = _crypto_clone,
+    .reset = _crypto_reset,
+};
+
+extern u8 *wpa_supplicant_get_mac(void);
+
+int wm_hw_crypto_device_init(void)
+{
+    static struct wm_hwcrypto_device _crypto_dev;
+
+    _crypto_dev.dev.ops = &_ops;
+    _crypto_dev.dev.id = 0;
+    rt_memcpy(&_crypto_dev.dev.id, wpa_supplicant_get_mac(), 
+        sizeof(_crypto_dev.dev.id) > 6 ?
+        6 : sizeof(_crypto_dev.dev.id));
+    _crypto_dev.dev.user_data = &_crypto_dev;
+
+    if (rt_hwcrypto_register(&_crypto_dev.dev,
+                             RT_HWCRYPTO_DEFAULT_NAME) != RT_EOK)
+    {
+        return -1;
+    }
+    rt_mutex_init(&_crypto_dev.mutex, RT_HWCRYPTO_DEFAULT_NAME, RT_IPC_FLAG_FIFO);
+    return 0;
+}
+INIT_DEVICE_EXPORT(wm_hw_crypto_device_init);
diff --git a/bsp/w60x/drivers/drv_spiflash.h b/bsp/w60x/drivers/drv_crypto.h
index 602635fa96..1fc5331284 100644
--- a/bsp/w60x/drivers/drv_spiflash.h
+++ b/bsp/w60x/drivers/drv_crypto.h
@@ -5,12 +5,12 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-11-12     fanwenl      1st version
+ * 2019-05-17     tyx          1st version
  */
 
-#ifndef __DRV_SPI_FLASH_H_
-#define __DRV_SPI_FLASH_H_
+#ifndef __DRV_CRYPTO_H__
+#define __DRV_CRYPTO_H__
 
-int wm_nor_flash_init(void);
+int wm_hw_crypto_device_init(void);
 
-#endif /* __DRV_SPI_FLASH_H_ */
\ No newline at end of file
+#endif /* __DRV_CRYPTO_H__ */
diff --git a/bsp/w60x/drivers/drv_flash.c b/bsp/w60x/drivers/drv_flash.c
new file mode 100644
index 0000000000..9ed0cba027
--- /dev/null
+++ b/bsp/w60x/drivers/drv_flash.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2019 Winner Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-04     tyx          1st version
+ */
+#include <rtthread.h>
+#include <rtdevice.h>
+#include "wm_flash_map.h"
+#include "wm_internal_flash.h"
+#include "drv_flash.h"
+
+#define FLASH_SECTOR (4096)
+
+#ifdef RT_USING_SPI
+static void *_spi0;
+#endif
+
+extern unsigned int flashtotalsize;
+
+rt_uint32_t wm_flash_total(void)
+{
+    rt_uint32_t total = 0x100000;
+
+    if (flashtotalsize == 0x200000)
+    {
+        total = 0x200000;
+    }
+
+    return total;
+}
+
+rt_uint32_t wm_flash_addr(void)
+{
+    return FLASH_BASE_ADDR;
+}
+
+rt_uint32_t wm_flash_blksize(void)
+{
+    return FLASH_SECTOR;
+}
+
+int wm_flash_read(long offset, void *data, int size)
+{
+    offset += FLASH_BASE_ADDR;
+#ifdef RT_USING_SPI
+    if (_spi0)
+    {
+        rt_spi_take_bus(_spi0);
+    }
+#endif
+    if (tls_fls_read(offset, data, size) != TLS_FLS_STATUS_OK)
+    {
+        size = -1;
+    }
+#ifdef RT_USING_SPI
+    if (_spi0)
+    {
+        rt_spi_release_bus(_spi0);
+    }
+#endif
+
+    return size;
+}
+
+int wm_flash_write(long offset, void *data, int size)
+{
+    offset += FLASH_BASE_ADDR;
+#ifdef RT_USING_SPI
+    if (_spi0)
+    {
+        rt_spi_take_bus(_spi0);
+    }
+#endif
+    if (tls_fls_write(offset, data, size) != TLS_FLS_STATUS_OK)
+    {
+        size = -1;
+    }
+#ifdef RT_USING_SPI
+    if (_spi0)
+    {
+        rt_spi_release_bus(_spi0);
+    }
+#endif
+
+    return size;
+}
+
+int wm_flash_erase(long offset, int size)
+{
+    int count, sector;
+
+    offset += FLASH_BASE_ADDR;
+    count = size / FLASH_SECTOR;
+    sector = offset / FLASH_SECTOR;
+#ifdef RT_USING_SPI
+    if (_spi0)
+    {
+        rt_spi_take_bus(_spi0);
+    }
+#endif
+    while (count)
+    {
+        if (tls_fls_erase(sector) != TLS_FLS_STATUS_OK)
+        {
+            size = -1;
+            break;
+        }
+        count--;
+        sector++;
+    }
+#ifdef RT_USING_SPI
+    if (_spi0)
+    {
+        rt_spi_release_bus(_spi0);
+    }
+#endif
+
+    return size;
+}
+
+int wm_flash_init(void)
+{
+#ifdef RT_USING_SPI
+    rt_err_t ret;
+
+    if (_spi0 != RT_NULL)
+    {
+        return 0;
+    }
+
+    _spi0 = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+    RT_ASSERT(_spi0 != RT_NULL);
+
+#ifdef WM_SPI_BUS_NAME
+    ret = rt_spi_bus_attach_device(_spi0, "flash", WM_SPI_BUS_NAME, RT_NULL);
+#else
+    ret = rt_spi_bus_attach_device(_spi0, "flash", "spi0", RT_NULL);
+#endif
+    if (ret != RT_EOK)
+    {
+        rt_free(_spi0);
+        _spi0 = RT_NULL;
+    }
+
+    if (_spi0)
+    {
+        ((struct rt_spi_device *)_spi0)->config.mode = RT_SPI_MODE_0;
+        ((struct rt_spi_device *)_spi0)->config.data_width = 8;
+        ((struct rt_spi_device *)_spi0)->config.max_hz = 20 * 1000 * 1000;
+    }
+#endif
+
+    return 0;
+}
diff --git a/bsp/w60x/drivers/drv_flash.h b/bsp/w60x/drivers/drv_flash.h
new file mode 100644
index 0000000000..94ee26f53b
--- /dev/null
+++ b/bsp/w60x/drivers/drv_flash.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2019 Winner Microelectronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-04-04     tyx          1st version
+ */
+
+#ifndef __DRV_FLASH_H__
+#define __DRV_FLASH_H__
+
+#include <rtthread.h>
+
+int wm_flash_read(long offset, void *data, int size);
+int wm_flash_write(long offset, void *data, int size);
+int wm_flash_erase(long offset, int size);
+int wm_flash_init(void);
+rt_uint32_t wm_flash_total(void);
+rt_uint32_t wm_flash_addr(void);
+rt_uint32_t wm_flash_blksize(void);
+
+#endif
diff --git a/bsp/w60x/drivers/drv_hw_timer.c b/bsp/w60x/drivers/drv_hw_timer.c
index 30ed4c04c4..d52c9c09a6 100644
--- a/bsp/w60x/drivers/drv_hw_timer.c
+++ b/bsp/w60x/drivers/drv_hw_timer.c
@@ -63,6 +63,11 @@ static void wm_timer_stop(rt_hwtimer_t *timer)
     tls_timer_stop(wm_timer->id);
 }
 
+static rt_uint32_t wm_timer_get(rt_hwtimer_t *timer)
+{
+    return 0;
+}
+
 static rt_err_t wm_timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
 {
     /* The frequency value is an immutable value. */
@@ -93,7 +98,7 @@ static const struct rt_hwtimer_ops _ops =
     wm_timer_init,
     wm_timer_start,
     wm_timer_stop,
-    RT_NULL,
+    wm_timer_get,
     wm_timer_ctrl,
 };
 
diff --git a/bsp/w60x/drivers/drv_i2c.c b/bsp/w60x/drivers/drv_i2c.c
index 688f23394d..29632bc815 100644
--- a/bsp/w60x/drivers/drv_i2c.c
+++ b/bsp/w60x/drivers/drv_i2c.c
@@ -10,6 +10,7 @@
 
 #include <rtdevice.h>
 #include <rtthread.h>
+#include "board.h"
 #include "wm_i2c.h"
 #include "wm_io.h"
 #include "wm_gpio_afsel.h"
@@ -167,7 +168,11 @@ int wm_hw_i2c_init(void)
     tls_i2c_init(WM_HW_I2C_FREQ);
 
     wm_i2c.parent.ops = &wm_i2c_ops;
+#ifdef WM_I2C_BUS_NAME
+    rt_i2c_bus_device_register(&wm_i2c.parent, WM_I2C_BUS_NAME);
+#else
     rt_i2c_bus_device_register(&wm_i2c.parent, "i2c");
+#endif
 
     return 0;
 }
diff --git a/bsp/w60x/drivers/drv_rtc.c b/bsp/w60x/drivers/drv_rtc.c
index 7affae875c..fbf6060691 100644
--- a/bsp/w60x/drivers/drv_rtc.c
+++ b/bsp/w60x/drivers/drv_rtc.c
@@ -20,6 +20,10 @@
 
 #ifdef BSP_USING_RTC
 
+#if defined(RT_USING_SOFT_RTC)
+#error "Please CANCEL the RT_USING_SOFT_RTC option. Make sure there is only one RTC device on the system."
+#endif
+
 static struct rt_rtc_device rtc_device;
 
 static time_t wm_get_timestamp(void)
diff --git a/bsp/w60x/drivers/drv_soft_i2c.c b/bsp/w60x/drivers/drv_soft_i2c.c
new file mode 100644
index 0000000000..a9365eaf07
--- /dev/null
+++ b/bsp/w60x/drivers/drv_soft_i2c.c
@@ -0,0 +1,243 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-22     balanceTWK   first version
+ */
+
+#include <board.h>
+#include "drv_soft_i2c.h"
+
+#include "wm_regs.h"
+#include "wm_gpio.h"
+#include "pin_map.h"
+
+#define DBG_SECTION_NAME     "soft_i2c"
+#define DBG_COLOR
+#define DBG_LEVEL           DBG_LOG
+#include <rtdbg.h>
+
+#ifdef BSP_USING_SOFT_I2C
+
+#if !defined(BSP_USING_SOFT_I2C1) && !defined(BSP_USING_SOFT_I2C2) && !defined(BSP_USING_SOFT_I2C3)
+#error "Please define at least one BSP_USING_SOFT_I2Cx"
+#endif
+
+static const struct w60x_soft_i2c_config soft_i2c_config[] =
+{
+#ifdef BSP_USING_SOFT_I2C1
+    I2C1_BUS_CONFIG,
+#endif
+#ifdef BSP_USING_SOFT_I2C2
+    I2C2_BUS_CONFIG,
+#endif
+#ifdef BSP_USING_SOFT_I2C3
+    I2C3_BUS_CONFIG,
+#endif
+};
+
+static struct w60x_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])];
+
+/**
+ * This function initializes the i2c pin.
+ *
+ * @param w60x i2c dirver class.
+ */
+static void w60x_i2c_gpio_init(struct w60x_i2c *i2c)
+{
+    struct w60x_soft_i2c_config* cfg = (struct w60x_soft_i2c_config*)i2c->ops.data;
+    rt_int16_t scl,sda;
+
+    scl = wm_get_pin(cfg->scl);
+    sda = wm_get_pin(cfg->sda);
+
+    tls_gpio_cfg((enum tls_io_name)scl, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH);
+    tls_gpio_cfg((enum tls_io_name)sda, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_PULLHIGH);
+
+    tls_gpio_write((enum tls_io_name)scl, 1);
+    tls_gpio_write((enum tls_io_name)sda, 1);
+}
+
+/**
+ * This function sets the sda pin.
+ *
+ * @param w60x config class.
+ * @param The sda pin state.
+ */
+static void w60x_set_sda(void *data, rt_int32_t state)
+{
+    struct w60x_soft_i2c_config* cfg = (struct w60x_soft_i2c_config*)data;
+    rt_int16_t sda;
+
+    sda = wm_get_pin(cfg->sda);
+
+    if (state)
+    {
+        tls_gpio_cfg((enum tls_io_name)sda, WM_GPIO_DIR_INPUT, WM_GPIO_ATTR_PULLHIGH);
+    }
+    else
+    {
+        tls_gpio_cfg((enum tls_io_name)sda, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_FLOATING);
+        tls_gpio_write((enum tls_io_name)sda, 0);
+    }
+}
+
+/**
+ * This function sets the scl pin.
+ *
+ * @param w60x config class.
+ * @param The scl pin state.
+ */
+static void w60x_set_scl(void *data, rt_int32_t state)
+{
+    struct w60x_soft_i2c_config* cfg = (struct w60x_soft_i2c_config*)data;
+    rt_int16_t scl;
+
+    scl = wm_get_pin(cfg->scl);
+
+    if (state)
+    {
+        tls_gpio_cfg((enum tls_io_name)scl, WM_GPIO_DIR_INPUT, WM_GPIO_ATTR_PULLHIGH);
+    }
+    else
+    {
+        tls_gpio_cfg((enum tls_io_name)scl, WM_GPIO_DIR_OUTPUT, WM_GPIO_ATTR_FLOATING);
+        tls_gpio_write((enum tls_io_name)scl, 0);
+    }
+}
+
+/**
+ * This function gets the sda pin state.
+ *
+ * @param The sda pin state.
+ */
+static rt_int32_t w60x_get_sda(void *data)
+{
+    struct w60x_soft_i2c_config* cfg = (struct w60x_soft_i2c_config*)data;
+    rt_int16_t sda;
+
+    sda = wm_get_pin(cfg->sda);
+
+    return tls_gpio_read((enum tls_io_name)sda);
+}
+
+/**
+ * This function gets the scl pin state.
+ *
+ * @param The scl pin state.
+ */
+static rt_int32_t w60x_get_scl(void *data)
+{
+    struct w60x_soft_i2c_config* cfg = (struct w60x_soft_i2c_config*)data;
+    rt_int16_t scl;
+
+    scl = wm_get_pin(cfg->scl);
+
+    return tls_gpio_read((enum tls_io_name)scl);
+}
+/**
+ * The time delay function.
+ *
+ * @param microseconds.
+ */
+static void w60x_udelay(rt_uint32_t us)
+{
+    rt_uint32_t ticks;
+    rt_uint32_t told, tnow, tcnt = 0;
+    rt_uint32_t reload = SysTick->LOAD;
+
+    ticks = us * reload / (1000000 / RT_TICK_PER_SECOND);
+    told = SysTick->VAL;
+    while (1)
+    {
+        tnow = SysTick->VAL;
+        if (tnow != told)
+        {
+            if (tnow < told)
+            {
+                tcnt += told - tnow;
+            }
+            else
+            {
+                tcnt += reload - tnow + told;
+            }
+            told = tnow;
+            if (tcnt >= ticks)
+            {
+                break;
+            }
+        }
+    }
+}
+
+static const struct rt_i2c_bit_ops w60x_bit_ops_default =
+{
+    .data     = RT_NULL,
+    .set_sda  = w60x_set_sda,
+    .set_scl  = w60x_set_scl,
+    .get_sda  = w60x_get_sda,
+    .get_scl  = w60x_get_scl,
+    .udelay   = w60x_udelay,
+    .delay_us = 1,
+    .timeout  = 100
+};
+
+/**
+ * if i2c is locked, this function will unlock it
+ *
+ * @param w60x config class
+ *
+ * @return RT_EOK indicates successful unlock.
+ */
+static rt_err_t w60x_i2c_bus_unlock(const struct w60x_soft_i2c_config *cfg)
+{
+    rt_int32_t i = 0;
+
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        while (i++ < 9)
+        {
+            rt_pin_write(cfg->scl, PIN_HIGH);
+            w60x_udelay(100);
+            rt_pin_write(cfg->scl, PIN_LOW);
+            w60x_udelay(100);
+        }
+    }
+    if (PIN_LOW == rt_pin_read(cfg->sda))
+    {
+        return -RT_ERROR;
+    }
+
+    return RT_EOK;
+}
+
+/* I2C initialization function */
+int rt_soft_i2c_init(void)
+{
+    rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct w60x_i2c);
+    rt_err_t result;
+
+    for (int i = 0; i < obj_num; i++)
+    {
+        i2c_obj[i].ops = w60x_bit_ops_default;
+        i2c_obj[i].ops.data = (void*)&soft_i2c_config[i];
+        i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops;
+        w60x_i2c_gpio_init(&i2c_obj[i]);
+        result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name);
+        RT_ASSERT(result == RT_EOK);
+        w60x_i2c_bus_unlock(&soft_i2c_config[i]);
+
+        LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
+        soft_i2c_config[i].bus_name, 
+        soft_i2c_config[i].scl, 
+        soft_i2c_config[i].sda);
+    }
+
+    return RT_EOK;
+}
+INIT_DEVICE_EXPORT(rt_soft_i2c_init);
+
+#endif /* BSP_USING_SOFT_I2C */
diff --git a/bsp/w60x/drivers/drv_soft_i2c.h b/bsp/w60x/drivers/drv_soft_i2c.h
new file mode 100644
index 0000000000..ee50abea71
--- /dev/null
+++ b/bsp/w60x/drivers/drv_soft_i2c.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-03-22     balanceTWK   first version
+ */
+
+#ifndef __DRV_SOFT_I2C__
+#define __DRV_SOFT_I2C__
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <rtdevice.h>
+
+/* w60x config class */
+struct w60x_soft_i2c_config
+{
+    rt_uint8_t scl;
+    rt_uint8_t sda;
+    const char *bus_name;
+};
+/* w60x i2c dirver class */
+struct w60x_i2c
+{
+    struct rt_i2c_bit_ops ops;
+    struct rt_i2c_bus_device i2c2_bus;
+};
+
+#ifdef BSP_USING_SOFT_I2C1
+#define I2C1_BUS_CONFIG                                  \
+    {                                                    \
+        .scl = SOFT_I2C1_SCL_PIN,                        \
+        .sda = SOFT_I2C1_SDA_PIN,                        \
+        .bus_name = "i2c1soft",                          \
+    }
+#endif
+
+#ifdef BSP_USING_SOFT_I2C2
+#define I2C2_BUS_CONFIG                                  \
+    {                                                    \
+        .scl = SOFT_I2C2_SCL_PIN,                        \
+        .sda = SOFT_I2C2_SDA_PIN,                        \
+        .bus_name = "i2c2soft",                          \
+    }
+#endif
+
+#ifdef BSP_USING_SOFT_I2C3
+#define I2C3_BUS_CONFIG                                  \
+    {                                                    \
+        .scl = SOFT_I2C3_SCL_PIN,                        \
+        .sda = SOFT_I2C3_SDA_PIN,                        \
+        .bus_name = "i2c3soft",                          \
+    }
+#endif
+
+int rt_hw_i2c_init(void);
+
+#endif
diff --git a/bsp/w60x/drivers/drv_spi.c b/bsp/w60x/drivers/drv_spi.c
index 88eef8b15a..ecec749278 100644
--- a/bsp/w60x/drivers/drv_spi.c
+++ b/bsp/w60x/drivers/drv_spi.c
@@ -10,6 +10,7 @@
 
 #include <rtthread.h>
 #include <rtdevice.h>
+#include "board.h"
 #include "wm_hostspi.h"
 #include "wm_spi_hal.h"
 #include "wm_io.h"
@@ -92,10 +93,13 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
 
     rt_int32_t length = 0;
     rt_int32_t remain_length = message->length;
+    rt_int32_t int_status;
+
+    tls_irq_disable(SPI0_INT);
 
     length = spi_fill_txfifo(&tls_transfer, remain_length);
     spi_set_sclk_length(length * 8, 0);
-    if (message->cs_take)
+    if (message->cs_take && cs)
     {
         tls_gpio_write((enum tls_io_name)cs->pin, 0);
     }
@@ -112,7 +116,7 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
         {
             while (spi_i2s_get_busy_status() == 1)
                 ;
-            if (message->cs_release)
+            if (message->cs_release && cs)
             {
                 tls_gpio_write((enum tls_io_name)cs->pin, 1);
             }
@@ -129,10 +133,15 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
 
     while (spi_i2s_get_busy_status() == 1)
         ;
-    if (message->cs_release)
+    if (message->cs_release && cs)
     {
         tls_gpio_write((enum tls_io_name)cs->pin, 1);
     }
+
+    int_status = spi_get_int_status();
+    spi_clear_int_status(int_status);
+    tls_irq_enable(SPI0_INT);
+
     return message->length - remain_length;
 }
 
@@ -193,7 +202,11 @@ int wm_hw_spi_bus_init(void)
     }
 
     wm_spi_bus.parent.user_data = &spi;
+#ifdef WM_SPI_BUS_NAME
+    rt_spi_bus_register(&wm_spi_bus, WM_SPI_BUS_NAME, &wm_spi_ops);
+#else
     rt_spi_bus_register(&wm_spi_bus, "spi0", &wm_spi_ops);
+#endif
 
     return RT_EOK;
 }
diff --git a/bsp/w60x/drivers/drv_spiflash.c b/bsp/w60x/drivers/drv_spiflash.c
deleted file mode 100644
index 51203ee894..0000000000
--- a/bsp/w60x/drivers/drv_spiflash.c
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2019 Winner Microelectronics Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2018-11-12     fanwenl      1st version
- */
-
-#include <rtthread.h>
-#include <rtdevice.h>
-
-#ifdef BSP_USING_FLASH
-#include "drv_spi.h"
-#include "string.h"
-#include "spi_flash.h"
-#include "spi_flash_sfud.h"
-
-int wm_nor_flash_init(void)
-{
-    rt_spi_flash_device_t spi_device;
-
-    wm_spi_bus_attach_device(SPI_Flash_BUS_NAME, "norspi", SPI_Flash_CS_PIN);
-    spi_device = rt_sfud_flash_probe("flash0", "norspi");
-    if (spi_device == RT_NULL)
-    {
-        return -RT_ERROR;
-    }
-    return 0;
-}
-INIT_DEVICE_EXPORT(wm_nor_flash_init);
-#endif
diff --git a/bsp/w60x/drivers/drv_uart.c b/bsp/w60x/drivers/drv_uart.c
index 9cf9472447..6a3c4c40fc 100644
--- a/bsp/w60x/drivers/drv_uart.c
+++ b/bsp/w60x/drivers/drv_uart.c
@@ -10,6 +10,7 @@
 
 #include <rtthread.h>
 #include <rtdevice.h>
+#include "board.h"
 #include "wm_io.h"
 #include "wm_uart.h"
 #include "wm_gpio_afsel.h"
diff --git a/bsp/w60x/drivers/drv_wifi.c b/bsp/w60x/drivers/drv_wifi.c
index 2ae441b420..b7bc9eb459 100644
--- a/bsp/w60x/drivers/drv_wifi.c
+++ b/bsp/w60x/drivers/drv_wifi.c
@@ -14,8 +14,10 @@
 #include "wm_wifi.h"
 #include "drv_wifi.h"
 
-#define DBG_TAG "WIFI"
-#define DBG_LVL DBG_INFO
+#define DBG_ENABLE
+#define DBG_LEVEL DBG_INFO
+#define DBG_SECTION_NAME  "WIFI"
+#define DBG_COLOR
 #include <rtdbg.h>
 
 #include "wm_ram_config.h"
diff --git a/bsp/w60x/drivers/linker_scripts/link.icf b/bsp/w60x/drivers/linker_scripts/link.icf
index e3c1f23abb..a3e861ed85 100644
--- a/bsp/w60x/drivers/linker_scripts/link.icf
+++ b/bsp/w60x/drivers/linker_scripts/link.icf
@@ -7,9 +7,9 @@ define symbol __ICFEDIT_intvec_start__ = 0x08010100;
 /* rom 959K */
 define symbol __ICFEDIT_region_ROM_start__ = 0x08010100;
 define symbol __ICFEDIT_region_ROM_end__   = 0x080FFFFF;
-/* ram 224k */
+/* ram 160k */
 define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
-define symbol __ICFEDIT_region_RAM_end__   = 0x2003C000;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20028000;
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__ = 0xc00;
 define symbol __ICFEDIT_size_heap__   = 0x1A000;
diff --git a/bsp/w60x/drivers/linker_scripts/link.lds b/bsp/w60x/drivers/linker_scripts/link.lds
index 33e9132506..483ead847b 100644
--- a/bsp/w60x/drivers/linker_scripts/link.lds
+++ b/bsp/w60x/drivers/linker_scripts/link.lds
@@ -8,8 +8,8 @@
 
 MEMORY
 {
-  FLASH (rx) : ORIGIN = 0x8010100, LENGTH = 959K    /* 960K-256B */
-  RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x3C000 /* 240K */
+    FLASH (rx) : ORIGIN = 0x8010100, LENGTH = 959K    /* 960K-256B */
+    RAM (rw) : ORIGIN = 0x20000000, LENGTH = 0x28000  /* 160K */
 }
 
 /* Linker script to place sections and symbol values. Should be used together
@@ -79,6 +79,12 @@ SECTIONS
         __rt_init_end = .;
 
         . = ALIGN(4);
+        __rtatcmdtab_start = .;
+        KEEP(*(RtAtCmdTab))
+        __rtatcmdtab_end = .;
+        . = ALIGN(4);
+
+        . = ALIGN(4);
         KEEP(*(.init))
         KEEP(*(.fini))
 
diff --git a/bsp/w60x/drivers/linker_scripts/link.sct b/bsp/w60x/drivers/linker_scripts/link.sct
index 20191e6190..76ca106e6b 100644
--- a/bsp/w60x/drivers/linker_scripts/link.sct
+++ b/bsp/w60x/drivers/linker_scripts/link.sct
@@ -3,12 +3,13 @@
 ; *************************************************************
 
 LR_IROM1 0x08010100 0x000EFEFF  {    ; load region size_region
-  ER_IROM1 0x08010100 0x000EFEFF  {  ; load address = execution address
+   ER_IROM1 0x08010100 0x000EFEFF  {  ; load address = execution address
    *.o (RESET, +First)
    *(InRoot$$Sections)
    .ANY (+RO)
+   .ANY (+XO)
   }
-  RW_IRAM1 0x20000000 0x0003C000  {  ; RW data
+  RW_IRAM1 0x20000000 0x00028000  {  ; RW data
    .ANY (+RW +ZI)
   }
 }
diff --git a/bsp/w60x/drivers/pin_config.h b/bsp/w60x/drivers/pin_config.h
new file mode 100644
index 0000000000..cf1eb774c3
--- /dev/null
+++ b/bsp/w60x/drivers/pin_config.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2019-06-01     Ernest       the first version
+ */
+#ifndef __PIN_CONFIG_H__
+#define __PIN_CONFIG_H__
+
+// UART
+#define WM_UART2_RX_PIN  1          // PB19 : UART2_RX  (W601)
+#define WM_UART2_TX_PIN  2          // PB20 : UART2_TX  (W601)
+
+#define WM_UART1_RX_PIN  31         // PB11 : UART1_RX  (W600)
+#define WM_UART1_TX_PIN  32         // PB12 : UART1_TX  (W600)
+
+// spi
+#define WM_SPI_CK_PIN 53            // PB27 : SPI_SCK
+#define WM_SPI_DI_PIN 55            // PB1  : SPI_MISO
+#define WM_SPI_DO_PIN 56            // PB2  : SPI_MOSI
+
+// i2c
+#define WM_I2C_SCL_PIN 18
+#define WM_I2C_DAT_PIN 19
+
+// soft i2c
+#define SOFT_I2C1_SCL_PIN 23         // PA0 : I2C1_SCL
+#define SOFT_I2C1_SDA_PIN 24         // PA1 : I2C1_SDA
+#define SOFT_I2C2_SCL_PIN 25         // PA2 : I2C2_SCL
+#define SOFT_I2C2_SDA_PIN 24         // PA1 : I2C2_SDA
+
+#endif /* __PIN_CONFIG_H__ */
+