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authorBernard Xiong <[email protected]>2021-05-28 16:20:08 +0800
committerGitHub <[email protected]>2021-05-28 16:20:08 +0800
commit92beddf3bccf6346e26aa097f82464456fb8e6bd (patch)
tree197e4a108118dda016ea02274172f0c40e7ee8ed /bsp/wh44b0/rtconfig.h
parentb18a99b44240ec3152011e159cc24a5af8dff0ce (diff)
parent03f4d40e30f3c94e1db0b3a65b3610dee695694a (diff)
Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5
[lts 3.1.x] format codes
Diffstat (limited to 'bsp/wh44b0/rtconfig.h')
-rw-r--r--bsp/wh44b0/rtconfig.h34
1 files changed, 17 insertions, 17 deletions
diff --git a/bsp/wh44b0/rtconfig.h b/bsp/wh44b0/rtconfig.h
index 32364bbc4a..0f981e1be7 100644
--- a/bsp/wh44b0/rtconfig.h
+++ b/bsp/wh44b0/rtconfig.h
@@ -3,16 +3,16 @@
#define __RTTHREAD_CFG_H__
/* RT_NAME_MAX*/
-#define RT_NAME_MAX 8
+#define RT_NAME_MAX 8
/* RT_ALIGN_SIZE*/
-#define RT_ALIGN_SIZE 4
+#define RT_ALIGN_SIZE 4
/* PRIORITY_MAX*/
-#define RT_THREAD_PRIORITY_MAX 256
+#define RT_THREAD_PRIORITY_MAX 256
/* Tick per Second*/
-#define RT_TICK_PER_SECOND 100
+#define RT_TICK_PER_SECOND 100
/* SECTION: RT_DEBUG */
/* Thread Debug*/
@@ -59,7 +59,7 @@
/* SECTION: Console options */
/* the buffer size of console*/
-#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLEBUF_SIZE 128
/* SECTION: FinSH shell options */
/* Using FinSH as Shell*/
@@ -99,21 +99,21 @@
/* #define RT_LWIP_DHCP */
/* ip address of target*/
-#define RT_LWIP_IPADDR0 192
-#define RT_LWIP_IPADDR1 168
-#define RT_LWIP_IPADDR2 0
-#define RT_LWIP_IPADDR3 30
+#define RT_LWIP_IPADDR0 192
+#define RT_LWIP_IPADDR1 168
+#define RT_LWIP_IPADDR2 0
+#define RT_LWIP_IPADDR3 30
/* gateway address of target*/
-#define RT_LWIP_GWADDR0 192
-#define RT_LWIP_GWADDR1 168
-#define RT_LWIP_GWADDR2 0
-#define RT_LWIP_GWADDR3 1
+#define RT_LWIP_GWADDR0 192
+#define RT_LWIP_GWADDR1 168
+#define RT_LWIP_GWADDR2 0
+#define RT_LWIP_GWADDR3 1
/* mask address of target*/
-#define RT_LWIP_MSKADDR0 255
-#define RT_LWIP_MSKADDR1 255
-#define RT_LWIP_MSKADDR2 255
-#define RT_LWIP_MSKADDR3 0
+#define RT_LWIP_MSKADDR0 255
+#define RT_LWIP_MSKADDR1 255
+#define RT_LWIP_MSKADDR2 255
+#define RT_LWIP_MSKADDR3 0
#endif