Merge branch 'master' of https://github.com/RT-Thread/rt-thread

author: moebius.ever <[email protected]> 2018-03-21 15:37:23 +0800
committer: moebius.ever <[email protected]> 2018-03-21 15:37:23 +0800
commit: feeff73168b1e6bb3aa1a286add44af7ac940bc2 (patch)
tree: d9dc4985294d771c3edd28bc7897941788d4ecca /bsp
parent: 61946325ee0850631758fd50a0cf68df3caf970e (diff)
parent: 883290ddefea2a7160f21960d955c601ad180d7b (diff)
15 files changed, 3334 insertions, 2719 deletions
diff --git a/bsp/imxrt1052-evk/.config b/bsp/imxrt1052-evk/.config
index 130d4835b5..badc996951 100644
--- a/bsp/imxrt1052-evk/.config
+++ b/bsp/imxrt1052-evk/.config
@@ -130,7 +130,9 @@ CONFIG_RT_USING_I2C_BITOPS=y
 CONFIG_RT_USING_PIN=y
 # CONFIG_RT_USING_MTD_NOR is not set
 # CONFIG_RT_USING_MTD_NAND is not set
-# CONFIG_RT_USING_RTC is not set
+CONFIG_RT_USING_RTC=y
+# CONFIG_RT_USING_SOFT_RTC is not set
+# CONFIG_RTC_SYNC_USING_NTP is not set
 CONFIG_RT_USING_SDIO=y
 # CONFIG_RT_USING_SPI is not set
 # CONFIG_RT_USING_WDT is not set
@@ -312,5 +314,5 @@ CONFIG_LWIP_NETIF_LOOPBACK=0
 # CONFIG_PKG_USING_HELLO is not set
 # CONFIG_PKG_USING_MULTIBUTTON is not set
 CONFIG_SOC_IMXRT1052=y
-CONFIG_RT_USING_UART=y
 CONFIG_RT_USING_UART1=y
+CONFIG_RT_USING_HP_RTC=y
diff --git a/bsp/imxrt1052-evk/Kconfig b/bsp/imxrt1052-evk/Kconfig
index 0a15061526..8bfb1e2589 100644
--- a/bsp/imxrt1052-evk/Kconfig
+++ b/bsp/imxrt1052-evk/Kconfig
@@ -23,13 +23,15 @@ config SOC_IMXRT1052
     select ARCH_ARM_CORTEX_M7
     default y
 
-config RT_USING_UART
-    bool "Using RT_USING_UART"
-    default y
-
-if RT_USING_UART
+if RT_USING_SERIAL
 config RT_USING_UART1
     bool "Using RT_USING_UART1"
-    default y      
+    default y 
 endif
- 
+
+if RT_USING_RTC
+config RT_USING_HP_RTC
+    bool "Using RT_USING_HP_RTC"
+    default n 
+endif
+
diff --git a/bsp/imxrt1052-evk/drivers/SConscript b/bsp/imxrt1052-evk/drivers/SConscript
index 4025fb6fbc..c18b8ca321 100644
--- a/bsp/imxrt1052-evk/drivers/SConscript
+++ b/bsp/imxrt1052-evk/drivers/SConscript
@@ -7,7 +7,7 @@ cwd     = os.path.join(str(Dir('#')), 'drivers')
 # add the general drivers.
 src = Split("""
 board.c
-usart.c
+drv_uart.c
 hyper_flash_boot.c
 drv_sdram.c
 """)
@@ -18,6 +18,9 @@ CPPDEFINES = []
 if GetDepend('RT_USING_PIN'):
     src += ['drv_pin.c']
 
+if GetDepend('RT_USING_HP_RTC'):
+    src += ['drv_hp_rtc.c']
+
 if GetDepend('RT_USING_LWIP'):
     src += ['drv_eth.c', 'fsl_phy.c']
     CPPDEFINES += ['FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE']
diff --git a/bsp/imxrt1052-evk/drivers/board.c b/bsp/imxrt1052-evk/drivers/board.c
index 5cb875827a..b182ed58e0 100644
--- a/bsp/imxrt1052-evk/drivers/board.c
+++ b/bsp/imxrt1052-evk/drivers/board.c
@@ -16,7 +16,7 @@
 #include <rtthread.h>
 
 #include "board.h"
-#include "usart.h"
+#include "drv_uart.h"
 
 static struct rt_memheap system_heap;
 
diff --git a/bsp/imxrt1052-evk/drivers/drv_hp_rtc.c b/bsp/imxrt1052-evk/drivers/drv_hp_rtc.c
new file mode 100644
index 0000000000..29093e0eb8
--- /dev/null
+++ b/bsp/imxrt1052-evk/drivers/drv_hp_rtc.c
@@ -0,0 +1,150 @@
+/*
+ * File      : drv_hp_rtc.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-03-15     Liuguang     the first version.
+ */
+#include "drv_hp_rtc.h" 
+#include <time.h>
+#include "fsl_common.h" 
+#include "fsl_snvs_hp.h"
+#include "fsl_snvs_lp.h"
+
+#ifdef RT_USING_RTC
+
+#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
+    #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
+#endif
+
+static time_t get_timestamp(void) 
+{
+    struct tm tm_new = {0}; 
+    snvs_hp_rtc_datetime_t rtcDate; 
+    
+    SNVS_HP_RTC_GetDatetime(SNVS, &rtcDate); 
+    
+    tm_new.tm_sec  = rtcDate.second; 
+    tm_new.tm_min  = rtcDate.minute; 
+    tm_new.tm_hour = rtcDate.hour;
+    
+    tm_new.tm_mday = rtcDate.day; 
+    tm_new.tm_mon  = rtcDate.month - 1;  
+    tm_new.tm_year = rtcDate.year - 1900; 
+
+    return mktime(&tm_new);
+}
+
+static int set_timestamp(time_t timestamp)
+{
+    struct tm *p_tm;
+    snvs_hp_rtc_datetime_t rtcDate; 
+    
+    p_tm = localtime(&timestamp);
+    
+    rtcDate.second = p_tm->tm_sec ; 
+    rtcDate.minute = p_tm->tm_min ; 
+    rtcDate.hour   = p_tm->tm_hour; 
+
+    rtcDate.day    = p_tm->tm_mday; 
+    rtcDate.month  = p_tm->tm_mon  + 1;  
+    rtcDate.year   = p_tm->tm_year + 1900; 
+    
+    SNVS_HP_RTC_SetDatetime(SNVS, &rtcDate); 
+    
+    return RT_EOK;
+}
+
+/* �����ӿ� */
+static rt_err_t rt1052_hp_rtc_init(rt_device_t dev)
+{
+    snvs_hp_rtc_config_t snvsRtcConfig;
+    
+    SNVS_HP_RTC_GetDefaultConfig(&snvsRtcConfig);
+    SNVS_HP_RTC_Init(SNVS, &snvsRtcConfig);
+    
+    SNVS_HP_RTC_StartTimer(SNVS); 
+    
+    return RT_EOK; 
+}
+
+static rt_err_t rt1052_hp_rtc_open(rt_device_t dev, rt_uint16_t oflag)
+{
+    return RT_EOK; 
+}
+
+static rt_err_t rt1052_hp_rtc_close(rt_device_t dev) 
+{
+    return RT_EOK; 
+} 
+
+static rt_size_t rt1052_hp_rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+    return 0; 
+}
+
+static rt_size_t rt1052_hp_rtc_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+    return 0; 
+}
+
+static rt_err_t rt1052_hp_rtc_control(rt_device_t dev, int cmd, void *args)
+{
+    RT_ASSERT(dev != RT_NULL);
+    
+    switch(cmd)
+    {
+        case RT_DEVICE_CTRL_RTC_GET_TIME: 
+        {
+            *(uint32_t *)args = get_timestamp(); 
+        }
+        break;
+            
+        case RT_DEVICE_CTRL_RTC_SET_TIME: 
+        {
+            set_timestamp(*(time_t *)args); 
+        }
+        break;
+            
+        /* ��Ч���� */
+        default:
+            return RT_EINVAL; 
+    }
+    
+    return RT_EOK; 
+}
+
+static struct rt_device device = 
+{
+    .type    = RT_Device_Class_RTC, 
+    .init    = rt1052_hp_rtc_init, 
+    .open    = rt1052_hp_rtc_open, 
+    .close   = rt1052_hp_rtc_close, 
+    .read    = rt1052_hp_rtc_read,
+    .write   = rt1052_hp_rtc_write,
+    .control = rt1052_hp_rtc_control, 
+};
+
+int rt_hw_hp_rtc_init(void)
+{
+    rt_err_t ret = RT_EOK;
+    
+    ret = rt_device_register(&device, "rtc", RT_DEVICE_FLAG_RDWR); 
+    if(ret != RT_EOK)
+    {
+        return ret; 
+    }
+    
+    rt_device_open(&device, RT_DEVICE_OFLAG_RDWR); 
+    
+    return RT_EOK; 
+}
+INIT_DEVICE_EXPORT(rt_hw_hp_rtc_init); 
+
+#endif /*RT_USING_RTC */
diff --git a/bsp/imxrt1052-evk/drivers/drv_hp_rtc.h b/bsp/imxrt1052-evk/drivers/drv_hp_rtc.h
new file mode 100644
index 0000000000..e191e4714c
--- /dev/null
+++ b/bsp/imxrt1052-evk/drivers/drv_hp_rtc.h
@@ -0,0 +1,23 @@
+/*
+ * File      : drv_hp_rtc.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-03-15     Liuguang     the first version. 
+ */
+ 
+#ifndef __DRV_RTC_H__
+#define __DRV_RTC_H__
+
+#include <rtthread.h> 
+#include <rtdevice.h> 
+
+int rt_hw_hp_rtc_init(void);
+
+#endif
diff --git a/bsp/imxrt1052-evk/drivers/drv_pin.c b/bsp/imxrt1052-evk/drivers/drv_pin.c
index 84e3733039..3715371cde 100644
--- a/bsp/imxrt1052-evk/drivers/drv_pin.c
+++ b/bsp/imxrt1052-evk/drivers/drv_pin.c
@@ -9,7 +9,8 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2018-03-13     Liuguang     the first version. 
+ * 2018-03-13     Liuguang     the first version.
+ * 2018-03-19     Liuguang     add GPIO interrupt mode support.
  */
 #include "drv_pin.h" 
 
@@ -19,12 +20,10 @@
 
 #ifdef RT_USING_PIN
 
-/* GPIO����ʱ�ӻ���GPIO_PinInit���Զ�����, ������������º��򲻻��Զ����� */ 
 #if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
     #error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
 #endif
 
-/* RT1052 PIN�����ṹ�� */
 struct rt1052_pin
 {
     rt_uint16_t   pin; 
@@ -32,10 +31,18 @@ struct rt1052_pin
     rt_uint32_t   gpio_pin; 
 }; 
 
+struct rt1052_irq
+{
+    rt_uint16_t           enable; 
+    struct rt_pin_irq_hdr irq_info; 
+};
+
 #define __ARRAY_LEN(array) (sizeof(array)/sizeof(array[0])) 
 #define __RT1052_PIN_DEFAULT {0, 0, 0} 
 #define __RT1052_PIN(INDEX, PORT, PIN) {INDEX, PORT, PIN} 
 
+static struct rt_pin_ops rt1052_pin_ops; 
+
 static struct rt1052_pin rt1052_pin_map[] = 
 {
     __RT1052_PIN_DEFAULT, 
@@ -179,6 +186,279 @@ static struct rt1052_pin rt1052_pin_map[] =
     __RT1052_PIN(127, GPIO5,  2)     /* PMIC_STBY_REQ */
 }; 
 
+static struct rt1052_irq rt1052_irq_map[] = 
+{
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} },
+    {PIN_IRQ_DISABLE, {PIN_IRQ_PIN_NONE, PIN_IRQ_MODE_RISING, RT_NULL, RT_NULL} }
+}; 
+
+void gpio_isr(GPIO_Type* base, rt_uint32_t gpio_pin)
+{
+    if((GPIO_PortGetInterruptFlags(base) & (1 << gpio_pin)) != 0)
+    {
+        GPIO_PortClearInterruptFlags(base, gpio_pin); 
+        
+        if(rt1052_irq_map[gpio_pin].irq_info.hdr != RT_NULL)
+        {
+            rt1052_irq_map[gpio_pin].irq_info.hdr(rt1052_irq_map[gpio_pin].irq_info.args);
+        }
+    }
+}
+
+void GPIO1_Combined_0_15_IRQHandler(void)
+{
+    rt_uint8_t gpio_pin; 
+    
+    rt_interrupt_enter();
+
+    for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
+    {
+        gpio_isr(GPIO1, gpio_pin); 
+    }
+    
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+    
+    rt_interrupt_leave();
+}
+
+void GPIO1_Combined_16_31_IRQHandler(void)
+{
+    rt_uint8_t gpio_pin; 
+    
+    rt_interrupt_enter();
+
+    for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
+    {
+        gpio_isr(GPIO1, gpio_pin); 
+    }
+    
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+    
+    rt_interrupt_leave();
+}
+
+void GPIO2_Combined_0_15_IRQHandler(void)
+{
+    rt_uint8_t gpio_pin; 
+    
+    rt_interrupt_enter();
+
+    for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
+    {
+        gpio_isr(GPIO2, gpio_pin); 
+    }
+    
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+    
+    rt_interrupt_leave();
+}
+
+void GPIO2_Combined_16_31_IRQHandler(void)
+{
+    rt_uint8_t gpio_pin; 
+    
+    rt_interrupt_enter();
+
+    for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
+    {
+        gpio_isr(GPIO2, gpio_pin); 
+    }
+    
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+    
+    rt_interrupt_leave();
+}
+
+void GPIO3_Combined_0_15_IRQHandler(void) 
+{
+    rt_uint8_t gpio_pin; 
+    
+    rt_interrupt_enter();
+
+    for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
+    {
+        gpio_isr(GPIO3, gpio_pin); 
+    }
+    
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+    
+    rt_interrupt_leave();
+}
+
+void GPIO3_Combined_16_31_IRQHandler(void)
+{
+    rt_uint8_t gpio_pin; 
+    
+    rt_interrupt_enter();
+
+    for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
+    {
+        gpio_isr(GPIO3, gpio_pin); 
+    }
+    
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+    
+    rt_interrupt_leave();
+}
+
+void GPIO4_Combined_0_15_IRQHandler(void)
+{
+    rt_uint8_t gpio_pin; 
+    
+    rt_interrupt_enter();
+
+    for(gpio_pin = 0; gpio_pin <= 15; gpio_pin++)
+    {
+        gpio_isr(GPIO4, gpio_pin); 
+    }
+    
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+    
+    rt_interrupt_leave();
+}
+void GPIO4_Combined_16_31_IRQHandler(void)
+{
+    rt_uint8_t gpio_pin; 
+    
+    rt_interrupt_enter();
+
+    for(gpio_pin = 16; gpio_pin <= 31; gpio_pin++)
+    {
+        gpio_isr(GPIO4, gpio_pin); 
+    }
+    
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+    
+    rt_interrupt_leave();
+}
+
+void GPIO5_Combined_0_15_IRQHandler(void)
+{ 
+    rt_uint8_t gpio_pin; 
+    
+    rt_interrupt_enter();
+
+    for(gpio_pin = 0; gpio_pin <= 2; gpio_pin++)
+    {
+        gpio_isr(GPIO5, gpio_pin); 
+    }
+    
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+    
+    rt_interrupt_leave();
+}
+
+static IRQn_Type rt1052_get_irqnum(GPIO_Type *gpio, rt_uint32_t gpio_pin)
+{
+    IRQn_Type irq_num; 
+    
+    if(gpio == GPIO1)
+    {
+        if(gpio_pin <= 15)
+        {
+            irq_num = GPIO1_Combined_0_15_IRQn; 
+        }
+        else
+        {
+            irq_num = GPIO1_Combined_16_31_IRQn; 
+        }
+    }
+    else if(gpio == GPIO2)
+    {
+        if(gpio_pin <= 15)
+        {
+            irq_num = GPIO2_Combined_0_15_IRQn; 
+        }
+        else
+        {
+            irq_num = GPIO2_Combined_16_31_IRQn; 
+        }
+    }
+    else if(gpio == GPIO3)
+    {
+        if(gpio_pin <= 15)
+        {
+            irq_num = GPIO3_Combined_0_15_IRQn; 
+        }
+        else
+        {
+            irq_num = GPIO3_Combined_16_31_IRQn; 
+        }
+    }
+    else if(gpio == GPIO4)
+    {
+        if(gpio_pin <= 15)
+        {
+            irq_num = GPIO4_Combined_0_15_IRQn; 
+        }
+        else
+        {
+            irq_num = GPIO4_Combined_16_31_IRQn; 
+        }
+    }
+    else if(gpio == GPIO5)
+    {
+        if(gpio_pin <= 15)
+        {
+            irq_num = GPIO5_Combined_0_15_IRQn; 
+        }
+        else
+        {
+            irq_num = GPIO5_Combined_16_31_IRQn; 
+        }
+    }
+    
+    return irq_num; 
+}
+
 static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
 {
     gpio_pin_config_t gpio; 
@@ -193,15 +473,15 @@ static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
     {
         CLOCK_EnableClock(kCLOCK_Iomuxc); 
         
+        IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 0); 
     }
     else
     {
         CLOCK_EnableClock(kCLOCK_IomuxcSnvs); 
+        
+        IOMUXC_SetPinMux(0x401F8000U + (pin-125)*4, 0x5U, 0, 0, 0, 0); 
     }
     
-    /* ����IOMUXC: ��IO����ΪGPIO */ 
-    IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 0); 
-    
     gpio.outputLogic = 0; 
     gpio.interruptMode = kGPIO_NoIntmode; 
     
@@ -243,7 +523,6 @@ static void rt1052_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
         break;
     }
     
-    /* ����GPIOģʽ: ������ģʽ, ��©ģ, IO��ת�ٶ�(50MHz) */ 
     IOMUXC_SetPinConfig(0, 0, 0, 0, 0x401F8200U + pin*4, config_value); 
     
     GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio); 
@@ -259,17 +538,175 @@ static void rt1052_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
     GPIO_PinWrite(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, value);
 }
 
-static struct rt_pin_ops rt1052_pin_ops = 
+static rt_err_t rt1052_pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+    rt_uint32_t mode, void (*hdr)(void *args), void *args)
 {
-    .pin_mode  = rt1052_pin_mode, 
-    .pin_read  = rt1052_pin_read, 
-    .pin_write = rt1052_pin_write
-}; 
+    struct rt1052_pin* pin_map = RT_NULL; 
+    struct rt1052_irq* irq_map = RT_NULL; 
+    
+    pin_map = &rt1052_pin_map[pin]; 
+    irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; 
+    
+    if(pin_map == RT_NULL || irq_map == RT_NULL) 
+    {
+        return RT_ENOSYS; 
+    }
+    
+    if(irq_map->enable == PIN_IRQ_ENABLE)
+    {
+        return RT_EBUSY; 
+    }
+    
+    irq_map->irq_info.pin  = pin; 
+    irq_map->irq_info.hdr  = hdr; 
+    irq_map->irq_info.mode = mode; 
+    irq_map->irq_info.args = args; 
+    
+    return RT_EOK;
+}
+
+static rt_err_t rt1052_pin_dettach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    struct rt1052_pin* pin_map = RT_NULL; 
+    struct rt1052_irq* irq_map = RT_NULL; 
+    
+    pin_map = &rt1052_pin_map[pin]; 
+    irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; 
+    
+    if(pin_map == RT_NULL || irq_map == RT_NULL) 
+    {
+        return RT_ENOSYS; 
+    }
+    
+    if(irq_map->enable == PIN_IRQ_DISABLE)
+    {
+        return RT_EOK; 
+    }
+    
+    irq_map->irq_info.pin  = PIN_IRQ_PIN_NONE; 
+    irq_map->irq_info.hdr  = RT_NULL; 
+    irq_map->irq_info.mode = PIN_IRQ_MODE_RISING; 
+    irq_map->irq_info.args = RT_NULL; 
+    
+    return RT_EOK;
+}
+
+static rt_err_t rt1052_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled)
+{
+    gpio_pin_config_t gpio; 
+    IRQn_Type irq_num;
+    
+    struct rt1052_pin* pin_map = RT_NULL; 
+    struct rt1052_irq* irq_map = RT_NULL; 
+    
+    pin_map = &rt1052_pin_map[pin]; 
+    irq_map = &rt1052_irq_map[rt1052_pin_map[pin].gpio_pin]; 
+    
+    if(pin_map == RT_NULL || irq_map == RT_NULL) 
+    {
+        return RT_ENOSYS; 
+    }
+    
+    if(enabled == PIN_IRQ_ENABLE) 
+    {
+        if(irq_map->enable == PIN_IRQ_ENABLE)
+        {
+            return RT_EBUSY; 
+        }
+        
+        if(irq_map->irq_info.pin != pin)
+        {
+            return RT_EIO; 
+        }
+        
+        irq_map->enable = PIN_IRQ_ENABLE; 
+        
+        if(rt1052_pin_map[pin].gpio != GPIO5)
+        {
+            CLOCK_EnableClock(kCLOCK_Iomuxc); 
+            IOMUXC_SetPinMux(0x401F8010U + pin*4, 0x5U, 0, 0, 0, 0); 
+        }
+        else
+        {
+            CLOCK_EnableClock(kCLOCK_IomuxcSnvs); 
+            IOMUXC_SetPinMux(0x401F8000U + (pin-125)*4, 0x5U, 0, 0, 0, 0); 
+        }
+        
+        gpio.direction     = kGPIO_DigitalInput; 
+        gpio.outputLogic   = 0; 
+        
+        switch(irq_map->irq_info.mode)
+        {
+            case PIN_IRQ_MODE_RISING:
+            {
+                gpio.interruptMode = kGPIO_IntRisingEdge; 
+            }
+            break;
+            
+            case PIN_IRQ_MODE_FALLING:
+            {
+                gpio.interruptMode = kGPIO_IntFallingEdge; 
+            }
+            break;
+            
+            case PIN_IRQ_MODE_RISING_FALLING:
+            {
+                gpio.interruptMode = kGPIO_IntRisingOrFallingEdge; 
+            }
+            break;
+            
+            case PIN_IRQ_MODE_HIGH_LEVEL:
+            {
+                gpio.interruptMode = kGPIO_IntHighLevel; 
+            }
+            break;
+            
+            case PIN_IRQ_MODE_LOW_LEVEL:
+            {
+                gpio.interruptMode = kGPIO_IntLowLevel; 
+            }
+            break;
+        }
+        
+        irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); 
+        
+        NVIC_SetPriority(irq_num, NVIC_EncodePriority(NVIC_GetPriorityGrouping(), 5, 0));
+        EnableIRQ(irq_num);
+        
+        GPIO_PinInit(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin, &gpio); 
+        GPIO_PortEnableInterrupts(rt1052_pin_map[pin].gpio, 1U << rt1052_pin_map[pin].gpio_pin); 
+    }
+    else if(enabled == PIN_IRQ_DISABLE)
+    {
+        if(irq_map->enable == PIN_IRQ_DISABLE)
+        {
+            return RT_EOK; 
+        }
+        
+        irq_map->enable = PIN_IRQ_DISABLE;
+        irq_num = rt1052_get_irqnum(rt1052_pin_map[pin].gpio, rt1052_pin_map[pin].gpio_pin); 
+        
+        NVIC_DisableIRQ(irq_num);
+    }
+    else
+    {
+        return RT_EINVAL; 
+    }
+    
+    return RT_EOK;
+}
 
 int rt_hw_pin_init(void)
 {
     int ret = RT_EOK; 
     
+    rt1052_pin_ops.pin_mode        = rt1052_pin_mode; 
+    rt1052_pin_ops.pin_read        = rt1052_pin_read; 
+    rt1052_pin_ops.pin_write       = rt1052_pin_write; 
+    rt1052_pin_ops.pin_attach_irq  = rt1052_pin_attach_irq; 
+    rt1052_pin_ops.pin_dettach_irq = rt1052_pin_dettach_irq;
+    rt1052_pin_ops.pin_irq_enable  = rt1052_pin_irq_enable; 
+    
     ret = rt_device_pin_register("pin", &rt1052_pin_ops, RT_NULL);
     
     return ret;
diff --git a/bsp/imxrt1052-evk/drivers/drv_pin.h b/bsp/imxrt1052-evk/drivers/drv_pin.h
index f1de4fbea7..6c0574ec0f 100644
--- a/bsp/imxrt1052-evk/drivers/drv_pin.h
+++ b/bsp/imxrt1052-evk/drivers/drv_pin.h
@@ -10,6 +10,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018-03-13     Liuguang     the first version. 
+ * 2018-03-19     Liuguang     add GPIO interrupt mode support.
  */
  
 #ifndef __DRV_PIN_H__
diff --git a/bsp/imxrt1052-evk/drivers/usart.c b/bsp/imxrt1052-evk/drivers/drv_uart.c
index 68c0f500ee..e4a303ef22 100644
--- a/bsp/imxrt1052-evk/drivers/usart.c
+++ b/bsp/imxrt1052-evk/drivers/drv_uart.c
@@ -1,5 +1,5 @@
 /*
- * File      : usart.c
+ * File      : drv_uart.c
  * This file is part of RT-Thread RTOS
  * COPYRIGHT (C) 2006-2013, RT-Thread Development Team
  *
@@ -10,24 +10,32 @@
  * Change Logs:
  * Date           Author       Notes
  * 2017-10-10     Tanek        the first version
+ * 2018-03-17     laiyiketang  Add other uart.
  */
 #include <rtthread.h>
-#include "usart.h"
+#include "drv_uart.h"
 
 #include "fsl_common.h"
 #include "fsl_lpuart.h"
 #include "fsl_iomuxc.h"
 
-#ifdef RT_USING_UART
+#ifdef RT_USING_SERIAL
 
-#if !defined(RT_USING_UART0) && !defined(RT_USING_UART1) && \
-    !defined(RT_USING_UART2) && !defined(RT_USING_UART3) && \
-    !defined(RT_USING_UART4) && !defined(RT_USING_UART5) && \
-    !defined(RT_USING_UART6) && !defined(RT_USING_UART7)
+/* GPIO����ʱ�ӻ���LPUART_Init���Զ�����, ������������º��򲻻��Զ����� */
+#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
+#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
+#endif
+
+#if !defined(RT_USING_UART1) && !defined(RT_USING_UART2) && \
+    !defined(RT_USING_UART3) && !defined(RT_USING_UART4) && \
+    !defined(RT_USING_UART5) && !defined(RT_USING_UART6) && \
+    !defined(RT_USING_UART7) && !defined(RT_USING_UART8)
 #error "Please define at least one UARTx"
 
 #endif
 
+
+
 #include <rtdevice.h>
 
 /* imxrt uart driver */
@@ -55,7 +63,7 @@ void LPUART1_IRQHandler(void)
 #if defined(RT_USING_UART2)
 struct rt_serial_device serial2;
 
-void USART2_IRQHandler(void)
+void LPUART2_IRQHandler(void)
 {
     uart_isr(&serial2);
 }
@@ -65,7 +73,7 @@ void USART2_IRQHandler(void)
 #if defined(RT_USING_UART3)
 struct rt_serial_device serial3;
 
-void UART3_IRQHandler(void)
+void LPUART3_IRQHandler(void)
 {
     uart_isr(&serial3);
 }
@@ -75,7 +83,7 @@ void UART3_IRQHandler(void)
 #if defined(RT_USING_UART4)
 struct rt_serial_device serial4;
 
-void UART4_IRQHandler(void)
+void LPUART4_IRQHandler(void)
 {
     uart_isr(&serial4);
 }
@@ -84,7 +92,7 @@ void UART4_IRQHandler(void)
 #if defined(RT_USING_UART5)
 struct rt_serial_device serial5;
 
-void USART5_IRQHandler(void)
+void LPUART5_IRQHandler(void)
 {
     uart_isr(&serial5);
 }
@@ -94,7 +102,7 @@ void USART5_IRQHandler(void)
 #if defined(RT_USING_UART6)
 struct rt_serial_device serial6;
 
-void UART6_IRQHandler(void)
+void LPUART6_IRQHandler(void)
 {
     uart_isr(&serial6);
 }
@@ -104,7 +112,7 @@ void UART6_IRQHandler(void)
 #if defined(RT_USING_UART7)
 struct rt_serial_device serial7;
 
-void UART7_IRQHandler(void)
+void LPUART7_IRQHandler(void)
 {
     uart_isr(&serial7);
 }
@@ -114,7 +122,7 @@ void UART7_IRQHandler(void)
 #if defined(RT_USING_UART8)
 struct rt_serial_device serial8;
 
-void UART8_IRQHandler(void)
+void LPUART8_IRQHandler(void)
 {
     uart_isr(&serial8);
 }
@@ -122,14 +130,70 @@ void UART8_IRQHandler(void)
 #endif /* RT_USING_UART8 */
 
 static const struct imxrt_uart uarts[] = {
-    #ifdef RT_USING_UART1
+#ifdef RT_USING_UART1
     {
         LPUART1,
         LPUART1_IRQn,
         &serial1,
         "uart1",
     },
-    #endif
+#endif
+#ifdef RT_USING_UART2
+    {
+        LPUART2,
+        LPUART2_IRQn,
+        &serial2,
+        "uart2",
+    },
+#endif
+#ifdef RT_USING_UART3
+    {
+        LPUART3,
+        LPUART3_IRQn,
+        &serial3,
+        "uart3",
+    },
+#endif
+#ifdef RT_USING_UART4
+    {
+        LPUART4,
+        LPUART4_IRQn,
+        &serial4,
+        "uart4",
+    },
+#endif
+#ifdef RT_USING_UART5
+    {
+        LPUART5,
+        LPUART5_IRQn,
+        &serial5,
+        "uart5",
+    },
+#endif
+#ifdef RT_USING_UART6
+    {
+        LPUART6,
+        LPUART6_IRQn,
+        &serial6,
+        "uart6",
+    },
+#endif
+#ifdef RT_USING_UART7
+    {
+        LPUART7,
+        LPUART7_IRQn,
+        &serial7,
+        "uart7",
+    },
+#endif
+#ifdef RT_USING_UART8
+    {
+        LPUART8,
+        LPUART8_IRQn,
+        &serial8,
+        "uart8",
+    },
+#endif
 
 };
 
@@ -164,19 +228,20 @@ uint32_t BOARD_DebugConsoleSrcFreq(void)
 */
 void imxrt_uart_gpio_init(struct imxrt_uart *uart)
 {
-    if (uart->uart_base == LPUART1)
+    if (uart->uart_base != RT_NULL)
     {
-        CLOCK_EnableClock(kCLOCK_Iomuxc);          /* iomuxc clock (iomuxc_clk_enable): 0x03u */
+#ifdef RT_USING_UART1
+        CLOCK_EnableClock(kCLOCK_Iomuxc);           /* iomuxc clock (iomuxc_clk_enable): 0x03u */
 
         IOMUXC_SetPinMux(
-          IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 is configured as LPUART1_TX */
-          0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+            IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 is configured as LPUART1_TX */
+            0U);                                    /* Software Input On Field: Input Path is determined by functionality */
         IOMUXC_SetPinMux(
-          IOMUXC_GPIO_AD_B0_13_LPUART1_RX,        /* GPIO_AD_B0_13 is configured as LPUART1_RX */
-          0U);                                    /* Software Input On Field: Input Path is determined by functionality */
+            IOMUXC_GPIO_AD_B0_13_LPUART1_RX,        /* GPIO_AD_B0_13 is configured as LPUART1_RX */
+            0U);                                    /* Software Input On Field: Input Path is determined by functionality */
         IOMUXC_SetPinConfig(
-          IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 PAD functional properties : */
-          0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
+            IOMUXC_GPIO_AD_B0_12_LPUART1_TX,        /* GPIO_AD_B0_12 PAD functional properties : */
+            0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
                                                      Drive Strength Field: R0/6
                                                      Speed Field: medium(100MHz)
                                                      Open Drain Enable Field: Open Drain Disabled
@@ -185,8 +250,8 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
                                                      Pull Up / Down Config. Field: 100K Ohm Pull Down
                                                      Hyst. Enable Field: Hysteresis Disabled */
         IOMUXC_SetPinConfig(
-          IOMUXC_GPIO_AD_B0_13_LPUART1_RX,        /* GPIO_AD_B0_13 PAD functional properties : */
-          0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
+            IOMUXC_GPIO_AD_B0_13_LPUART1_RX,        /* GPIO_AD_B0_13 PAD functional properties : */
+            0x10B0u);                               /* Slew Rate Field: Slow Slew Rate
                                                      Drive Strength Field: R0/6
                                                      Speed Field: medium(100MHz)
                                                      Open Drain Enable Field: Open Drain Disabled
@@ -194,6 +259,128 @@ void imxrt_uart_gpio_init(struct imxrt_uart *uart)
                                                      Pull / Keep Select Field: Keeper
                                                      Pull Up / Down Config. Field: 100K Ohm Pull Down
                                                      Hyst. Enable Field: Hysteresis Disabled */
+#endif
+#ifdef RT_USING_UART2
+        CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
+            0U);
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
+            0U);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
+            0x10B0u);
+
+
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
+            0x10B0u);
+
+#endif
+#ifdef RT_USING_UART3
+        CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
+            0U);
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
+            0U);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
+            0x10B0u);
+
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
+            0x10B0u);
+#endif
+#ifdef RT_USING_UART4
+        CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_B1_00_LPUART4_TX,
+            0U);
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_B1_01_LPUART4_RX,
+            0U);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_B1_00_LPUART4_TX,
+            0x10B0u);
+
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_B1_01_LPUART4_RX,
+            0x10B0u);
+#endif
+#ifdef RT_USING_UART5
+        CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_B1_12_LPUART5_TX,
+            0U);
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_B1_13_LPUART5_RX,
+            0U);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_B1_12_LPUART5_TX,
+            0x10B0u);
+
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_B1_13_LPUART5_RX,
+            0x10B0u);
+#endif
+#ifdef RT_USING_UART6
+        CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
+            0U);
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
+            0U);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
+            0x10B0u);
+
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
+            0x10B0u);
+#endif
+#ifdef RT_USING_UART7
+        CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_EMC_31_LPUART7_TX,
+            0U);
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_EMC_32_LPUART7_RX,
+            0U);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_EMC_31_LPUART7_TX,
+            0x10B0u);
+
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_EMC_32_LPUART7_RX,
+            0x10B0u);
+#endif
+#ifdef RT_USING_UART8
+        CLOCK_EnableClock(kCLOCK_Iomuxc);
+
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
+            0U);
+        IOMUXC_SetPinMux(
+            IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
+            0U);
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
+            0x10B0u);
+
+        IOMUXC_SetPinConfig(
+            IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
+            0x10B0u);
+#endif
     }
     else
     {
@@ -324,10 +511,10 @@ static void uart_isr(struct rt_serial_device *serial)
     LPUART_Type *base;
 
     RT_ASSERT(serial != RT_NULL);
-    
+
     uart = (struct imxrt_uart *) serial->parent.user_data;
     RT_ASSERT(uart != RT_NULL);
-    
+
     base = uart->uart_base;
     RT_ASSERT(base != RT_NULL);
 
@@ -339,7 +526,7 @@ static void uart_isr(struct rt_serial_device *serial)
     {
         rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
     }
-    
+
     /* If RX overrun. */
     if (LPUART_STAT_OR_MASK & base->STAT)
     {
@@ -363,7 +550,6 @@ int imxrt_hw_usart_init(void)
 {
     struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
     int i;
-
     for (i = 0; i < sizeof(uarts) / sizeof(uarts[0]); i++)
     {
         uarts[i].serial->ops    = &imxrt_uart_ops;
@@ -380,4 +566,4 @@ int imxrt_hw_usart_init(void)
 }
 INIT_BOARD_EXPORT(imxrt_hw_usart_init);
 
-#endif /*RT_USING_UART*/
+#endif /*RT_USING_SERIAL */
diff --git a/bsp/imxrt1052-evk/drivers/usart.h b/bsp/imxrt1052-evk/drivers/drv_uart.h
index abd7631fee..f5d3842b46 100644
--- a/bsp/imxrt1052-evk/drivers/usart.h
+++ b/bsp/imxrt1052-evk/drivers/drv_uart.h
@@ -1,5 +1,5 @@
 /*
- * File      : usart.h
+ * File      : drv_uart.h
  * This file is part of RT-Thread RTOS
  * COPYRIGHT (C) 2009, RT-Thread Development Team
  *
@@ -9,11 +9,11 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2013-11-15     bright       the first version
+ * 2017-10-10     Tanek        the first version
  */
 
-#ifndef __USART_H__
-#define __USART_H__
+#ifndef __DRV_USART_H__
+#define __DRV_USART_H__
 
 #include <rthw.h>
 #include <rtthread.h>
diff --git a/bsp/imxrt1052-evk/project.ewp b/bsp/imxrt1052-evk/project.ewp
index d3ff73d2a7..5443606ca3 100644
--- a/bsp/imxrt1052-evk/project.ewp
+++ b/bsp/imxrt1052-evk/project.ewp
@@ -1,2649 +1,2450 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<project>
-    <fileVersion>3</fileVersion>
-    <configuration>
-        <name>Debug</name>
-        <toolchain>
-            <name>ARM</name>
-        </toolchain>
-        <debug>1</debug>
-        <settings>
-            <name>General</name>
-            <archiveVersion>3</archiveVersion>
-            <data>
-                <version>29</version>
-                <wantNonLocal>1</wantNonLocal>
-                <debug>1</debug>
-                <option>
-                    <name>ExePath</name>
-                    <state>Debug\Exe</state>
-                </option>
-                <option>
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+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\icmp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\igmp.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_addr.c</name>
+    </file>
+    <file>
+      <name>$PROJ_DIR$\..\..\components\net\lwip-2.0.2\src\core\ipv4\ip4_frag.c</name>
+    </file>
+  </group>
+</project>
diff --git a/bsp/imxrt1052-evk/project.uvprojx b/bsp/imxrt1052-evk/project.uvprojx
index 40d5d8b5d7..2c067820c8 100644
--- a/bsp/imxrt1052-evk/project.uvprojx
+++ b/bsp/imxrt1052-evk/project.uvprojx
@@ -333,7 +333,7 @@
               <MiscControls>--library_interface=armcc --library_type=standardlib --diag_suppress=66,1296,186</MiscControls>
               <Define>SKIP_SYSCLK_INIT, CPU_MIMXRT1052DVL6A, FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1, EVK_MCIMXRM, FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE, RT_USING_ARM_LIBC</Define>
               <Undefine />
-              <IncludePath>applications;.;drivers;Libraries;Libraries\drivers;Libraries\utilities;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m7;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\lwip-2.0.2\src\include\posix</IncludePath>
+              <IncludePath>applications;.;drivers;Libraries;Libraries\drivers;Libraries\utilities;Libraries\CMSIS\Include;..\..\include;..\..\libcpu\arm\cortex-m7;..\..\libcpu\arm\common;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\dfs\filesystems\elmfat;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\finsh;..\..\components\libc\compilers\armlibc;..\..\components\net\lwip-2.0.2\src;..\..\components\net\lwip-2.0.2\src\include;..\..\components\net\lwip-2.0.2\src\include\ipv4;..\..\components\net\lwip-2.0.2\src\arch\include;..\..\components\net\lwip-2.0.2\src\include\netif;..\..\components\net\lwip-2.0.2\src\include\posix</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -416,9 +416,9 @@
           </Files>
           <Files>
             <File>
-              <FileName>usart.c</FileName>
+              <FileName>drv_uart.c</FileName>
               <FileType>1</FileType>
-              <FilePath>drivers\usart.c</FilePath>
+              <FilePath>drivers\drv_uart.c</FilePath>
             </File>
           </Files>
           <Files>
@@ -444,6 +444,13 @@
           </Files>
           <Files>
             <File>
+              <FileName>drv_hp_rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>drivers\drv_hp_rtc.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
               <FileName>drv_eth.c</FileName>
               <FileType>1</FileType>
               <FilePath>drivers\drv_eth.c</FilePath>
@@ -1117,6 +1124,13 @@
           </Files>
           <Files>
             <File>
+              <FileName>rtc.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\..\components\drivers\rtc\rtc.c</FilePath>
+            </File>
+          </Files>
+          <Files>
+            <File>
               <FileName>block_dev.c</FileName>
               <FileType>1</FileType>
               <FilePath>..\..\components\drivers\sdio\block_dev.c</FilePath>
diff --git a/bsp/imxrt1052-evk/rtconfig.h b/bsp/imxrt1052-evk/rtconfig.h
index b04305f7b9..664aeb5458 100644
--- a/bsp/imxrt1052-evk/rtconfig.h
+++ b/bsp/imxrt1052-evk/rtconfig.h
@@ -121,7 +121,9 @@
 #define RT_USING_PIN
 /* RT_USING_MTD_NOR is not set */
 /* RT_USING_MTD_NAND is not set */
-/* RT_USING_RTC is not set */
+#define RT_USING_RTC
+/* RT_USING_SOFT_RTC is not set */
+/* RTC_SYNC_USING_NTP is not set */
 #define RT_USING_SDIO
 /* RT_USING_SPI is not set */
 /* RT_USING_WDT is not set */
@@ -277,7 +279,7 @@
 /* PKG_USING_HELLO is not set */
 /* PKG_USING_MULTIBUTTON is not set */
 #define SOC_IMXRT1052
-#define RT_USING_UART
 #define RT_USING_UART1
+#define RT_USING_HP_RTC
 
 #endif
diff --git a/bsp/lpc824/rtconfig.h b/bsp/lpc824/rtconfig.h
index b51d38aa9a..1426427b8d 100644
--- a/bsp/lpc824/rtconfig.h
+++ b/bsp/lpc824/rtconfig.h
@@ -80,7 +80,7 @@
 // </c>
 // <c1>Using Mutex
 //  <i>Using Mutex
-//#define RT_USING_MUTEX
+#define RT_USING_MUTEX
 // </c>
 // <c1>Using Event
 //  <i>Using Event
diff --git a/bsp/tm4c129x/libraries/SConscript b/bsp/tm4c129x/libraries/SConscript
index 8b48a34c7d..d1ed0b9383 100644
--- a/bsp/tm4c129x/libraries/SConscript
+++ b/bsp/tm4c129x/libraries/SConscript
@@ -18,12 +18,6 @@ elif rtconfig.CROSS_TOOL == 'iar':
 CPPPATH = [cwd, cwd + '/inc', cwd + '/driverlib']
 
 CPPDEFINES = [rtconfig.PART_TYPE]
-if rtconfig.CROSS_TOOL == 'gcc':
-	CPPDEFINES += ['gcc'];
-	CPPDEFINES += ['uint_fast8_t=uint32_t'];
-	CPPDEFINES += ['uint_fast32_t=uint32_t'];
-	CPPDEFINES += ['int_fast8_t=int32_t'];
-	CPPDEFINES += ['uint_fast16_t=uint32_t'];
 group = DefineGroup('Libraries', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES)
 
 Return('group')
author	moebius.ever <[email protected]>	2018-03-21 15:37:23 +0800
committer	moebius.ever <[email protected]>	2018-03-21 15:37:23 +0800
commit	feeff73168b1e6bb3aa1a286add44af7ac940bc2 (patch)
tree	d9dc4985294d771c3edd28bc7897941788d4ecca /bsp
parent	61946325ee0850631758fd50a0cf68df3caf970e (diff)
parent	883290ddefea2a7160f21960d955c601ad180d7b (diff)