[ARCH/RISC-V] Next RISC-V (#10320)

* [libcpu][risc-v] Refactor the RISC-V architecture port

Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.

- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration

Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.

Signed-off-by: GuEe-GUI <[email protected]>

* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk

Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.

Signed-off-by: seteiro <[email protected]>

* [libcpu][risc-v] Fix per-CPU page table mapping

- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings

Signed-off-by: GuEe-GUI <[email protected]>

---------

Signed-off-by: GuEe-GUI <[email protected]>
Signed-off-by: seteiro <[email protected]>
Co-authored-by: seteiro <[email protected]>

2 files changed, 16 insertions, 11 deletions

diff --git a/components/drivers/clock_time/SConscript b/components/drivers/clock_time/SConscript
index 111449276a..386ce7135d 100644
--- a/components/drivers/clock_time/SConscript
+++ b/components/drivers/clock_time/SConscript
@@ -25,7 +25,12 @@ if os.path.isdir(arch_dir):
     arch_list = os.listdir(arch_dir)
     if rtconfig.ARCH in arch_list:
         cpu_dir = os.path.join(arch_dir, rtconfig.ARCH, rtconfig.CPU)
-        if os.path.exists(cpu_dir):
+        if rtconfig.ARCH == 'risc-v':
+            if GetDepend('RT_USING_RISCV_NEW_COMMON'):
+                src += Glob("arch/risc-v/*.c")
+            elif os.path.exists(cpu_dir):
+                src += Glob("arch/%s/%s/*.c" % (rtconfig.ARCH, rtconfig.CPU))
+        elif os.path.exists(cpu_dir):
             src += Glob("arch/%s/%s/*.c" % (rtconfig.ARCH, rtconfig.CPU))
         else:
             src += Glob("arch/%s/*.c" % rtconfig.ARCH)
diff --git a/components/drivers/clock_time/arch/risc-v/virt64/cputimer.c b/components/drivers/clock_time/arch/risc-v/cputimer.c
index 7921716b7f..8941830f77 100644
--- a/components/drivers/clock_time/arch/risc-v/virt64/cputimer.c
+++ b/components/drivers/clock_time/arch/risc-v/cputimer.c
@@ -1,40 +1,40 @@
 /*
- * Copyright (c) 2006-2023, RT-Thread Development Team
+ * Copyright (c) 2006-2025, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2023-07-10     xqyjlj       The first version.
+ * 2025-04-20     GuEe-GUI     Port to common RISC-V timer.
  */
 
 #include <drivers/clock_time.h>
+#include <riscv_timer.h>
 
-static volatile unsigned long _init_cnt = 0;
+static volatile rt_uint64_t _init_cnt = 0;
 static rt_bool_t _riscv_clock_registered = RT_FALSE;
 static struct rt_clock_time_device _riscv_clock_dev;
 
-extern rt_uint64_t rt_hw_get_clock_timer_freq(void);
-
 static rt_uint64_t _riscv_clock_get_freq(struct rt_clock_time_device *dev)
 {
     RT_UNUSED(dev);
-    return rt_hw_get_clock_timer_freq();
+
+    return riscv_timer_get_frequency();
 }
 
 static rt_uint64_t _riscv_clock_get_counter(struct rt_clock_time_device *dev)
 {
-    unsigned long time_elapsed;
-
     RT_UNUSED(dev);
-    __asm__ __volatile__("rdtime %0" : "=r"(time_elapsed));
-    return (rt_uint64_t)(time_elapsed - _init_cnt);
+
+    return riscv_timer_rdtime() - _init_cnt;
 }
 
 static rt_err_t _riscv_clock_set_timeout(struct rt_clock_time_device *dev, rt_uint64_t delta)
 {
     RT_UNUSED(dev);
     RT_UNUSED(delta);
+
     return -RT_ENOSYS;
 }
 
@@ -47,7 +47,7 @@ static const struct rt_clock_time_ops _riscv_clock_ops =
 
 void rt_clock_time_source_init(void)
 {
-    __asm__ __volatile__("rdtime %0" : "=r"(_init_cnt));
+    _init_cnt = riscv_timer_rdtime();
 
     if (!_riscv_clock_registered)
     {