[ARCH/RISC-V] Next RISC-V (#10320)

* [libcpu][risc-v] Refactor the RISC-V architecture port

Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.

- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration

Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.

Signed-off-by: GuEe-GUI <[email protected]>

* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk

Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.

Signed-off-by: seteiro <[email protected]>

* [libcpu][risc-v] Fix per-CPU page table mapping

- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings

Signed-off-by: GuEe-GUI <[email protected]>

---------

Signed-off-by: GuEe-GUI <[email protected]>
Signed-off-by: seteiro <[email protected]>
Co-authored-by: seteiro <[email protected]>

2 files changed, 49 insertions, 4 deletions

diff --git a/components/lwp/arch/risc-v/rv64/lwp_arch.c b/components/lwp/arch/risc-v/rv64/lwp_arch.c
index 62383f91fa..d14163be32 100644
--- a/components/lwp/arch/risc-v/rv64/lwp_arch.c
+++ b/components/lwp/arch/risc-v/rv64/lwp_arch.c
@@ -34,7 +34,11 @@
 #include <page.h>
 
 #include <cpuport.h>
+#ifdef RT_USING_RISCV_NEW_COMMON
+#include <csr.h>
+#else
 #include <encoding.h>
+#endif
 #include <stack.h>
 #include <cache.h>
 
@@ -113,7 +117,11 @@ int arch_user_space_init(struct rt_lwp *lwp)
 
 void *arch_kernel_mmu_table_get(void)
 {
+#if defined(RT_USING_RISCV_NEW_COMMON) && defined(RT_USING_SMP) && RT_CPUS_NR > 1
+    return (void *)((char *)MMUTable + rt_hw_cpu_id() * ARCH_PAGE_SIZE);
+#else
     return (void *)((char *)MMUTable);
+#endif
 }
 
 void arch_user_space_free(struct rt_lwp *lwp)
@@ -165,15 +173,25 @@ int arch_set_thread_context(void (*exit)(void), void *new_thread_stack,
     RT_ASSERT(new_thread_stack != RT_NULL);
     RT_ASSERT(thread_sp != RT_NULL);
     struct rt_hw_stack_frame *syscall_frame;
+#ifdef RT_USING_RISCV_NEW_COMMON
+    struct rt_hw_switch_frame *frame;
+#else
     struct rt_hw_stack_frame *thread_frame;
+#endif
 
     rt_uint8_t *stk;
+#ifndef RT_USING_RISCV_NEW_COMMON
     rt_uint8_t *syscall_stk;
+#endif
 
     stk = (rt_uint8_t *)new_thread_stack;
     /* reserve syscall context, all the registers are copyed from parent */
+#ifdef RT_USING_RISCV_NEW_COMMON
+    stk -= CTX_ALL_REG_NR * sizeof(void *);
+#else
     stk -= CTX_REG_NR * REGBYTES;
     syscall_stk = stk;
+#endif
 
     syscall_frame = (struct rt_hw_stack_frame *)stk;
 
@@ -191,6 +209,15 @@ int arch_set_thread_context(void (*exit)(void), void *new_thread_stack,
     rt_thread_t thread = rt_container_of((unsigned long)thread_sp, struct rt_thread, sp);
     syscall_frame->tp = (rt_ubase_t)thread->thread_idr;
 
+#ifdef RT_USING_RISCV_NEW_COMMON
+    frame = (struct rt_hw_switch_frame *)((rt_ubase_t)stk - sizeof(*frame));
+    rt_memset(frame, 0, sizeof(*frame));
+
+    frame->regs[RT_HW_SWITCH_CONTEXT_RA] = (rt_ubase_t)exit;
+    frame->regs[RT_HW_SWITCH_CONTEXT_XSTATUS] = (csr_read(CSR_STATUS) | SR_PP) & ~SR_IE;
+
+    stk = (void *)frame;
+#else
 #ifdef ARCH_USING_NEW_CTX_SWITCH
     extern void *_rt_hw_stack_init(rt_ubase_t *sp, rt_ubase_t ra, rt_ubase_t sstatus);
     rt_ubase_t sstatus = read_csr(sstatus) | SSTATUS_SPP;
@@ -221,6 +248,7 @@ int arch_set_thread_context(void (*exit)(void), void *new_thread_stack,
     thread_frame->user_sp_exc_stack = (rt_ubase_t)syscall_stk;
 
 #endif /* ARCH_USING_NEW_CTX_SWITCH */
+#endif /* RT_USING_RISCV_NEW_COMMON */
     /* save new stack top */
     *thread_sp = (void *)stk;
 
diff --git a/components/lwp/arch/risc-v/rv64/lwp_gcc.S b/components/lwp/arch/risc-v/rv64/lwp_gcc.S
index d9f3a29299..b74abe5da1 100644
--- a/components/lwp/arch/risc-v/rv64/lwp_gcc.S
+++ b/components/lwp/arch/risc-v/rv64/lwp_gcc.S
@@ -19,10 +19,27 @@
 #define __ASSEMBLY__
 #endif /* __ASSEMBLY__ */
 
+#ifdef RT_USING_RISCV_NEW_COMMON
+#include "asm.h"
+#include "csr.h"
+
+#define LOAD                REG_L
+#define STORE               REG_S
+#define REGBYTES            SZREG
+#define CTX_REG_NR          CTX_ALL_REG_NR
+#define FRAME_OFF_SSTATUS   FRAME_OFF_XSTATUS
+#define SSTATUS_SPP         SR_PP
+#define SSTATUS_SIE         SR_IE
+#define SSTATUS_SPIE        SR_PIE
+#define sstatus             CSR_STATUS
+#define sscratch            CSR_SCRATCH
+#define sepc                CSR_EPC
+#else
 #include "cpuport.h"
 #include "encoding.h"
 #include "stackframe.h"
 #include "asm-generic.h"
+#endif
 
 .section      .text.lwp
 
@@ -267,13 +284,13 @@ copy_context_loop:
     LOAD t0, 0(t1)
     STORE t0, 0(t2)
     addi s0, s0, -1
-    addi t1, t1, 8
-    addi t2, t2, 8
+    addi t1, t1, REGBYTES
+    addi t2, t2, REGBYTES
     bnez s0, copy_context_loop
 #endif /* ARCH_USING_NEW_CTX_SWITCH */
 
     /* fetch SYSCALL ID */
-    LOAD a7, 17 * REGBYTES(sp)
+    LOAD a7, FRAME_OFF_A7(sp)
     addi a7, a7, -0xfe
     beqz a7, arch_signal_quit
 
@@ -307,7 +324,7 @@ dont_ret_to_user:
     call  lwp_user_setting_restore
 
     /* after restore the reg `tp`, need modify context */
-    STORE tp, 4 * REGBYTES(sp)
+    STORE tp, FRAME_OFF_TP(sp)
 #endif
 
     //restore context