[ARCH/RISC-V] Next RISC-V (#10320)

* [libcpu][risc-v] Refactor the RISC-V architecture port

Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration.

- use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection
- unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling
- add PLIC, CLIC, ACLINT, APLIC and IMSIC support
- map physical hart IDs to contiguous logical CPU IDs
- add T-Head vendor overrides while preserving legacy ports
- migrate qemu-virt64-riscv with RV32 and RV64 support
- update clock_time, MM, LWP, OFW, PCI and Rust integration

Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON.

Signed-off-by: GuEe-GUI <[email protected]>

* [libcpu][risc-v] skip disabled CPU nodes in early FDT walk

Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child
without checking status, so disabled cores still joined hart registration
and MMU capability probing. Skip nodes that are not okay/ok via
rt_fdt_device_is_available() before reading reg or mmu-type.

Signed-off-by: seteiro <[email protected]>

* [libcpu][risc-v] Fix per-CPU page table mapping

- reuse existing non-leaf page table entries when mapping per-CPU areas
- reject leaf entry conflicts instead of overwriting mappings

Signed-off-by: GuEe-GUI <[email protected]>

---------

Signed-off-by: GuEe-GUI <[email protected]>
Signed-off-by: seteiro <[email protected]>
Co-authored-by: seteiro <[email protected]>

1 files changed, 8 insertions, 1 deletions

diff --git a/components/mm/SConscript b/components/mm/SConscript
index f90f540ce2..cc205119f8 100644
--- a/components/mm/SConscript
+++ b/components/mm/SConscript
@@ -4,7 +4,14 @@ from building import *
 group = []
 cwd = GetCurrentDir()
 
-if GetDepend('ARCH_ARM_CORTEX_A') or GetDepend('ARCH_ARMV8') or GetDepend('ARCH_RISCV64'):
+new_riscv_common = GetDepend('RT_USING_RISCV_NEW_COMMON')
+legacy_mmu_arch = (GetDepend('ARCH_ARM_CORTEX_A') or
+                   GetDepend('ARCH_ARMV8') or
+                   (GetDepend('ARCH_RISCV64') and not new_riscv_common))
+new_riscv_mmu_arch = (new_riscv_common and
+                      GetDepend('ARCH_MM_MMU'))
+
+if legacy_mmu_arch or new_riscv_mmu_arch:
     src = Glob('*.c') + Glob('*_gcc.S')
     SrcRemove(src, ['ioremap-nommu.c'])
     if not GetDepend('RT_USING_MEMBLOCK'):