diff options
| author | Bernard Xiong <[email protected]> | 2019-03-25 21:58:48 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2019-03-25 21:58:48 +0800 |
| commit | 94e7f7316b0ece92ae1441fb3dd86b3caedb3388 (patch) | |
| tree | 7e7e4457888b509d96bf74312ec5952dc5b7169e /components | |
| parent | bc6117b4e5b49bb8a3c50870e89ac439f0d66d06 (diff) | |
| parent | 2eb1bef773e099ac93ec74dba7ec216bdf61597c (diff) | |
Merge pull request #2503 from qz721/libcpu_cortex_a
Make 'qemu-vexpress-a9' and 'imx6ul' use the same libcpu code.
Diffstat (limited to 'components')
| -rw-r--r-- | components/lwp/SConscript | 2 | ||||
| -rw-r--r-- | components/lwp/arch/arm/cortex-a/lwp_gcc.S | 70 |
2 files changed, 71 insertions, 1 deletions
diff --git a/components/lwp/SConscript b/components/lwp/SConscript index d3b799257b..f151f3b92e 100644 --- a/components/lwp/SConscript +++ b/components/lwp/SConscript @@ -5,7 +5,7 @@ cwd = GetCurrentDir() src = [] CPPPATH = [cwd] -support_arch = {"arm": ["cortex-m3", "cortex-m4", "cortex-m7", "arm926", "cortex-a9"]} +support_arch = {"arm": ["cortex-m3", "cortex-m4", "cortex-m7", "arm926", "cortex-a"]} platform_file = {'armcc': 'rvds.S', 'gcc': 'gcc.S', 'iar': 'iar.S'} if rtconfig.PLATFORM in platform_file.keys(): # support platforms diff --git a/components/lwp/arch/arm/cortex-a/lwp_gcc.S b/components/lwp/arch/arm/cortex-a/lwp_gcc.S new file mode 100644 index 0000000000..6c89152b0c --- /dev/null +++ b/components/lwp/arch/arm/cortex-a/lwp_gcc.S @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2006-2018, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2018-12-10 Jesven first version + */ + +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_MON 0x16 +#define Mode_ABT 0x17 +#define Mode_UDF 0x1B +#define Mode_SYS 0x1F + +#define A_Bit 0x100 +#define I_Bit 0x80 @; when I bit is set, IRQ is disabled +#define F_Bit 0x40 @; when F bit is set, FIQ is disabled +#define T_Bit 0x20 + +.cpu cortex-a9 +.syntax unified +.text + +/* + * void lwp_user_entry(args, text, data); + */ +.global lwp_user_entry +.type lwp_user_entry, % function +lwp_user_entry: + mrs r9, cpsr + bic r9, #0x1f + orr r9, #Mode_USR + cpsid i + msr spsr, r9 + + /* set data address. */ + mov r9, r2 + movs pc, r1 + +/* + * void SVC_Handler(void); + */ +.global SVC_Handler +.type SVC_Handler, % function +SVC_Handler: + push {lr} + mrs lr, spsr + push {r4, r5, lr} + cpsie i + + push {r0 - r3, r12} + and r0, r7, #0xff + bl lwp_get_sys_api + cmp r0, #0 /* r0 = api */ + mov lr, r0 + pop {r0 - r3, r12} + beq svc_exit + blx lr + +svc_exit: + cpsid i + pop {r4, r5, lr} + msr spsr_cxsf, lr + pop {lr} + movs pc, lr |