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authorWayne Lin <[email protected]>2022-01-10 12:36:11 +0800
committerWayne Lin <[email protected]>2022-01-10 12:36:11 +0800
commit715eecd3eb6cfbbc95aba4fdf932db2e1a7698fb (patch)
tree111003eb53eaa4a789729792a622d2abfd602031 /libcpu/aarch64/common/cache_ops.c
parent6d2a7d00db2808f26b96efaebfa3aa18b6fd47b8 (diff)
parent5206f6504018d1e1978e1c547f6a5b782d505be5 (diff)
Merge branch 'master' of https://github.com/RT-Thread/rt-thread into nuvoton
# Conflicts: # bsp/nuvoton/nk-980iot/.config # bsp/nuvoton/nk-n9h30/.config # bsp/nuvoton/nk-rtu980/.config # bsp/nuvoton/numaker-iot-m487/.config # bsp/nuvoton/numaker-m2354/.config # bsp/nuvoton/numaker-pfm-m487/.config
Diffstat (limited to 'libcpu/aarch64/common/cache_ops.c')
-rw-r--r--libcpu/aarch64/common/cache_ops.c70
1 files changed, 70 insertions, 0 deletions
diff --git a/libcpu/aarch64/common/cache_ops.c b/libcpu/aarch64/common/cache_ops.c
new file mode 100644
index 0000000000..517845e924
--- /dev/null
+++ b/libcpu/aarch64/common/cache_ops.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2006-2021, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2021-12-28 GuEe-GUI the first version
+ */
+
+#include <rthw.h>
+#include <rtdef.h>
+
+void __asm_flush_dcache_all(void);
+void __asm_invalidate_dcache_all(void);
+void __asm_flush_dcache_range(unsigned long start, unsigned long end);
+void __asm_invalidate_dcache_range(unsigned long start, unsigned long end);
+
+void __asm_invalidate_icache_all(void);
+void __asm_invalidate_icache_range(unsigned long start, unsigned long end);
+
+void rt_hw_dcache_flush_all(void)
+{
+ __asm_flush_dcache_all();
+}
+
+void rt_hw_dcache_invalidate_all(void)
+{
+ __asm_invalidate_dcache_all();
+}
+
+void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size)
+{
+ __asm_flush_dcache_range(start_addr, start_addr + size);
+}
+
+void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size)
+{
+ __asm_invalidate_dcache_range(start_addr, start_addr + size);
+}
+
+void rt_hw_icache_invalidate_all()
+{
+ __asm_invalidate_icache_all();
+}
+
+void rt_hw_icache_invalidate_range(unsigned long start_addr, int size)
+{
+ __asm_invalidate_icache_range(start_addr, start_addr + size);
+}
+
+void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
+{
+ if (ops == RT_HW_CACHE_INVALIDATE)
+ {
+ rt_hw_icache_invalidate_range((unsigned long)addr, size);
+ }
+}
+
+void rt_hw_cpu_dcache_ops(int ops, void *addr, int size)
+{
+ if (ops == RT_HW_CACHE_FLUSH)
+ {
+ rt_hw_dcache_flush_range((unsigned long)addr, size);
+ }
+ else if (ops == RT_HW_CACHE_INVALIDATE)
+ {
+ rt_hw_dcache_invalidate_range((unsigned long)addr, size);
+ }
+}