feat: arm64: generic implementation of vector irq (#9336)

feat: overall implementation of vector irq

This patch generalize the irq handling on up/mp system by adding the
`rt_hw_irq_exit()` & `rt_hw_vector_irq_sched()` API.

Changes:
- Added `rt_hw_irq_exit()` and `rt_hw_vector_irq_sched()` APIs for unified IRQ management.
- Refactored assembly code for both UP and MP systems to use the new IRQ handling flow.
- Removed redundant code and optimized exception handling paths.

Signed-off-by: Shell <[email protected]>

2 files changed, 27 insertions, 51 deletions

diff --git a/libcpu/aarch64/common/include/asm-generic.h b/libcpu/aarch64/common/include/asm-generic.h
index 362ef8f525..d2d32ce73f 100644
--- a/libcpu/aarch64/common/include/asm-generic.h
+++ b/libcpu/aarch64/common/include/asm-generic.h
@@ -23,6 +23,14 @@
     .cfi_endproc;               \
     .size name, .-name;
 
+#define TRACE_SYMBOL(name)
+
+.macro NEVER_RETURN
+#ifdef RT_USING_DEBUG
+    b       .
+#endif /* RT_USING_DEBUG */
+.endm
+
 .macro GET_THREAD_SELF, dst:req
 #ifdef ARCH_USING_HW_THREAD_SELF
     mrs     x0, tpidr_el1
diff --git a/libcpu/aarch64/common/include/vector_gcc.h b/libcpu/aarch64/common/include/vector_gcc.h
index 8fa5c04aec..31c532316e 100644
--- a/libcpu/aarch64/common/include/vector_gcc.h
+++ b/libcpu/aarch64/common/include/vector_gcc.h
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2024-03-28     Shell        Move vector handling codes from context_gcc.S
+ * 2024-04-08     Shell        Optimizing exception switch between u-space/kernel,
  */
 
 #ifndef __ARM64_INC_VECTOR_H__
@@ -45,8 +46,6 @@
     mrs     x2, elr_el1
 
     stp     x2, x3, [sp, #-0x10]!
-
-    mov     x0, sp   /* Move SP into X0 for saving. */
 .endm
 
 #ifdef RT_USING_SMP
@@ -55,60 +54,29 @@
 #include "../up/context_gcc.h"
 #endif
 
-.macro RESTORE_IRQ_CONTEXT_WITHOUT_MMU_SWITCH
-    /* the SP is already ok */
-    ldp     x2, x3, [sp], #0x10  /* SPSR and ELR. */
-
-    tst     x3, #0x1f
-    msr     spsr_el1, x3
-    msr     elr_el1, x2
-
-    ldp     x29, x30, [sp], #0x10
-    msr     sp_el0, x29
-    ldp     x28, x29, [sp], #0x10
-    msr     fpcr, x28
-    msr     fpsr, x29
-    ldp     x28, x29, [sp], #0x10
-    ldp     x26, x27, [sp], #0x10
-    ldp     x24, x25, [sp], #0x10
-    ldp     x22, x23, [sp], #0x10
-    ldp     x20, x21, [sp], #0x10
-    ldp     x18, x19, [sp], #0x10
-    ldp     x16, x17, [sp], #0x10
-    ldp     x14, x15, [sp], #0x10
-    ldp     x12, x13, [sp], #0x10
-    ldp     x10, x11, [sp], #0x10
-    ldp     x8, x9, [sp], #0x10
-    ldp     x6, x7, [sp], #0x10
-    ldp     x4, x5, [sp], #0x10
-    ldp     x2, x3, [sp], #0x10
-    ldp     x0, x1, [sp], #0x10
-    RESTORE_FPU sp
+.macro SAVE_USER_CTX, eframex, tmpx
 #ifdef RT_USING_SMART
-    beq     arch_ret_to_user
-#endif
-    eret
-.endm
-
-.macro SAVE_USER_CTX
-    mrs     x1, spsr_el1
-    and     x1, x1, 0xf
-    cmp     x1, xzr
-
-    bne     1f
-    bl      lwp_uthread_ctx_save
-    ldp     x0, x1, [sp]
+    mrs     \tmpx, spsr_el1
+    and     \tmpx, \tmpx, 0xf
+    cbz     \tmpx, 1f
+    b       2f
 1:
+    mov     x0, \eframex
+    bl      lwp_uthread_ctx_save
+2:
+#endif /* RT_USING_SMART */
 .endm
 
-.macro RESTORE_USER_CTX, ctx
-    ldr     x1, [\ctx, #CONTEXT_OFFSET_SPSR_EL1]
-    and     x1, x1, 0x1f
-    cmp     x1, xzr
-
-    bne     1f
-    bl      lwp_uthread_ctx_restore
+.macro RESTORE_USER_CTX, eframex, tmpx
+#ifdef RT_USING_SMART
+    ldr     \tmpx, [\eframex, #CONTEXT_OFFSET_SPSR_EL1]
+    and     \tmpx, \tmpx, 0x1f
+    cbz     \tmpx, 1f
+    b       2f
 1:
+    bl      lwp_uthread_ctx_restore
+2:
+#endif /* RT_USING_SMART */
 .endm
 
 #endif /* __ARM64_INC_VECTOR_H__ */