[libcpu/arm64] feat: Trimming General Context

This patch focuses on the ARM64 general context handling code.
The modifications are aimed at enhancing performance by simplifying
context save/restore operations.

Changes include:
- Adjusted stack alignment in `arch_set_thread_context` function.
- Updated `lwp_gcc.S` to reset frame pointer and link register.
- Refined `rt_hw_backtrace_frame_unwind` to handle user space address checks.
- Added `GET_THREAD_SELF` macro in `asm-generic.h`.
- Simplified context saving/restoring in `context_gcc.h` and related files.
- Optimized `rt_hw_context_switch_interrupt` and related assembly routines.

Signed-off-by: Shell <[email protected]>

1 files changed, 16 insertions, 38 deletions

diff --git a/libcpu/aarch64/common/stack.c b/libcpu/aarch64/common/stack.c
index c554ab077d..e3e8ccbc9d 100644
--- a/libcpu/aarch64/common/stack.c
+++ b/libcpu/aarch64/common/stack.c
@@ -41,44 +41,22 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
         *(rt_uint128_t *)stk = (rt_uint128_t) { 0 };
     }
 
-    *(--stk) = (rt_ubase_t)0;           /* X1 */
-    *(--stk) = (rt_ubase_t)parameter;   /* X0 */
-    *(--stk) = (rt_ubase_t)3;           /* X3 */
-    *(--stk) = (rt_ubase_t)2;           /* X2 */
-    *(--stk) = (rt_ubase_t)5;           /* X5 */
-    *(--stk) = (rt_ubase_t)4;           /* X4 */
-    *(--stk) = (rt_ubase_t)7;           /* X7 */
-    *(--stk) = (rt_ubase_t)6;           /* X6 */
-    *(--stk) = (rt_ubase_t)9;           /* X9 */
-    *(--stk) = (rt_ubase_t)8;           /* X8 */
-    *(--stk) = (rt_ubase_t)11;          /* X11 */
-    *(--stk) = (rt_ubase_t)10;          /* X10 */
-    *(--stk) = (rt_ubase_t)13;          /* X13 */
-    *(--stk) = (rt_ubase_t)12;          /* X12 */
-    *(--stk) = (rt_ubase_t)15;          /* X15 */
-    *(--stk) = (rt_ubase_t)14;          /* X14 */
-    *(--stk) = (rt_ubase_t)17;          /* X17 */
-    *(--stk) = (rt_ubase_t)16;          /* X16 */
-    *(--stk) = (rt_ubase_t)tentry;      /* X19, 1st param */
-    *(--stk) = (rt_ubase_t)18;          /* X18 */
-    *(--stk) = (rt_ubase_t)21;          /* X21 */
-    *(--stk) = (rt_ubase_t)texit;       /* X20, 2nd param */
-    *(--stk) = (rt_ubase_t)23;          /* X23 */
-    *(--stk) = (rt_ubase_t)22;          /* X22 */
-    *(--stk) = (rt_ubase_t)25;          /* X25 */
-    *(--stk) = (rt_ubase_t)24;          /* X24 */
-    *(--stk) = (rt_ubase_t)27;          /* X27 */
-    *(--stk) = (rt_ubase_t)26;          /* X26 */
-    *(--stk) = (rt_ubase_t)0;           /* X29 - addr 0 as AAPCS64 specified */
-    *(--stk) = (rt_ubase_t)28;          /* X28 */
-    *(--stk) = (rt_ubase_t)0;           /* FPSR */
-    *(--stk) = (rt_ubase_t)0;           /* FPCR */
-    *(--stk) = (rt_ubase_t)0;           /* X30 - procedure call link register. */
-    *(--stk) = (rt_ubase_t)0;           /* sp_el0 */
-
-    *(--stk) = INITIAL_SPSR_EL1;
-
-    *(--stk) = (rt_ubase_t)_thread_start; /* Exception return address. */
+    *(--stk) = (rt_ubase_t)texit;           /* X20, 2nd param */
+    *(--stk) = (rt_ubase_t)tentry;          /* X19, 1st param */
+    *(--stk) = (rt_ubase_t)22;              /* X22 */
+    *(--stk) = (rt_ubase_t)parameter;       /* X21, 3rd param */
+    *(--stk) = (rt_ubase_t)24;              /* X24 */
+    *(--stk) = (rt_ubase_t)23;              /* X23 */
+    *(--stk) = (rt_ubase_t)26;              /* X26 */
+    *(--stk) = (rt_ubase_t)25;              /* X25 */
+    *(--stk) = (rt_ubase_t)28;              /* X28 */
+    *(--stk) = (rt_ubase_t)27;              /* X27 */
+    *(--stk) = (rt_ubase_t)0;               /* sp_el0 */
+    *(--stk) = (rt_ubase_t)0;               /* X29 - addr 0 as AAPCS64 specified */
+    *(--stk) = (rt_ubase_t)0;               /* FPSR */
+    *(--stk) = (rt_ubase_t)0;               /* FPCR */
+    *(--stk) = INITIAL_SPSR_EL1;            /* Save Processor States */
+    *(--stk) = (rt_ubase_t)_thread_start;   /* Exception return address. */
 
     /* return task's current stack address */
     return (rt_uint8_t *)stk;