[libcpu] auto formatted

15 files changed, 199 insertions, 199 deletions

diff --git a/libcpu/aarch64/common/armv8.h b/libcpu/aarch64/common/armv8.h
index 4350890544..77fb4de8a2 100644
--- a/libcpu/aarch64/common/armv8.h
+++ b/libcpu/aarch64/common/armv8.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,47 +14,47 @@
 /* the exception stack without VFP registers */
 struct rt_hw_exp_stack
 {
-	unsigned long long pc;
-	unsigned long long spsr;
-	unsigned long long x30;
-	unsigned long long xz;
-	unsigned long long x28;
-	unsigned long long x29;
-	unsigned long long x26;
-	unsigned long long x27;
-	unsigned long long x24;
-	unsigned long long x25;
-	unsigned long long x22;
-	unsigned long long x23;
-	unsigned long long x20;
-	unsigned long long x21;
-	unsigned long long x18;	
-	unsigned long long x19;
-	unsigned long long x16;
-	unsigned long long x17;
-	unsigned long long x14;
-	unsigned long long x15;
-	unsigned long long x12;
-	unsigned long long x13;
-	unsigned long long x10;
-	unsigned long long x11;
-	unsigned long long x8;
-	unsigned long long x9;
-	unsigned long long x6;
-	unsigned long long x7;
-	unsigned long long x4;
-	unsigned long long x5;
-	unsigned long long x2;
-	unsigned long long x3;
-	unsigned long long x0;
-	unsigned long long x1;
+    unsigned long long pc;
+    unsigned long long spsr;
+    unsigned long long x30;
+    unsigned long long xz;
+    unsigned long long x28;
+    unsigned long long x29;
+    unsigned long long x26;
+    unsigned long long x27;
+    unsigned long long x24;
+    unsigned long long x25;
+    unsigned long long x22;
+    unsigned long long x23;
+    unsigned long long x20;
+    unsigned long long x21;
+    unsigned long long x18;
+    unsigned long long x19;
+    unsigned long long x16;
+    unsigned long long x17;
+    unsigned long long x14;
+    unsigned long long x15;
+    unsigned long long x12;
+    unsigned long long x13;
+    unsigned long long x10;
+    unsigned long long x11;
+    unsigned long long x8;
+    unsigned long long x9;
+    unsigned long long x6;
+    unsigned long long x7;
+    unsigned long long x4;
+    unsigned long long x5;
+    unsigned long long x2;
+    unsigned long long x3;
+    unsigned long long x0;
+    unsigned long long x1;
 };
 
-#define SP_ELx						( ( unsigned long long ) 0x01 )
-#define SP_EL0						( ( unsigned long long ) 0x00 )
-#define PSTATE_EL1					( ( unsigned long long ) 0x04 )
-#define PSTATE_EL2					( ( unsigned long long ) 0x08 )
-#define PSTATE_EL3					( ( unsigned long long ) 0x0c )
+#define SP_ELx                      ( ( unsigned long long ) 0x01 )
+#define SP_EL0                      ( ( unsigned long long ) 0x00 )
+#define PSTATE_EL1                  ( ( unsigned long long ) 0x04 )
+#define PSTATE_EL2                  ( ( unsigned long long ) 0x08 )
+#define PSTATE_EL3                  ( ( unsigned long long ) 0x0c )
 
 rt_ubase_t rt_hw_get_current_el(void);
 void rt_hw_set_elx_env(void);
diff --git a/libcpu/aarch64/common/cp15.h b/libcpu/aarch64/common/cp15.h
index f3ffd6f857..e6d8626ab9 100644
--- a/libcpu/aarch64/common/cp15.h
+++ b/libcpu/aarch64/common/cp15.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -55,7 +55,7 @@ static inline void send_ipi_msg(int cpu, int ipi_vector)
 
 static inline void setup_bootstrap_addr(int cpu, int addr)
 {
-	CORE_MAILBOX3_SET(cpu) = addr;
+    CORE_MAILBOX3_SET(cpu) = addr;
 }
 
 static inline void enable_cpu_ipi_intr(int cpu)
@@ -65,7 +65,7 @@ static inline void enable_cpu_ipi_intr(int cpu)
 
 static inline void enable_cpu_timer_intr(int cpu)
 {
-	CORETIMER_INTCTL(cpu) = 0x8;
+    CORETIMER_INTCTL(cpu) = 0x8;
 }
 
 static inline void enable_cntv(void)
diff --git a/libcpu/aarch64/common/cpu.c b/libcpu/aarch64/common/cpu.c
index 84d3df2e8a..66b540a5e5 100644
--- a/libcpu/aarch64/common/cpu.c
+++ b/libcpu/aarch64/common/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c
index 1f4d868636..ec690a1cc6 100644
--- a/libcpu/aarch64/common/gic/gic_pl400.c
+++ b/libcpu/aarch64/common/gic/gic_pl400.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/aarch64/common/gic/gic_pl400.h b/libcpu/aarch64/common/gic/gic_pl400.h
index fa20846ea2..9ca4835b9a 100644
--- a/libcpu/aarch64/common/gic/gic_pl400.h
+++ b/libcpu/aarch64/common/gic/gic_pl400.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/aarch64/common/mmu.c b/libcpu/aarch64/common/mmu.c
index b799143084..2a41c4f813 100644
--- a/libcpu/aarch64/common/mmu.c
+++ b/libcpu/aarch64/common/mmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -52,7 +52,7 @@ void mmu_memset(char *dst, char v,  size_t len)
 }
 
 static unsigned long __page_off = 0;
-static unsigned long get_free_page(void) 
+static unsigned long get_free_page(void)
 {
     __page_off += 512;
     return (unsigned long)(main_tbl + __page_off);
@@ -128,7 +128,7 @@ void mmu_enable(void)
 
 }
 
-static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) 
+static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr)
 {
     int level;
     unsigned long* cur_lv_tbl = lv0_tbl;
@@ -136,22 +136,22 @@ static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned
     unsigned long off;
     int level_shift = 39;
 
-    if (va & (0x200000UL - 1)) 
+    if (va & (0x200000UL - 1))
     {
         return MMU_MAP_ERROR_VANOTALIGN;
     }
-    if (pa & (0x200000UL - 1)) 
+    if (pa & (0x200000UL - 1))
     {
         return MMU_MAP_ERROR_PANOTALIGN;
     }
-    for (level = 0; level < 2; level++) 
+    for (level = 0; level < 2; level++)
     {
         off = (va >> level_shift);
         off &= MMU_LEVEL_MASK;
-        if ((cur_lv_tbl[off] & 1) == 0) 
+        if ((cur_lv_tbl[off] & 1) == 0)
         {
             page = get_free_page();
-            if (!page) 
+            if (!page)
             {
                 return MMU_MAP_ERROR_NOPAGE;
             }
@@ -159,7 +159,7 @@ static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned
             cur_lv_tbl[off] = page | 0x3UL;
         }
         page = cur_lv_tbl[off];
-        if (!(page & 0x2)) 
+        if (!(page & 0x2))
         {
             //is block! error!
             return MMU_MAP_ERROR_CONFLICT;
@@ -239,8 +239,8 @@ static int level2shift(int level)
 static uint64_t *get_level_table(uint64_t *pte)
 {
     uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
-    
-    if (pte_type(pte) != PMD_TYPE_TABLE) 
+
+    if (pte_type(pte) != PMD_TYPE_TABLE)
     {
         table = create_table();
         set_table(pte, table);
@@ -259,10 +259,10 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
     int level = 0;
 
     addr = virt;
-    while (size) 
+    while (size)
     {
         table = &main_tbl[0];
-        for (level = 0; level < 4; level++) 
+        for (level = 0; level < 4; level++)
         {
             block_shift = level2shift(level);
             idx = addr >> block_shift;
@@ -270,7 +270,7 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att
             block_size = (uint64_t)(1L << block_shift);
             pte = table + idx;
 
-            if (size >= block_size && IS_ALIGNED(addr, block_size)) 
+            if (size >= block_size && IS_ALIGNED(addr, block_size))
             {
                 attr &= 0xfff0000000000ffcUL;
                 if(level != 3)
@@ -298,7 +298,7 @@ void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned
 
 void rt_hw_dcache_enable(void)
 {
-    if (!(get_sctlr() & CR_M)) 
+    if (!(get_sctlr() & CR_M))
     {
         rt_kprintf("please init mmu!\n");
     }
@@ -364,4 +364,4 @@ void rt_hw_icache_invalidate_all(void)
 void rt_hw_icache_disable(void)
 {
     set_sctlr(get_sctlr() & ~CR_I);
-}
\ No newline at end of file
+}
diff --git a/libcpu/aarch64/common/mmu.h b/libcpu/aarch64/common/mmu.h
index 6a66472c79..f3261c3a1d 100644
--- a/libcpu/aarch64/common/mmu.h
+++ b/libcpu/aarch64/common/mmu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/aarch64/cortex-a53/interrupt.c b/libcpu/aarch64/cortex-a53/interrupt.c
index a412ca1953..4a5d502a3c 100644
--- a/libcpu/aarch64/cortex-a53/interrupt.c
+++ b/libcpu/aarch64/cortex-a53/interrupt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -7,7 +7,7 @@
  * Date           Author       Notes
  * 2018/5/3       Bernard      first version
  * 2019-07-28     zdzn         add smp support
- * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues, 
+ * 2019-08-09     zhangjun     fixup the problem of smp startup and scheduling issues,
  *                             write addr to mailbox3 to startup smp, and we use mailbox0 for ipi
  */
 
@@ -160,15 +160,15 @@ void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask)
     }
     if(cpu_mask & 0x2)
     {
-    	send_ipi_msg(1, ipi_vector);
+        send_ipi_msg(1, ipi_vector);
     }
     if(cpu_mask & 0x4)
     {
-    	send_ipi_msg(2, ipi_vector);
+        send_ipi_msg(2, ipi_vector);
     }
     if(cpu_mask & 0x8)
     {
-    	send_ipi_msg(3, ipi_vector);
+        send_ipi_msg(3, ipi_vector);
     }
     __DSB();
 }
diff --git a/libcpu/aarch64/cortex-a53/interrupt.h b/libcpu/aarch64/cortex-a53/interrupt.h
index 8e741ed4e6..94a455550d 100644
--- a/libcpu/aarch64/cortex-a53/interrupt.h
+++ b/libcpu/aarch64/cortex-a53/interrupt.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/aarch64/cortex-a53/stack.c b/libcpu/aarch64/cortex-a53/stack.c
index 68222c2c67..751793d7a3 100644
--- a/libcpu/aarch64/cortex-a53/stack.c
+++ b/libcpu/aarch64/cortex-a53/stack.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -21,70 +21,70 @@
  * This function will initialize thread stack
  *
  * @param tentry the entry of thread
- * @param parameter the parameter of entry 
+ * @param parameter the parameter of entry
  * @param stack_addr the beginning stack address
  * @param texit the function will be called when thread exit
  *
  * @return stack address
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
+    rt_uint8_t *stack_addr, void *texit)
 {
-	rt_ubase_t *stk;
-	rt_ubase_t current_el;
+    rt_ubase_t *stk;
+    rt_ubase_t current_el;
 
-	stk 	 = (rt_ubase_t*)stack_addr;
+    stk      = (rt_ubase_t*)stack_addr;
 
-	*(--stk) = ( rt_ubase_t ) 11;			/* X1 */
-	*(--stk) = ( rt_ubase_t ) parameter; 	/* X0 */
-	*(--stk) = ( rt_ubase_t ) 33;			/* X3 */
-	*(--stk) = ( rt_ubase_t ) 22;			/* X2 */
-	*(--stk) = ( rt_ubase_t ) 55;			/* X5 */
-	*(--stk) = ( rt_ubase_t ) 44;			/* X4 */
-	*(--stk) = ( rt_ubase_t ) 77;			/* X7 */
-	*(--stk) = ( rt_ubase_t ) 66;			/* X6 */
-	*(--stk) = ( rt_ubase_t ) 99;			/* X9 */
-	*(--stk) = ( rt_ubase_t ) 88;			/* X8 */
-	*(--stk) = ( rt_ubase_t ) 11;			/* X11 */
-	*(--stk) = ( rt_ubase_t ) 10;			/* X10 */
-	*(--stk) = ( rt_ubase_t ) 13;			/* X13 */
-	*(--stk) = ( rt_ubase_t ) 12;			/* X12 */
-	*(--stk) = ( rt_ubase_t ) 15;			/* X15 */
-	*(--stk) = ( rt_ubase_t ) 14;			/* X14 */
-	*(--stk) = ( rt_ubase_t ) 17;			/* X17 */
-	*(--stk) = ( rt_ubase_t ) 16;			/* X16 */
-	*(--stk) = ( rt_ubase_t ) 19;			/* X19 */
-	*(--stk) = ( rt_ubase_t ) 18;			/* X18 */
-	*(--stk) = ( rt_ubase_t ) 21;			/* X21 */
-	*(--stk) = ( rt_ubase_t ) 20;			/* X20 */
-	*(--stk) = ( rt_ubase_t ) 23;			/* X23 */
-	*(--stk) = ( rt_ubase_t ) 22;			/* X22 */
-	*(--stk) = ( rt_ubase_t ) 25;			/* X25 */
-	*(--stk) = ( rt_ubase_t ) 24;			/* X24 */
-	*(--stk) = ( rt_ubase_t ) 27;			/* X27 */
-	*(--stk) = ( rt_ubase_t ) 26;			/* X26 */
-	*(--stk) = ( rt_ubase_t ) 29;			/* X29 */
-	*(--stk) = ( rt_ubase_t ) 28;			/* X28 */
-	*(--stk) = ( rt_ubase_t ) 0;			/* XZR - has no effect, used so there are an even number of registers. */
-	*(--stk) = ( rt_ubase_t ) texit;		/* X30 - procedure call link register. */
+    *(--stk) = ( rt_ubase_t ) 11;           /* X1 */
+    *(--stk) = ( rt_ubase_t ) parameter;    /* X0 */
+    *(--stk) = ( rt_ubase_t ) 33;           /* X3 */
+    *(--stk) = ( rt_ubase_t ) 22;           /* X2 */
+    *(--stk) = ( rt_ubase_t ) 55;           /* X5 */
+    *(--stk) = ( rt_ubase_t ) 44;           /* X4 */
+    *(--stk) = ( rt_ubase_t ) 77;           /* X7 */
+    *(--stk) = ( rt_ubase_t ) 66;           /* X6 */
+    *(--stk) = ( rt_ubase_t ) 99;           /* X9 */
+    *(--stk) = ( rt_ubase_t ) 88;           /* X8 */
+    *(--stk) = ( rt_ubase_t ) 11;           /* X11 */
+    *(--stk) = ( rt_ubase_t ) 10;           /* X10 */
+    *(--stk) = ( rt_ubase_t ) 13;           /* X13 */
+    *(--stk) = ( rt_ubase_t ) 12;           /* X12 */
+    *(--stk) = ( rt_ubase_t ) 15;           /* X15 */
+    *(--stk) = ( rt_ubase_t ) 14;           /* X14 */
+    *(--stk) = ( rt_ubase_t ) 17;           /* X17 */
+    *(--stk) = ( rt_ubase_t ) 16;           /* X16 */
+    *(--stk) = ( rt_ubase_t ) 19;           /* X19 */
+    *(--stk) = ( rt_ubase_t ) 18;           /* X18 */
+    *(--stk) = ( rt_ubase_t ) 21;           /* X21 */
+    *(--stk) = ( rt_ubase_t ) 20;           /* X20 */
+    *(--stk) = ( rt_ubase_t ) 23;           /* X23 */
+    *(--stk) = ( rt_ubase_t ) 22;           /* X22 */
+    *(--stk) = ( rt_ubase_t ) 25;           /* X25 */
+    *(--stk) = ( rt_ubase_t ) 24;           /* X24 */
+    *(--stk) = ( rt_ubase_t ) 27;           /* X27 */
+    *(--stk) = ( rt_ubase_t ) 26;           /* X26 */
+    *(--stk) = ( rt_ubase_t ) 29;           /* X29 */
+    *(--stk) = ( rt_ubase_t ) 28;           /* X28 */
+    *(--stk) = ( rt_ubase_t ) 0;            /* XZR - has no effect, used so there are an even number of registers. */
+    *(--stk) = ( rt_ubase_t ) texit;        /* X30 - procedure call link register. */
 
-	current_el = rt_hw_get_current_el();
+    current_el = rt_hw_get_current_el();
 
-	if(current_el == 3)
-	{
-		*(--stk) = INITIAL_SPSR_EL3;
-	}
-	else if(current_el == 2)
-	{
-		*(--stk) = INITIAL_SPSR_EL2;
-	}
-	else
-	{
-		*(--stk) = INITIAL_SPSR_EL1;
-	}
+    if(current_el == 3)
+    {
+        *(--stk) = INITIAL_SPSR_EL3;
+    }
+    else if(current_el == 2)
+    {
+        *(--stk) = INITIAL_SPSR_EL2;
+    }
+    else
+    {
+        *(--stk) = INITIAL_SPSR_EL1;
+    }
 
-	*(--stk) = ( rt_ubase_t ) tentry; 		/* Exception return address. */
+    *(--stk) = ( rt_ubase_t ) tentry;       /* Exception return address. */
 
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
 }
diff --git a/libcpu/aarch64/cortex-a53/trap.c b/libcpu/aarch64/cortex-a53/trap.c
index 41d4d620f6..d43e0e4d6a 100644
--- a/libcpu/aarch64/cortex-a53/trap.c
+++ b/libcpu/aarch64/cortex-a53/trap.c
@@ -1,8 +1,8 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
- * 
+ *
  * Date           Author       Notes
  * 2018-10-06     ZhaoXiaowei    the first version
  */
@@ -28,14 +28,14 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs)
     rt_kprintf("Execption:\n");
     rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
     rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
-	rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
-	rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
-	rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
-	rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
+    rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
+    rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
+    rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
+    rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
     rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
-	rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
-	rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
-	rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
+    rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
+    rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
+    rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
 }
 
 /**
@@ -57,7 +57,7 @@ void rt_hw_trap_error(struct rt_hw_exp_stack *regs)
 }
 
 #define GIC_ACK_INTID_MASK              (0x000003ff)
-#define CORE0_IRQ_SOURCE	            (0x40000060)
+#define CORE0_IRQ_SOURCE                (0x40000060)
 
 void rt_hw_trap_irq(void)
 {
diff --git a/libcpu/aarch64/cortex-a72/interrupt.c b/libcpu/aarch64/cortex-a72/interrupt.c
index 3b689dceb3..3ecb7750ad 100644
--- a/libcpu/aarch64/cortex-a72/interrupt.c
+++ b/libcpu/aarch64/cortex-a72/interrupt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/aarch64/cortex-a72/interrupt.h b/libcpu/aarch64/cortex-a72/interrupt.h
index 0d2d4867c7..72e69bd808 100644
--- a/libcpu/aarch64/cortex-a72/interrupt.h
+++ b/libcpu/aarch64/cortex-a72/interrupt.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/aarch64/cortex-a72/stack.c b/libcpu/aarch64/cortex-a72/stack.c
index 68222c2c67..751793d7a3 100644
--- a/libcpu/aarch64/cortex-a72/stack.c
+++ b/libcpu/aarch64/cortex-a72/stack.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2019, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -21,70 +21,70 @@
  * This function will initialize thread stack
  *
  * @param tentry the entry of thread
- * @param parameter the parameter of entry 
+ * @param parameter the parameter of entry
  * @param stack_addr the beginning stack address
  * @param texit the function will be called when thread exit
  *
  * @return stack address
  */
 rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
-	rt_uint8_t *stack_addr, void *texit)
+    rt_uint8_t *stack_addr, void *texit)
 {
-	rt_ubase_t *stk;
-	rt_ubase_t current_el;
+    rt_ubase_t *stk;
+    rt_ubase_t current_el;
 
-	stk 	 = (rt_ubase_t*)stack_addr;
+    stk      = (rt_ubase_t*)stack_addr;
 
-	*(--stk) = ( rt_ubase_t ) 11;			/* X1 */
-	*(--stk) = ( rt_ubase_t ) parameter; 	/* X0 */
-	*(--stk) = ( rt_ubase_t ) 33;			/* X3 */
-	*(--stk) = ( rt_ubase_t ) 22;			/* X2 */
-	*(--stk) = ( rt_ubase_t ) 55;			/* X5 */
-	*(--stk) = ( rt_ubase_t ) 44;			/* X4 */
-	*(--stk) = ( rt_ubase_t ) 77;			/* X7 */
-	*(--stk) = ( rt_ubase_t ) 66;			/* X6 */
-	*(--stk) = ( rt_ubase_t ) 99;			/* X9 */
-	*(--stk) = ( rt_ubase_t ) 88;			/* X8 */
-	*(--stk) = ( rt_ubase_t ) 11;			/* X11 */
-	*(--stk) = ( rt_ubase_t ) 10;			/* X10 */
-	*(--stk) = ( rt_ubase_t ) 13;			/* X13 */
-	*(--stk) = ( rt_ubase_t ) 12;			/* X12 */
-	*(--stk) = ( rt_ubase_t ) 15;			/* X15 */
-	*(--stk) = ( rt_ubase_t ) 14;			/* X14 */
-	*(--stk) = ( rt_ubase_t ) 17;			/* X17 */
-	*(--stk) = ( rt_ubase_t ) 16;			/* X16 */
-	*(--stk) = ( rt_ubase_t ) 19;			/* X19 */
-	*(--stk) = ( rt_ubase_t ) 18;			/* X18 */
-	*(--stk) = ( rt_ubase_t ) 21;			/* X21 */
-	*(--stk) = ( rt_ubase_t ) 20;			/* X20 */
-	*(--stk) = ( rt_ubase_t ) 23;			/* X23 */
-	*(--stk) = ( rt_ubase_t ) 22;			/* X22 */
-	*(--stk) = ( rt_ubase_t ) 25;			/* X25 */
-	*(--stk) = ( rt_ubase_t ) 24;			/* X24 */
-	*(--stk) = ( rt_ubase_t ) 27;			/* X27 */
-	*(--stk) = ( rt_ubase_t ) 26;			/* X26 */
-	*(--stk) = ( rt_ubase_t ) 29;			/* X29 */
-	*(--stk) = ( rt_ubase_t ) 28;			/* X28 */
-	*(--stk) = ( rt_ubase_t ) 0;			/* XZR - has no effect, used so there are an even number of registers. */
-	*(--stk) = ( rt_ubase_t ) texit;		/* X30 - procedure call link register. */
+    *(--stk) = ( rt_ubase_t ) 11;           /* X1 */
+    *(--stk) = ( rt_ubase_t ) parameter;    /* X0 */
+    *(--stk) = ( rt_ubase_t ) 33;           /* X3 */
+    *(--stk) = ( rt_ubase_t ) 22;           /* X2 */
+    *(--stk) = ( rt_ubase_t ) 55;           /* X5 */
+    *(--stk) = ( rt_ubase_t ) 44;           /* X4 */
+    *(--stk) = ( rt_ubase_t ) 77;           /* X7 */
+    *(--stk) = ( rt_ubase_t ) 66;           /* X6 */
+    *(--stk) = ( rt_ubase_t ) 99;           /* X9 */
+    *(--stk) = ( rt_ubase_t ) 88;           /* X8 */
+    *(--stk) = ( rt_ubase_t ) 11;           /* X11 */
+    *(--stk) = ( rt_ubase_t ) 10;           /* X10 */
+    *(--stk) = ( rt_ubase_t ) 13;           /* X13 */
+    *(--stk) = ( rt_ubase_t ) 12;           /* X12 */
+    *(--stk) = ( rt_ubase_t ) 15;           /* X15 */
+    *(--stk) = ( rt_ubase_t ) 14;           /* X14 */
+    *(--stk) = ( rt_ubase_t ) 17;           /* X17 */
+    *(--stk) = ( rt_ubase_t ) 16;           /* X16 */
+    *(--stk) = ( rt_ubase_t ) 19;           /* X19 */
+    *(--stk) = ( rt_ubase_t ) 18;           /* X18 */
+    *(--stk) = ( rt_ubase_t ) 21;           /* X21 */
+    *(--stk) = ( rt_ubase_t ) 20;           /* X20 */
+    *(--stk) = ( rt_ubase_t ) 23;           /* X23 */
+    *(--stk) = ( rt_ubase_t ) 22;           /* X22 */
+    *(--stk) = ( rt_ubase_t ) 25;           /* X25 */
+    *(--stk) = ( rt_ubase_t ) 24;           /* X24 */
+    *(--stk) = ( rt_ubase_t ) 27;           /* X27 */
+    *(--stk) = ( rt_ubase_t ) 26;           /* X26 */
+    *(--stk) = ( rt_ubase_t ) 29;           /* X29 */
+    *(--stk) = ( rt_ubase_t ) 28;           /* X28 */
+    *(--stk) = ( rt_ubase_t ) 0;            /* XZR - has no effect, used so there are an even number of registers. */
+    *(--stk) = ( rt_ubase_t ) texit;        /* X30 - procedure call link register. */
 
-	current_el = rt_hw_get_current_el();
+    current_el = rt_hw_get_current_el();
 
-	if(current_el == 3)
-	{
-		*(--stk) = INITIAL_SPSR_EL3;
-	}
-	else if(current_el == 2)
-	{
-		*(--stk) = INITIAL_SPSR_EL2;
-	}
-	else
-	{
-		*(--stk) = INITIAL_SPSR_EL1;
-	}
+    if(current_el == 3)
+    {
+        *(--stk) = INITIAL_SPSR_EL3;
+    }
+    else if(current_el == 2)
+    {
+        *(--stk) = INITIAL_SPSR_EL2;
+    }
+    else
+    {
+        *(--stk) = INITIAL_SPSR_EL1;
+    }
 
-	*(--stk) = ( rt_ubase_t ) tentry; 		/* Exception return address. */
+    *(--stk) = ( rt_ubase_t ) tentry;       /* Exception return address. */
 
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
 }
diff --git a/libcpu/aarch64/cortex-a72/trap.c b/libcpu/aarch64/cortex-a72/trap.c
index d93aa18fd6..bd76f7717b 100644
--- a/libcpu/aarch64/cortex-a72/trap.c
+++ b/libcpu/aarch64/cortex-a72/trap.c
@@ -1,8 +1,8 @@
 /*
- * Copyright (c) 2006-2020, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
- * 
+ *
  * Date           Author       Notes
  * 2018-10-06     ZhaoXiaowei    the first version
  */
@@ -28,14 +28,14 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs)
     rt_kprintf("Execption:\n");
     rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3);
     rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7);
-	rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
-	rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
-	rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
-	rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
+    rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11);
+    rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15);
+    rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19);
+    rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23);
     rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27);
-	rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
-	rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
-	rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
+    rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30);
+    rt_kprintf("spsr:0x%16.16lx\n", regs->spsr);
+    rt_kprintf("return pc:0x%16.16lx\n", regs->pc);
 }
 
 /**
@@ -64,7 +64,7 @@ void rt_hw_interrupt_ack(int fiq_irq);
 void rt_hw_trap_irq(void)
 {
     void *param;
-    int ir; 
+    int ir;
     rt_isr_handler_t isr_func;
     extern struct rt_irq_desc isr_table[];