Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5

[lts 3.1.x] format codes

7 files changed, 565 insertions, 565 deletions

diff --git a/libcpu/arm/AT91SAM7S/AT91SAM7S.h b/libcpu/arm/AT91SAM7S/AT91SAM7S.h
index 130f9074d1..91b57053da 100644
--- a/libcpu/arm/AT91SAM7S/AT91SAM7S.h
+++ b/libcpu/arm/AT91SAM7S/AT91SAM7S.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -15,276 +15,276 @@
 extern "C" {
 #endif
 
-#define AT91_REG *(volatile unsigned int *)		/* Hardware register definition */
+#define AT91_REG *(volatile unsigned int *)     /* Hardware register definition */
 
 /* ========== Register definition for TC0 peripheral ==========  */
-#define AT91C_TC0_SR		(AT91_REG(0xFFFA0020)) /* TC0 Status Register */
-#define AT91C_TC0_RC		(AT91_REG(0xFFFA001C)) /* TC0 Register C */
-#define AT91C_TC0_RB		(AT91_REG(0xFFFA0018)) /* TC0 Register B */
-#define AT91C_TC0_CCR		(AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */
-#define AT91C_TC0_CMR		(AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC0_IER		(AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */
-#define AT91C_TC0_RA		(AT91_REG(0xFFFA0014)) /* TC0 Register A */
-#define AT91C_TC0_IDR		(AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */
-#define AT91C_TC0_CV		(AT91_REG(0xFFFA0010)) /* TC0 Counter Value */
-#define AT91C_TC0_IMR		(AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */
+#define AT91C_TC0_SR        (AT91_REG(0xFFFA0020)) /* TC0 Status Register */
+#define AT91C_TC0_RC        (AT91_REG(0xFFFA001C)) /* TC0 Register C */
+#define AT91C_TC0_RB        (AT91_REG(0xFFFA0018)) /* TC0 Register B */
+#define AT91C_TC0_CCR       (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */
+#define AT91C_TC0_CMR       (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC0_IER       (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */
+#define AT91C_TC0_RA        (AT91_REG(0xFFFA0014)) /* TC0 Register A */
+#define AT91C_TC0_IDR       (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */
+#define AT91C_TC0_CV        (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */
+#define AT91C_TC0_IMR       (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */
 
 /* ========== Register definition for TC1 peripheral ========== */
-#define AT91C_TC1_RB		(AT91_REG(0xFFFA0058)) /* TC1 Register B */
-#define AT91C_TC1_CCR		(AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */
-#define AT91C_TC1_IER		(AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */
-#define AT91C_TC1_IDR		(AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */
-#define AT91C_TC1_SR		(AT91_REG(0xFFFA0060)) /* TC1 Status Register */
-#define AT91C_TC1_CMR		(AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC1_RA		(AT91_REG(0xFFFA0054)) /* TC1 Register A */
-#define AT91C_TC1_RC		(AT91_REG(0xFFFA005C)) /* TC1 Register C */
-#define AT91C_TC1_IMR		(AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */
-#define AT91C_TC1_CV		(AT91_REG(0xFFFA0050)) /* TC1 Counter Value */
+#define AT91C_TC1_RB        (AT91_REG(0xFFFA0058)) /* TC1 Register B */
+#define AT91C_TC1_CCR       (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */
+#define AT91C_TC1_IER       (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */
+#define AT91C_TC1_IDR       (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */
+#define AT91C_TC1_SR        (AT91_REG(0xFFFA0060)) /* TC1 Status Register */
+#define AT91C_TC1_CMR       (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC1_RA        (AT91_REG(0xFFFA0054)) /* TC1 Register A */
+#define AT91C_TC1_RC        (AT91_REG(0xFFFA005C)) /* TC1 Register C */
+#define AT91C_TC1_IMR       (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */
+#define AT91C_TC1_CV        (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */
 
 /* ========== Register definition for TC2 peripheral ========== */
-#define AT91C_TC2_CMR		(AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */
-#define AT91C_TC2_CCR		(AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */
-#define AT91C_TC2_CV		(AT91_REG(0xFFFA0090)) /* TC2 Counter Value */
-#define AT91C_TC2_RA		(AT91_REG(0xFFFA0094)) /* TC2 Register A */
-#define AT91C_TC2_RB		(AT91_REG(0xFFFA0098)) /* TC2 Register B */
-#define AT91C_TC2_IDR		(AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */
-#define AT91C_TC2_IMR		(AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */
-#define AT91C_TC2_RC		(AT91_REG(0xFFFA009C)) /* TC2 Register C */
-#define AT91C_TC2_IER		(AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */
-#define AT91C_TC2_SR		(AT91_REG(0xFFFA00A0)) /* TC2 Status Register */
+#define AT91C_TC2_CMR       (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */
+#define AT91C_TC2_CCR       (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */
+#define AT91C_TC2_CV        (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */
+#define AT91C_TC2_RA        (AT91_REG(0xFFFA0094)) /* TC2 Register A */
+#define AT91C_TC2_RB        (AT91_REG(0xFFFA0098)) /* TC2 Register B */
+#define AT91C_TC2_IDR       (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */
+#define AT91C_TC2_IMR       (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */
+#define AT91C_TC2_RC        (AT91_REG(0xFFFA009C)) /* TC2 Register C */
+#define AT91C_TC2_IER       (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */
+#define AT91C_TC2_SR        (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */
 
 /* ========== Register definition for PITC peripheral ========== */
-#define AT91C_PITC_PIVR		(AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */
-#define AT91C_PITC_PISR		(AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */
-#define AT91C_PITC_PIIR		(AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */
-#define AT91C_PITC_PIMR		(AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */
+#define AT91C_PITC_PIVR     (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */
+#define AT91C_PITC_PISR     (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */
+#define AT91C_PITC_PIIR     (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */
+#define AT91C_PITC_PIMR     (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */
 
 /* ========== Register definition for UDP peripheral ==========  */
-#define AT91C_UDP_NUM		(AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */
-#define AT91C_UDP_STAT		(AT91_REG(0xFFFB0004)) /* UDP Global State Register */
-#define AT91C_UDP_FADDR		(AT91_REG(0xFFFB0008)) /* UDP Function Address Register */
-#define AT91C_UDP_IER		(AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */
-#define AT91C_UDP_IDR		(AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */
-#define AT91C_UDP_IMR		(AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */
-#define AT91C_UDP_ISR		(AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */
-#define AT91C_UDP_ICR		(AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */
-#define AT91C_UDP_RSTEP		(AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */
-#define AT91C_UDP_CSR0		(AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */
-#define AT91C_UDP_CSR(n)	(*(&AT91C_UDP_CSR0 + n))
-#define AT91C_UDP_FDR0		(AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */
-#define AT91C_UDP_FDR(n)	(*(&AT91C_UDP_FDR0 + n))
-#define AT91C_UDP_TXVC		(AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */
+#define AT91C_UDP_NUM       (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */
+#define AT91C_UDP_STAT      (AT91_REG(0xFFFB0004)) /* UDP Global State Register */
+#define AT91C_UDP_FADDR     (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */
+#define AT91C_UDP_IER       (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */
+#define AT91C_UDP_IDR       (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */
+#define AT91C_UDP_IMR       (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */
+#define AT91C_UDP_ISR       (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */
+#define AT91C_UDP_ICR       (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */
+#define AT91C_UDP_RSTEP     (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */
+#define AT91C_UDP_CSR0      (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */
+#define AT91C_UDP_CSR(n)    (*(&AT91C_UDP_CSR0 + n))
+#define AT91C_UDP_FDR0      (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */
+#define AT91C_UDP_FDR(n)    (*(&AT91C_UDP_FDR0 + n))
+#define AT91C_UDP_TXVC      (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */
 
 /* ========== Register definition for US0 peripheral ========== */
-#define AT91C_US0_CR		(AT91_REG(0xFFFC0000)) /* US0 Control Register */
-#define AT91C_US0_MR		(AT91_REG(0xFFFC0004)) /* US0 Mode Register */
-#define AT91C_US0_IER		(AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */
-#define AT91C_US0_IDR		(AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */
-#define AT91C_US0_IMR		(AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */
-#define AT91C_US0_CSR		(AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */
-#define AT91C_US0_RHR		(AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */
-#define AT91C_US0_THR		(AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */
-#define AT91C_US0_BRGR		(AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */
-#define AT91C_US0_RTOR		(AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */
-#define AT91C_US0_TTGR		(AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */
-#define AT91C_US0_NER		(AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */
-#define AT91C_US0_FIDI		(AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */
-#define AT91C_US0_IF		(AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */
+#define AT91C_US0_CR        (AT91_REG(0xFFFC0000)) /* US0 Control Register */
+#define AT91C_US0_MR        (AT91_REG(0xFFFC0004)) /* US0 Mode Register */
+#define AT91C_US0_IER       (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */
+#define AT91C_US0_IDR       (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */
+#define AT91C_US0_IMR       (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */
+#define AT91C_US0_CSR       (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */
+#define AT91C_US0_RHR       (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */
+#define AT91C_US0_THR       (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */
+#define AT91C_US0_BRGR      (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */
+#define AT91C_US0_RTOR      (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */
+#define AT91C_US0_TTGR      (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */
+#define AT91C_US0_NER       (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */
+#define AT91C_US0_FIDI      (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */
+#define AT91C_US0_IF        (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */
 
 /* ========== Register definition for AIC peripheral ==========  */
-#define AT91C_AIC_SMR0		(AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */
-#define AT91C_AIC_SMR(n)	(*(&AT91C_AIC_SMR0 + n))
-#define AT91C_AIC_SVR0		(AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */
-#define AT91C_AIC_SVR(n)	(*(&AT91C_AIC_SVR0 + n))
-#define AT91C_AIC_IVR		(AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */
-#define AT91C_AIC_FVR		(AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */
-#define AT91C_AIC_ISR		(AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */
-#define AT91C_AIC_IPR		(AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */
-#define AT91C_AIC_IMR		(AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */
-#define AT91C_AIC_CISR		(AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */
-#define AT91C_AIC_IECR		(AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */
-#define AT91C_AIC_IDCR		(AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */
-#define AT91C_AIC_ICCR		(AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */
-#define AT91C_AIC_ISCR		(AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */
-#define AT91C_AIC_EOICR		(AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */
-#define AT91C_AIC_SPU		(AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */
-#define AT91C_AIC_DCR		(AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */
-#define AT91C_AIC_FFER		(AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */
-#define AT91C_AIC_FFDR		(AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */
-#define AT91C_AIC_FFSR		(AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */
+#define AT91C_AIC_SMR0      (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */
+#define AT91C_AIC_SMR(n)    (*(&AT91C_AIC_SMR0 + n))
+#define AT91C_AIC_SVR0      (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */
+#define AT91C_AIC_SVR(n)    (*(&AT91C_AIC_SVR0 + n))
+#define AT91C_AIC_IVR       (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */
+#define AT91C_AIC_FVR       (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */
+#define AT91C_AIC_ISR       (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */
+#define AT91C_AIC_IPR       (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */
+#define AT91C_AIC_IMR       (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */
+#define AT91C_AIC_CISR      (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */
+#define AT91C_AIC_IECR      (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */
+#define AT91C_AIC_IDCR      (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */
+#define AT91C_AIC_ICCR      (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */
+#define AT91C_AIC_ISCR      (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */
+#define AT91C_AIC_EOICR     (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */
+#define AT91C_AIC_SPU       (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */
+#define AT91C_AIC_DCR       (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */
+#define AT91C_AIC_FFER      (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */
+#define AT91C_AIC_FFDR      (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */
+#define AT91C_AIC_FFSR      (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */
 
 
 /* ========== Register definition for DBGU peripheral ==========  */
-#define AT91C_DBGU_EXID		(AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */
-#define AT91C_DBGU_BRGR		(AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */
-#define AT91C_DBGU_IDR		(AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */
-#define AT91C_DBGU_CSR		(AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */
-#define AT91C_DBGU_CIDR		(AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */
-#define AT91C_DBGU_MR		(AT91_REG(0xFFFFF204)) /* DBGU Mode Register */
-#define AT91C_DBGU_IMR		(AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */
-#define AT91C_DBGU_CR		(AT91_REG(0xFFFFF200)) /* DBGU Control Register */
-#define AT91C_DBGU_FNTR		(AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */
-#define AT91C_DBGU_THR		(AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */
-#define AT91C_DBGU_RHR		(AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */
-#define AT91C_DBGU_IER		(AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */
+#define AT91C_DBGU_EXID     (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */
+#define AT91C_DBGU_BRGR     (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */
+#define AT91C_DBGU_IDR      (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */
+#define AT91C_DBGU_CSR      (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */
+#define AT91C_DBGU_CIDR     (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */
+#define AT91C_DBGU_MR       (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */
+#define AT91C_DBGU_IMR      (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */
+#define AT91C_DBGU_CR       (AT91_REG(0xFFFFF200)) /* DBGU Control Register */
+#define AT91C_DBGU_FNTR     (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */
+#define AT91C_DBGU_THR      (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */
+#define AT91C_DBGU_RHR      (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */
+#define AT91C_DBGU_IER      (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */
 
 /* ========== Register definition for PIO peripheral ========== */
-#define AT91C_PIO_ODR		(AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */
-#define AT91C_PIO_SODR		(AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */
-#define AT91C_PIO_ISR		(AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */
-#define AT91C_PIO_ABSR		(AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */
-#define AT91C_PIO_IER		(AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */
-#define AT91C_PIO_PPUDR		(AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */
-#define AT91C_PIO_IMR		(AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */
-#define AT91C_PIO_PER		(AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */
-#define AT91C_PIO_IFDR		(AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */
-#define AT91C_PIO_OWDR		(AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */
-#define AT91C_PIO_MDSR		(AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */
-#define AT91C_PIO_IDR		(AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */
-#define AT91C_PIO_ODSR		(AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */
-#define AT91C_PIO_PPUSR		(AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */
-#define AT91C_PIO_OWSR		(AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */
-#define AT91C_PIO_BSR		(AT91_REG(0xFFFFF474)) /* PIOA Select B Register */
-#define AT91C_PIO_OWER		(AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */
-#define AT91C_PIO_IFER		(AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */
-#define AT91C_PIO_PDSR		(AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */
-#define AT91C_PIO_PPUER		(AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */
-#define AT91C_PIO_OSR		(AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */
-#define AT91C_PIO_ASR		(AT91_REG(0xFFFFF470)) /* PIOA Select A Register */
-#define AT91C_PIO_MDDR		(AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */
-#define AT91C_PIO_CODR		(AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */
-#define AT91C_PIO_MDER		(AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */
-#define AT91C_PIO_PDR		(AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */
-#define AT91C_PIO_IFSR		(AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */
-#define AT91C_PIO_OER		(AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */
-#define AT91C_PIO_PSR		(AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */
+#define AT91C_PIO_ODR       (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */
+#define AT91C_PIO_SODR      (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */
+#define AT91C_PIO_ISR       (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */
+#define AT91C_PIO_ABSR      (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */
+#define AT91C_PIO_IER       (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */
+#define AT91C_PIO_PPUDR     (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */
+#define AT91C_PIO_IMR       (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */
+#define AT91C_PIO_PER       (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */
+#define AT91C_PIO_IFDR      (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */
+#define AT91C_PIO_OWDR      (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */
+#define AT91C_PIO_MDSR      (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */
+#define AT91C_PIO_IDR       (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */
+#define AT91C_PIO_ODSR      (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */
+#define AT91C_PIO_PPUSR     (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */
+#define AT91C_PIO_OWSR      (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */
+#define AT91C_PIO_BSR       (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */
+#define AT91C_PIO_OWER      (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */
+#define AT91C_PIO_IFER      (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */
+#define AT91C_PIO_PDSR      (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */
+#define AT91C_PIO_PPUER     (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */
+#define AT91C_PIO_OSR       (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */
+#define AT91C_PIO_ASR       (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */
+#define AT91C_PIO_MDDR      (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */
+#define AT91C_PIO_CODR      (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */
+#define AT91C_PIO_MDER      (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */
+#define AT91C_PIO_PDR       (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */
+#define AT91C_PIO_IFSR      (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */
+#define AT91C_PIO_OER       (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */
+#define AT91C_PIO_PSR       (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */
 
 // ========== Register definition for PIOA peripheral ==========
-#define AT91C_PIOA_IMR  	(AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_IER  	(AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_OWDR 	(AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_ISR  	(AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_PPUDR 	(AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_MDSR 	(AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_MDER 	(AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PER  	(AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_PSR  	(AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register
-#define AT91C_PIOA_OER  	(AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register
-#define AT91C_PIOA_BSR  	(AT91_REG(0xFFFFF474)) // (PIOA) Select B Register
-#define AT91C_PIOA_PPUER 	(AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_MDDR 	(AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_PDR  	(AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_ODR  	(AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_IFDR 	(AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_ABSR 	(AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_ASR  	(AT91_REG(0xFFFFF470)) // (PIOA) Select A Register
-#define AT91C_PIOA_PPUSR 	(AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_ODSR 	(AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_SODR 	(AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_IFSR 	(AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_IFER 	(AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_OSR  	(AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register
-#define AT91C_PIOA_IDR  	(AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_PDSR 	(AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_CODR 	(AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_OWSR 	(AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_OWER 	(AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IMR      (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_IER      (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_OWDR     (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_ISR      (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_PPUDR    (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_MDSR     (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_MDER     (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PER      (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_PSR      (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register
+#define AT91C_PIOA_OER      (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register
+#define AT91C_PIOA_BSR      (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register
+#define AT91C_PIOA_PPUER    (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_MDDR     (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_PDR      (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_ODR      (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_IFDR     (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_ABSR     (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_ASR      (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register
+#define AT91C_PIOA_PPUSR    (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_ODSR     (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_SODR     (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_IFSR     (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_IFER     (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_OSR      (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register
+#define AT91C_PIOA_IDR      (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_PDSR     (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_CODR     (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_OWSR     (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_OWER     (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register
 // ========== Register definition for PIOB peripheral ==========
-#define AT91C_PIOB_OWSR 	(AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PPUSR 	(AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_PPUDR 	(AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_MDSR 	(AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_MDER 	(AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_IMR  	(AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_OSR  	(AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register
-#define AT91C_PIOB_OER  	(AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PSR  	(AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register
-#define AT91C_PIOB_PER  	(AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register
-#define AT91C_PIOB_BSR  	(AT91_REG(0xFFFFF674)) // (PIOB) Select B Register
-#define AT91C_PIOB_PPUER 	(AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_IFDR 	(AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_ODR  	(AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_ABSR 	(AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_ASR  	(AT91_REG(0xFFFFF670)) // (PIOB) Select A Register
-#define AT91C_PIOB_IFER 	(AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_IFSR 	(AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_SODR 	(AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ODSR 	(AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_CODR 	(AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_PDSR 	(AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_OWER 	(AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_IER  	(AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_OWDR 	(AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDDR 	(AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_ISR  	(AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_IDR  	(AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_PDR  	(AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_OWSR     (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PPUSR    (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_PPUDR    (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_MDSR     (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_MDER     (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_IMR      (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_OSR      (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register
+#define AT91C_PIOB_OER      (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PSR      (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register
+#define AT91C_PIOB_PER      (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register
+#define AT91C_PIOB_BSR      (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register
+#define AT91C_PIOB_PPUER    (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_IFDR     (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_ODR      (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_ABSR     (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_ASR      (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register
+#define AT91C_PIOB_IFER     (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_IFSR     (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_SODR     (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ODSR     (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_CODR     (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_PDSR     (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_OWER     (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_IER      (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_OWDR     (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDDR     (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_ISR      (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_IDR      (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_PDR      (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register
 
 /* ========== Register definition for PMC peripheral ========== */
-#define AT91C_PMC_SCER		(AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */
-#define AT91C_PMC_SCDR		(AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */
-#define AT91C_PMC_SCSR		(AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */
-#define AT91C_PMC_PCER		(AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */
-#define AT91C_PMC_PCDR		(AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */
-#define AT91C_PMC_PCSR		(AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */
-#define AT91C_PMC_MOR		(AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */
-#define AT91C_PMC_MCFR		(AT91_REG(0xFFFFFC24)) /* PMC Main Clock  Frequency Register */
-#define AT91C_PMC_PLLR		(AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */
-#define AT91C_PMC_MCKR		(AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */
-#define AT91C_PMC_PCKR		(AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */
-#define AT91C_PMC_IER		(AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */
-#define AT91C_PMC_IDR		(AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */
-#define AT91C_PMC_SR		(AT91_REG(0xFFFFFC68)) /* PMC Status Register */
-#define AT91C_PMC_IMR		(AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */
+#define AT91C_PMC_SCER      (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */
+#define AT91C_PMC_SCDR      (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */
+#define AT91C_PMC_SCSR      (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */
+#define AT91C_PMC_PCER      (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */
+#define AT91C_PMC_PCDR      (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */
+#define AT91C_PMC_PCSR      (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */
+#define AT91C_PMC_MOR       (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */
+#define AT91C_PMC_MCFR      (AT91_REG(0xFFFFFC24)) /* PMC Main Clock  Frequency Register */
+#define AT91C_PMC_PLLR      (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */
+#define AT91C_PMC_MCKR      (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */
+#define AT91C_PMC_PCKR      (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */
+#define AT91C_PMC_IER       (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */
+#define AT91C_PMC_IDR       (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */
+#define AT91C_PMC_SR        (AT91_REG(0xFFFFFC68)) /* PMC Status Register */
+#define AT91C_PMC_IMR       (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */
 
 /******************************************************************************/
 /*               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64                    */
 /******************************************************************************/
-#define AT91C_ID_FIQ    	0 	/* Advanced Interrupt Controller (FIQ) */
-#define AT91C_ID_SYS    	1 	/* System Peripheral */
-#define AT91C_ID_PIOA   	2 	/* Parallel IO Controller A */
-#define AT91C_ID_PIOB   	3 	/* Parallel IO Controller B */
-#define AT91C_ID_ADC    	4 	/* Analog-to-Digital Converter */
-#define AT91C_ID_SPI    	5	/* Serial Peripheral Interface */
-#define AT91C_ID_US0    	6	/* USART 0 */
-#define AT91C_ID_US1    	7	/* USART 1 */
-#define AT91C_ID_SSC    	8	/* Serial Synchronous Controller */
-#define AT91C_ID_TWI    	9 	/* Two-Wire Interface */
-#define AT91C_ID_PWMC   	10	/* PWM Controller */
-#define AT91C_ID_UDP    	11 	/* USB Device Port */
-#define AT91C_ID_TC0    	12 	/* Timer Counter 0 */
-#define AT91C_ID_TC1    	13 	/* Timer Counter 1 */
-#define AT91C_ID_TC2    	14 	/* Timer Counter 2 */
-#define AT91C_ID_15			15	/* Reserved */
-#define AT91C_ID_16 		16 	/* Reserved */
-#define AT91C_ID_17 		17 	/* Reserved */
-#define AT91C_ID_18 		18 	/* Reserved */
-#define AT91C_ID_19 		19 	/* Reserved */
-#define AT91C_ID_20 		20 	/* Reserved */
-#define AT91C_ID_21 		21 	/* Reserved */
-#define AT91C_ID_22 		22 	/* Reserved */
-#define AT91C_ID_23 		23 	/* Reserved */
-#define AT91C_ID_24 		24 	/* Reserved */
-#define AT91C_ID_25 		25 	/* Reserved */
-#define AT91C_ID_26 		26 	/* Reserved */
-#define AT91C_ID_27 		27 	/* Reserved */
-#define AT91C_ID_28 		28 	/* Reserved */
-#define AT91C_ID_29 		29 	/* Reserved */
-#define AT91C_ID_IRQ0		30 	/* Advanced Interrupt Controller (IRQ0) */
-#define AT91C_ID_IRQ1		31 	/* Advanced Interrupt Controller (IRQ1) */
-#define AT91C_ALL_INT		0xC0007FF7	/* ALL VALID INTERRUPTS */
+#define AT91C_ID_FIQ        0   /* Advanced Interrupt Controller (FIQ) */
+#define AT91C_ID_SYS        1   /* System Peripheral */
+#define AT91C_ID_PIOA       2   /* Parallel IO Controller A */
+#define AT91C_ID_PIOB       3   /* Parallel IO Controller B */
+#define AT91C_ID_ADC        4   /* Analog-to-Digital Converter */
+#define AT91C_ID_SPI        5   /* Serial Peripheral Interface */
+#define AT91C_ID_US0        6   /* USART 0 */
+#define AT91C_ID_US1        7   /* USART 1 */
+#define AT91C_ID_SSC        8   /* Serial Synchronous Controller */
+#define AT91C_ID_TWI        9   /* Two-Wire Interface */
+#define AT91C_ID_PWMC       10  /* PWM Controller */
+#define AT91C_ID_UDP        11  /* USB Device Port */
+#define AT91C_ID_TC0        12  /* Timer Counter 0 */
+#define AT91C_ID_TC1        13  /* Timer Counter 1 */
+#define AT91C_ID_TC2        14  /* Timer Counter 2 */
+#define AT91C_ID_15         15  /* Reserved */
+#define AT91C_ID_16         16  /* Reserved */
+#define AT91C_ID_17         17  /* Reserved */
+#define AT91C_ID_18         18  /* Reserved */
+#define AT91C_ID_19         19  /* Reserved */
+#define AT91C_ID_20         20  /* Reserved */
+#define AT91C_ID_21         21  /* Reserved */
+#define AT91C_ID_22         22  /* Reserved */
+#define AT91C_ID_23         23  /* Reserved */
+#define AT91C_ID_24         24  /* Reserved */
+#define AT91C_ID_25         25  /* Reserved */
+#define AT91C_ID_26         26  /* Reserved */
+#define AT91C_ID_27         27  /* Reserved */
+#define AT91C_ID_28         28  /* Reserved */
+#define AT91C_ID_29         29  /* Reserved */
+#define AT91C_ID_IRQ0       30  /* Advanced Interrupt Controller (IRQ0) */
+#define AT91C_ID_IRQ1       31  /* Advanced Interrupt Controller (IRQ1) */
+#define AT91C_ALL_INT       0xC0007FF7  /* ALL VALID INTERRUPTS */
 
 /*****************************/
 /* CPU Mode                  */
 /*****************************/
-#define USERMODE			0x10
-#define FIQMODE				0x11
-#define IRQMODE				0x12
-#define SVCMODE				0x13
-#define ABORTMODE			0x17
-#define UNDEFMODE			0x1b
-#define MODEMASK			0x1f
-#define NOINT				0xc0
+#define USERMODE            0x10
+#define FIQMODE             0x11
+#define IRQMODE             0x12
+#define SVCMODE             0x13
+#define ABORTMODE           0x17
+#define UNDEFMODE           0x1b
+#define MODEMASK            0x1f
+#define NOINT               0xc0
 
 #ifdef __cplusplus
 }
diff --git a/libcpu/arm/AT91SAM7S/cpu.c b/libcpu/arm/AT91SAM7S/cpu.c
index 8d28063eb1..8a6943dca1 100644
--- a/libcpu/arm/AT91SAM7S/cpu.c
+++ b/libcpu/arm/AT91SAM7S/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -30,9 +30,9 @@ void rt_hw_cpu_reset()
  */
 void rt_hw_cpu_shutdown()
 {
-	rt_kprintf("shutdown...\n");
+    rt_kprintf("shutdown...\n");
 
-	while (1);
+    while (1);
 }
 
 /*@}*/
diff --git a/libcpu/arm/AT91SAM7S/interrupt.c b/libcpu/arm/AT91SAM7S/interrupt.c
index db9d31fe28..e4aa8643f1 100644
--- a/libcpu/arm/AT91SAM7S/interrupt.c
+++ b/libcpu/arm/AT91SAM7S/interrupt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,7 +11,7 @@
 #include <rtthread.h>
 #include "AT91SAM7S.h"
 
-#define MAX_HANDLERS	32
+#define MAX_HANDLERS    32
 
 extern rt_uint32_t rt_interrupt_nest;
 
@@ -25,7 +25,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag;
 
 void rt_hw_interrupt_handler(int vector)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }
 
 /**
@@ -33,18 +33,18 @@ void rt_hw_interrupt_handler(int vector)
  */
 void rt_hw_interrupt_init()
 {
-	rt_base_t index;
+    rt_base_t index;
 
-	for (index = 0; index < MAX_HANDLERS; index ++)
-	{
-		AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler;
-	}
+    for (index = 0; index < MAX_HANDLERS; index ++)
+    {
+        AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler;
+    }
 
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
 }
 
 /**
@@ -53,11 +53,11 @@ void rt_hw_interrupt_init()
  */
 void rt_hw_interrupt_mask(int vector)
 {
-	/* disable interrupt */
-	AT91C_AIC_IDCR = 1 << vector;
+    /* disable interrupt */
+    AT91C_AIC_IDCR = 1 << vector;
 
-	/* clear interrupt */
-	AT91C_AIC_ICCR = 1 << vector;
+    /* clear interrupt */
+    AT91C_AIC_ICCR = 1 << vector;
 }
 
 /**
@@ -66,7 +66,7 @@ void rt_hw_interrupt_mask(int vector)
  */
 void rt_hw_interrupt_umask(int vector)
 {
-	AT91C_AIC_IECR = 1 << vector;
+    AT91C_AIC_IECR = 1 << vector;
 }
 
 /**
@@ -77,11 +77,11 @@ void rt_hw_interrupt_umask(int vector)
  */
 void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
 {
-	if(vector >= 0 && vector < MAX_HANDLERS)
-	{
-		if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)AT91C_AIC_SVR(vector);
-		if (new_handler != RT_NULL) AT91C_AIC_SVR(vector) = (rt_uint32_t)new_handler;
-	}
+    if(vector >= 0 && vector < MAX_HANDLERS)
+    {
+        if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)AT91C_AIC_SVR(vector);
+        if (new_handler != RT_NULL) AT91C_AIC_SVR(vector) = (rt_uint32_t)new_handler;
+    }
 }
 
 /*@}*/
diff --git a/libcpu/arm/AT91SAM7S/serial.c b/libcpu/arm/AT91SAM7S/serial.c
index adbe8609d6..583443f4cb 100644
--- a/libcpu/arm/AT91SAM7S/serial.c
+++ b/libcpu/arm/AT91SAM7S/serial.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,46 +22,46 @@
 typedef volatile rt_uint32_t REG32;
 struct rt_at91serial_hw
 {
-	REG32	 US_CR; 	// Control Register
-	REG32	 US_MR; 	// Mode Register
-	REG32	 US_IER; 	// Interrupt Enable Register
-	REG32	 US_IDR; 	// Interrupt Disable Register
-	REG32	 US_IMR; 	// Interrupt Mask Register
-	REG32	 US_CSR; 	// Channel Status Register
-	REG32	 US_RHR; 	// Receiver Holding Register
-	REG32	 US_THR; 	// Transmitter Holding Register
-	REG32	 US_BRGR; 	// Baud Rate Generator Register
-	REG32	 US_RTOR; 	// Receiver Time-out Register
-	REG32	 US_TTGR; 	// Transmitter Time-guard Register
-	REG32	 Reserved0[5]; 	//
-	REG32	 US_FIDI; 	// FI_DI_Ratio Register
-	REG32	 US_NER; 	// Nb Errors Register
-	REG32	 Reserved1[1]; 	//
-	REG32	 US_IF; 	// IRDA_FILTER Register
-	REG32	 Reserved2[44]; 	//
-	REG32	 US_RPR; 	// Receive Pointer Register
-	REG32	 US_RCR; 	// Receive Counter Register
-	REG32	 US_TPR; 	// Transmit Pointer Register
-	REG32	 US_TCR; 	// Transmit Counter Register
-	REG32	 US_RNPR; 	// Receive Next Pointer Register
-	REG32	 US_RNCR; 	// Receive Next Counter Register
-	REG32	 US_TNPR; 	// Transmit Next Pointer Register
-	REG32	 US_TNCR; 	// Transmit Next Counter Register
-	REG32	 US_PTCR; 	// PDC Transfer Control Register
-	REG32	 US_PTSR; 	// PDC Transfer Status Register
+    REG32    US_CR;     // Control Register
+    REG32    US_MR;     // Mode Register
+    REG32    US_IER;    // Interrupt Enable Register
+    REG32    US_IDR;    // Interrupt Disable Register
+    REG32    US_IMR;    // Interrupt Mask Register
+    REG32    US_CSR;    // Channel Status Register
+    REG32    US_RHR;    // Receiver Holding Register
+    REG32    US_THR;    // Transmitter Holding Register
+    REG32    US_BRGR;   // Baud Rate Generator Register
+    REG32    US_RTOR;   // Receiver Time-out Register
+    REG32    US_TTGR;   // Transmitter Time-guard Register
+    REG32    Reserved0[5];  //
+    REG32    US_FIDI;   // FI_DI_Ratio Register
+    REG32    US_NER;    // Nb Errors Register
+    REG32    Reserved1[1];  //
+    REG32    US_IF;     // IRDA_FILTER Register
+    REG32    Reserved2[44];     //
+    REG32    US_RPR;    // Receive Pointer Register
+    REG32    US_RCR;    // Receive Counter Register
+    REG32    US_TPR;    // Transmit Pointer Register
+    REG32    US_TCR;    // Transmit Counter Register
+    REG32    US_RNPR;   // Receive Next Pointer Register
+    REG32    US_RNCR;   // Receive Next Counter Register
+    REG32    US_TNPR;   // Transmit Next Pointer Register
+    REG32    US_TNCR;   // Transmit Next Counter Register
+    REG32    US_PTCR;   // PDC Transfer Control Register
+    REG32    US_PTSR;   // PDC Transfer Status Register
 };
 
 struct rt_at91serial
 {
-	struct rt_device parent;
+    struct rt_device parent;
 
-	struct rt_at91serial_hw* hw_base;
-	rt_uint16_t peripheral_id;
-	rt_uint32_t baudrate;
+    struct rt_at91serial_hw* hw_base;
+    rt_uint16_t peripheral_id;
+    rt_uint32_t baudrate;
 
-	/* reception field */
-	rt_uint16_t save_index, read_index;
-	rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
+    /* reception field */
+    rt_uint16_t save_index, read_index;
+    rt_uint8_t  rx_buffer[RT_UART_RX_BUFFER_SIZE];
 };
 #ifdef RT_USING_UART1
 struct rt_at91serial serial1;
@@ -72,312 +72,312 @@ struct rt_at91serial serial2;
 
 static void rt_hw_serial_isr(int irqno)
 {
-	rt_base_t level;
-	struct rt_device* device;
-	struct rt_at91serial* serial = RT_NULL;
+    rt_base_t level;
+    struct rt_device* device;
+    struct rt_at91serial* serial = RT_NULL;
 
-	if (irqno == AT91C_ID_US0)
-	{
+    if (irqno == AT91C_ID_US0)
+    {
 #ifdef RT_USING_UART1
-		/* serial 1 */
-		serial = &serial1;
+        /* serial 1 */
+        serial = &serial1;
 #endif
-	}
-	else if (irqno == AT91C_ID_US1)
-	{
+    }
+    else if (irqno == AT91C_ID_US1)
+    {
 #ifdef RT_USING_UART2
-		/* serial 2 */
-		serial = &serial2;
+        /* serial 2 */
+        serial = &serial2;
 #endif
-	}
-	RT_ASSERT(serial != RT_NULL);
+    }
+    RT_ASSERT(serial != RT_NULL);
 
-	/* get generic device object */
-	device = (rt_device_t)serial;
+    /* get generic device object */
+    device = (rt_device_t)serial;
 
-	/* disable interrupt */
-	level = rt_hw_interrupt_disable();
+    /* disable interrupt */
+    level = rt_hw_interrupt_disable();
 
-	/* get received character */
-	serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR;
+    /* get received character */
+    serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR;
 
-	/* move to next position */
-	serial->save_index ++;
-	if (serial->save_index >= RT_UART_RX_BUFFER_SIZE)
-		serial->save_index = 0;
+    /* move to next position */
+    serial->save_index ++;
+    if (serial->save_index >= RT_UART_RX_BUFFER_SIZE)
+        serial->save_index = 0;
 
-	/* if the next position is read index, discard this 'read char' */
-	if (serial->save_index == serial->read_index)
-	{
-		serial->read_index ++;
-		if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
-			serial->read_index = 0;
-	}
+    /* if the next position is read index, discard this 'read char' */
+    if (serial->save_index == serial->read_index)
+    {
+        serial->read_index ++;
+        if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
+            serial->read_index = 0;
+    }
 
-	/* enable interrupt */
-	rt_hw_interrupt_enable(level);
+    /* enable interrupt */
+    rt_hw_interrupt_enable(level);
 
-	/* indicate to upper layer application */
-	if (device->rx_indicate != RT_NULL)
-		device->rx_indicate(device, 1);
+    /* indicate to upper layer application */
+    if (device->rx_indicate != RT_NULL)
+        device->rx_indicate(device, 1);
 
-	/* ack interrupt */
-	AT91C_AIC_EOICR = 1;
+    /* ack interrupt */
+    AT91C_AIC_EOICR = 1;
 }
 
 static rt_err_t rt_serial_init (rt_device_t dev)
 {
-	rt_uint32_t bd;
-	struct rt_at91serial* serial = (struct rt_at91serial*) dev;
+    rt_uint32_t bd;
+    struct rt_at91serial* serial = (struct rt_at91serial*) dev;
 
-	RT_ASSERT(serial != RT_NULL);
-	/* must be US0 or US1 */
-	RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) ||
-		(serial->peripheral_id == AT91C_ID_US1)));
+    RT_ASSERT(serial != RT_NULL);
+    /* must be US0 or US1 */
+    RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) ||
+        (serial->peripheral_id == AT91C_ID_US1)));
 
-	/* Enable Clock for USART */
-	AT91C_PMC_PCER = 1 << serial->peripheral_id;
+    /* Enable Clock for USART */
+    AT91C_PMC_PCER = 1 << serial->peripheral_id;
 
-	/* Enable RxD0 and TxDO Pin */
-	if (serial->peripheral_id == AT91C_ID_US0)
-	{
-		/* set pinmux */
-		AT91C_PIO_PDR = (1 << 5) | (1 << 6);
-	}
-	else if (serial->peripheral_id == AT91C_ID_US1)
-	{
-		/* set pinmux */
-		AT91C_PIO_PDR = (1 << 21) | (1 << 22);
-	}
+    /* Enable RxD0 and TxDO Pin */
+    if (serial->peripheral_id == AT91C_ID_US0)
+    {
+        /* set pinmux */
+        AT91C_PIO_PDR = (1 << 5) | (1 << 6);
+    }
+    else if (serial->peripheral_id == AT91C_ID_US1)
+    {
+        /* set pinmux */
+        AT91C_PIO_PDR = (1 << 21) | (1 << 22);
+    }
 
-	serial->hw_base->US_CR = AT91C_US_RSTRX	| 	/* Reset Receiver      */
-					AT91C_US_RSTTX		|		/* Reset Transmitter   */
-					AT91C_US_RXDIS		|		/* Receiver Disable    */
-					AT91C_US_TXDIS;				/* Transmitter Disable */
+    serial->hw_base->US_CR = AT91C_US_RSTRX |   /* Reset Receiver      */
+                    AT91C_US_RSTTX      |       /* Reset Transmitter   */
+                    AT91C_US_RXDIS      |       /* Receiver Disable    */
+                    AT91C_US_TXDIS;             /* Transmitter Disable */
 
-	serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL |	/* Normal Mode */
-					AT91C_US_CLKS_CLOCK		|		/* Clock = MCK */
-					AT91C_US_CHRL_8_BITS	|		/* 8-bit Data  */
-					AT91C_US_PAR_NONE		|		/* No Parity   */
-					AT91C_US_NBSTOP_1_BIT;			/* 1 Stop Bit  */
+    serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL |   /* Normal Mode */
+                    AT91C_US_CLKS_CLOCK     |       /* Clock = MCK */
+                    AT91C_US_CHRL_8_BITS    |       /* 8-bit Data  */
+                    AT91C_US_PAR_NONE       |       /* No Parity   */
+                    AT91C_US_NBSTOP_1_BIT;          /* 1 Stop Bit  */
 
-	/* set baud rate divisor */
-	bd =  ((MCK*10)/(serial->baudrate * 16));
-	if ((bd % 10) >= 5) bd = (bd / 10) + 1;
-	else bd /= 10;
+    /* set baud rate divisor */
+    bd =  ((MCK*10)/(serial->baudrate * 16));
+    if ((bd % 10) >= 5) bd = (bd / 10) + 1;
+    else bd /= 10;
 
-	serial->hw_base->US_BRGR = bd;
-	serial->hw_base->US_CR = AT91C_US_RXEN |		/* Receiver Enable     */
-					AT91C_US_TXEN;					/* Transmitter Enable  */
+    serial->hw_base->US_BRGR = bd;
+    serial->hw_base->US_CR = AT91C_US_RXEN |        /* Receiver Enable     */
+                    AT91C_US_TXEN;                  /* Transmitter Enable  */
 
-	/* reset rx index */
-	serial->save_index = 0;
-	serial->read_index = 0;
+    /* reset rx index */
+    serial->save_index = 0;
+    serial->read_index = 0;
 
-	/* reset rx buffer */
-	rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE);
+    /* reset rx buffer */
+    rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE);
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
 {
-	struct rt_at91serial *serial = (struct rt_at91serial*)dev;
-	RT_ASSERT(serial != RT_NULL);
+    struct rt_at91serial *serial = (struct rt_at91serial*)dev;
+    RT_ASSERT(serial != RT_NULL);
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* enable UART rx interrupt */
-		serial->hw_base->US_IER = 1 << 0; 		/* RxReady interrupt */
-		serial->hw_base->US_IMR |= 1 << 0; 		/* umask RxReady interrupt */
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* enable UART rx interrupt */
+        serial->hw_base->US_IER = 1 << 0;       /* RxReady interrupt */
+        serial->hw_base->US_IMR |= 1 << 0;      /* umask RxReady interrupt */
 
-		/* install UART handler */
-		rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL);
-		AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5);
-		rt_hw_interrupt_umask(serial->peripheral_id);
-	}
+        /* install UART handler */
+        rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL);
+        AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5);
+        rt_hw_interrupt_umask(serial->peripheral_id);
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_err_t rt_serial_close(rt_device_t dev)
 {
-	struct rt_at91serial *serial = (struct rt_at91serial*)dev;
-	RT_ASSERT(serial != RT_NULL);
+    struct rt_at91serial *serial = (struct rt_at91serial*)dev;
+    RT_ASSERT(serial != RT_NULL);
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		/* disable interrupt */
-		serial->hw_base->US_IDR = 1 << 0; 		/* RxReady interrupt */
-		serial->hw_base->US_IMR &= ~(1 << 0); 	/* mask RxReady interrupt */
-	}
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        /* disable interrupt */
+        serial->hw_base->US_IDR = 1 << 0;       /* RxReady interrupt */
+        serial->hw_base->US_IMR &= ~(1 << 0);   /* mask RxReady interrupt */
+    }
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	struct rt_at91serial *serial = (struct rt_at91serial*)dev;
-	RT_ASSERT(serial != RT_NULL);
+    rt_uint8_t* ptr;
+    struct rt_at91serial *serial = (struct rt_at91serial*)dev;
+    RT_ASSERT(serial != RT_NULL);
 
-	/* point to buffer */
-	ptr = (rt_uint8_t*) buffer;
+    /* point to buffer */
+    ptr = (rt_uint8_t*) buffer;
 
-	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
-	{
-		while (size)
-		{
-			/* interrupt receive */
-			rt_base_t level;
+    if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        while (size)
+        {
+            /* interrupt receive */
+            rt_base_t level;
 
-			/* disable interrupt */
-			level = rt_hw_interrupt_disable();
-			if (serial->read_index != serial->save_index)
-			{
-				*ptr = serial->rx_buffer[serial->read_index];
+            /* disable interrupt */
+            level = rt_hw_interrupt_disable();
+            if (serial->read_index != serial->save_index)
+            {
+                *ptr = serial->rx_buffer[serial->read_index];
 
-				serial->read_index ++;
-				if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
-					serial->read_index = 0;
-			}
-			else
-			{
-				/* no data in rx buffer */
+                serial->read_index ++;
+                if (serial->read_index >= RT_UART_RX_BUFFER_SIZE)
+                    serial->read_index = 0;
+            }
+            else
+            {
+                /* no data in rx buffer */
 
-				/* enable interrupt */
-				rt_hw_interrupt_enable(level);
-				break;
-			}
+                /* enable interrupt */
+                rt_hw_interrupt_enable(level);
+                break;
+            }
 
-			/* enable interrupt */
-			rt_hw_interrupt_enable(level);
+            /* enable interrupt */
+            rt_hw_interrupt_enable(level);
 
-			ptr ++; size --;
-		}
+            ptr ++; size --;
+        }
 
-		return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
-	}
-	else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
-	{
-		/* not support right now */
-		RT_ASSERT(0);
-	}
-	else
-	{
-		/* poll mode */
-		while (size)
-		{
-			/* Wait for Full Rx Buffer */
-			while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY));
+        return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+    }
+    else if (dev->flag & RT_DEVICE_FLAG_DMA_RX)
+    {
+        /* not support right now */
+        RT_ASSERT(0);
+    }
+    else
+    {
+        /* poll mode */
+        while (size)
+        {
+            /* Wait for Full Rx Buffer */
+            while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY));
 
-			/* Read Character */
-			*ptr = serial->hw_base->US_RHR;
-			ptr ++;
-			size --;
-		}
+            /* Read Character */
+            *ptr = serial->hw_base->US_RHR;
+            ptr ++;
+            size --;
+        }
 
-		return (rt_size_t)ptr - (rt_size_t)buffer;
-	}
+        return (rt_size_t)ptr - (rt_size_t)buffer;
+    }
 
-	return 0;
+    return 0;
 }
 
 static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
 {
-	rt_uint8_t* ptr;
-	struct rt_at91serial *serial = (struct rt_at91serial*)dev;
-	RT_ASSERT(serial != RT_NULL);
+    rt_uint8_t* ptr;
+    struct rt_at91serial *serial = (struct rt_at91serial*)dev;
+    RT_ASSERT(serial != RT_NULL);
 
-	ptr = (rt_uint8_t*) buffer;
-	if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY)
-	{
-		if (dev->flag & RT_DEVICE_FLAG_STREAM)
-		{
-			/* it's a stream mode device */
-			while (size)
-			{
-				/* stream mode */
-				if (*ptr == '\n')
-				{
-					while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY));
-					serial->hw_base->US_THR = '\r';
-				}
+    ptr = (rt_uint8_t*) buffer;
+    if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY)
+    {
+        if (dev->flag & RT_DEVICE_FLAG_STREAM)
+        {
+            /* it's a stream mode device */
+            while (size)
+            {
+                /* stream mode */
+                if (*ptr == '\n')
+                {
+                    while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY));
+                    serial->hw_base->US_THR = '\r';
+                }
 
-				/* Wait for Empty Tx Buffer */
-				while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY));
+                /* Wait for Empty Tx Buffer */
+                while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY));
 
-				/* Transmit Character */
-				serial->hw_base->US_THR = *ptr;
-				ptr ++; size --;
-			}
-		}
-		else
-		{
-			while (size)
-			{
-				/* Wait for Empty Tx Buffer */
-				while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY));
+                /* Transmit Character */
+                serial->hw_base->US_THR = *ptr;
+                ptr ++; size --;
+            }
+        }
+        else
+        {
+            while (size)
+            {
+                /* Wait for Empty Tx Buffer */
+                while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY));
 
-				/* Transmit Character */
-				serial->hw_base->US_THR = *ptr;
-				ptr ++; size --;
-			}
-		}
-	}
+                /* Transmit Character */
+                serial->hw_base->US_THR = *ptr;
+                ptr ++; size --;
+            }
+        }
+    }
 
-	return (rt_size_t)ptr - (rt_size_t)buffer;
+    return (rt_size_t)ptr - (rt_size_t)buffer;
 }
 
 static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args)
 {
-	return RT_EOK;
+    return RT_EOK;
 }
 
 rt_err_t rt_hw_serial_init()
 {
-	rt_device_t device;
+    rt_device_t device;
 
 #ifdef RT_USING_UART1
-	device = (rt_device_t) &serial1;
+    device = (rt_device_t) &serial1;
 
-	/* init serial device private data */
-	serial1.hw_base 		= (struct rt_at91serial_hw*)AT91C_BASE_US0;
-	serial1.peripheral_id 	= AT91C_ID_US0;
-	serial1.baudrate		= 115200;
+    /* init serial device private data */
+    serial1.hw_base         = (struct rt_at91serial_hw*)AT91C_BASE_US0;
+    serial1.peripheral_id   = AT91C_ID_US0;
+    serial1.baudrate        = 115200;
 
-	/* set device virtual interface */
-	device->init 	= rt_serial_init;
-	device->open 	= rt_serial_open;
-	device->close 	= rt_serial_close;
-	device->read 	= rt_serial_read;
-	device->write 	= rt_serial_write;
-	device->control = rt_serial_control;
+    /* set device virtual interface */
+    device->init    = rt_serial_init;
+    device->open    = rt_serial_open;
+    device->close   = rt_serial_close;
+    device->read    = rt_serial_read;
+    device->write   = rt_serial_write;
+    device->control = rt_serial_control;
 
-	/* register uart1 on device subsystem */
-	rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
+    /* register uart1 on device subsystem */
+    rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
 #endif
 
 #ifdef RT_USING_UART2
-	device = (rt_device_t) &serial2;
+    device = (rt_device_t) &serial2;
 
-	serial2.hw_base 		= (struct rt_at91serial_hw*)AT91C_BASE_US1;
-	serial2.peripheral_id 	= AT91C_ID_US1;
-	serial2.baudrate		= 115200;
+    serial2.hw_base         = (struct rt_at91serial_hw*)AT91C_BASE_US1;
+    serial2.peripheral_id   = AT91C_ID_US1;
+    serial2.baudrate        = 115200;
 
-	/* set device virtual interface */
-	device->init 	= rt_serial_init;
-	device->open 	= rt_serial_open;
-	device->close 	= rt_serial_close;
-	device->read 	= rt_serial_read;
-	device->write 	= rt_serial_write;
-	device->control = rt_serial_control;
+    /* set device virtual interface */
+    device->init    = rt_serial_init;
+    device->open    = rt_serial_open;
+    device->close   = rt_serial_close;
+    device->read    = rt_serial_read;
+    device->write   = rt_serial_write;
+    device->control = rt_serial_control;
 
-	/* register uart2 on device subsystem */
-	rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
+    /* register uart2 on device subsystem */
+    rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX);
 #endif
 
-	return RT_EOK;
+    return RT_EOK;
 }
 
 /*@}*/
diff --git a/libcpu/arm/AT91SAM7S/serial.h b/libcpu/arm/AT91SAM7S/serial.h
index 0937e92f6c..7766053a7f 100644
--- a/libcpu/arm/AT91SAM7S/serial.h
+++ b/libcpu/arm/AT91SAM7S/serial.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,48 +17,48 @@
 #define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
 #endif
 
-#define AT91C_US_RXRDY			((unsigned int) 0x1 <<  0)	/* US RXRDY Interrupt */
-#define AT91C_US_TXRDY			((unsigned int) 0x1 <<  1)	/* US TXRDY Interrupt */
-#define AT91C_US_RSTRX			((unsigned int) 0x1 <<  2)	/* US Reset Receiver */
-#define AT91C_US_RSTTX			((unsigned int) 0x1 <<  3)	/* US Reset Transmitter */
-#define AT91C_US_RXEN			((unsigned int) 0x1 <<  4)	/* US Receiver Enable */
-#define AT91C_US_RXDIS			((unsigned int) 0x1 <<  5)	/* US Receiver Disable */
-#define AT91C_US_TXEN			((unsigned int) 0x1 <<  6)	/* US Transmitter Enable */
-#define AT91C_US_TXDIS			((unsigned int) 0x1 <<  7)	/* US Transmitter Disable */
-#define AT91C_US_RSTSTA			((unsigned int) 0x1 <<  8)	/* US Reset Status Bits */
+#define AT91C_US_RXRDY          ((unsigned int) 0x1 <<  0)  /* US RXRDY Interrupt */
+#define AT91C_US_TXRDY          ((unsigned int) 0x1 <<  1)  /* US TXRDY Interrupt */
+#define AT91C_US_RSTRX          ((unsigned int) 0x1 <<  2)  /* US Reset Receiver */
+#define AT91C_US_RSTTX          ((unsigned int) 0x1 <<  3)  /* US Reset Transmitter */
+#define AT91C_US_RXEN           ((unsigned int) 0x1 <<  4)  /* US Receiver Enable */
+#define AT91C_US_RXDIS          ((unsigned int) 0x1 <<  5)  /* US Receiver Disable */
+#define AT91C_US_TXEN           ((unsigned int) 0x1 <<  6)  /* US Transmitter Enable */
+#define AT91C_US_TXDIS          ((unsigned int) 0x1 <<  7)  /* US Transmitter Disable */
+#define AT91C_US_RSTSTA         ((unsigned int) 0x1 <<  8)  /* US Reset Status Bits */
 
-#define AT91C_US_USMODE_NORMAL	((unsigned int) 0x0)		/* USAR) Normal */
-#define AT91C_US_USMODE_RS485	((unsigned int) 0x1)		/* USAR) RS485 */
-#define AT91C_US_USMODE_HWHSH	((unsigned int) 0x2)		/* USAR) Hardware Handshaking */
-#define AT91C_US_USMODE_MODEM	((unsigned int) 0x3)		/* USAR) Modem */
-#define AT91C_US_USMODE_ISO7816_0	((unsigned int) 0x4)	/* USAR) ISO7816 protocol: T = 0 */
-#define AT91C_US_USMODE_ISO7816_1	((unsigned int) 0x6)	/* USAR) ISO7816 protocol: T = 1 */
-#define AT91C_US_USMODE_IRDA	((unsigned int) 0x8)		/* USAR) IrDA */
-#define AT91C_US_USMODE_SWHSH	((unsigned int) 0xC)		/* USAR) Software Handshaking */
+#define AT91C_US_USMODE_NORMAL  ((unsigned int) 0x0)        /* USAR) Normal */
+#define AT91C_US_USMODE_RS485   ((unsigned int) 0x1)        /* USAR) RS485 */
+#define AT91C_US_USMODE_HWHSH   ((unsigned int) 0x2)        /* USAR) Hardware Handshaking */
+#define AT91C_US_USMODE_MODEM   ((unsigned int) 0x3)        /* USAR) Modem */
+#define AT91C_US_USMODE_ISO7816_0   ((unsigned int) 0x4)    /* USAR) ISO7816 protocol: T = 0 */
+#define AT91C_US_USMODE_ISO7816_1   ((unsigned int) 0x6)    /* USAR) ISO7816 protocol: T = 1 */
+#define AT91C_US_USMODE_IRDA    ((unsigned int) 0x8)        /* USAR) IrDA */
+#define AT91C_US_USMODE_SWHSH   ((unsigned int) 0xC)        /* USAR) Software Handshaking */
 
-#define AT91C_US_CLKS_CLOCK		((unsigned int) 0x0 <<  4)	/* USAR) Clock */
-#define AT91C_US_CLKS_FDIV1		((unsigned int) 0x1 <<  4)	/* USAR) fdiv1 */
-#define AT91C_US_CLKS_SLOW		((unsigned int) 0x2 <<  4)	/* USAR) slow_clock (ARM) */
-#define AT91C_US_CLKS_EXT		((unsigned int) 0x3 <<  4)	/* USAR) External (SCK) */
+#define AT91C_US_CLKS_CLOCK     ((unsigned int) 0x0 <<  4)  /* USAR) Clock */
+#define AT91C_US_CLKS_FDIV1     ((unsigned int) 0x1 <<  4)  /* USAR) fdiv1 */
+#define AT91C_US_CLKS_SLOW      ((unsigned int) 0x2 <<  4)  /* USAR) slow_clock (ARM) */
+#define AT91C_US_CLKS_EXT       ((unsigned int) 0x3 <<  4)  /* USAR) External (SCK) */
 
-#define AT91C_US_CHRL_5_BITS	((unsigned int) 0x0 <<  6)	/* USAR) Character Length: 5 bits */
-#define AT91C_US_CHRL_6_BITS	((unsigned int) 0x1 <<  6)	/* USAR) Character Length: 6 bits */
-#define AT91C_US_CHRL_7_BITS	((unsigned int) 0x2 <<  6)	/* USAR) Character Length: 7 bits */
-#define AT91C_US_CHRL_8_BITS	((unsigned int) 0x3 <<  6)	/* USAR) Character Length: 8 bits */
+#define AT91C_US_CHRL_5_BITS    ((unsigned int) 0x0 <<  6)  /* USAR) Character Length: 5 bits */
+#define AT91C_US_CHRL_6_BITS    ((unsigned int) 0x1 <<  6)  /* USAR) Character Length: 6 bits */
+#define AT91C_US_CHRL_7_BITS    ((unsigned int) 0x2 <<  6)  /* USAR) Character Length: 7 bits */
+#define AT91C_US_CHRL_8_BITS    ((unsigned int) 0x3 <<  6)  /* USAR) Character Length: 8 bits */
 
-#define AT91C_US_PAR_EVEN		((unsigned int) 0x0 <<  9)	/* DBGU Even Parity */
-#define AT91C_US_PAR_ODD		((unsigned int) 0x1 <<  9)	/* DBGU Odd Parity */
-#define AT91C_US_PAR_SPACE		((unsigned int) 0x2 <<  9)	/* DBGU Parity forced to 0 (Space) */
-#define AT91C_US_PAR_MARK		((unsigned int) 0x3 <<  9)	/* DBGU Parity forced to 1 (Mark) */
-#define AT91C_US_PAR_NONE		((unsigned int) 0x4 <<  9)	/* DBGU No Parity */
-#define AT91C_US_PAR_MULTI_DROP	((unsigned int) 0x6 <<  9)	/* DBGU Multi-drop mode */
+#define AT91C_US_PAR_EVEN       ((unsigned int) 0x0 <<  9)  /* DBGU Even Parity */
+#define AT91C_US_PAR_ODD        ((unsigned int) 0x1 <<  9)  /* DBGU Odd Parity */
+#define AT91C_US_PAR_SPACE      ((unsigned int) 0x2 <<  9)  /* DBGU Parity forced to 0 (Space) */
+#define AT91C_US_PAR_MARK       ((unsigned int) 0x3 <<  9)  /* DBGU Parity forced to 1 (Mark) */
+#define AT91C_US_PAR_NONE       ((unsigned int) 0x4 <<  9)  /* DBGU No Parity */
+#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 <<  9)  /* DBGU Multi-drop mode */
 
-#define AT91C_US_NBSTOP_1_BIT	((unsigned int) 0x0 << 12)	/* USART 1 stop bit */
-#define AT91C_US_NBSTOP_15_BIT	((unsigned int) 0x1 << 12)	/* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
-#define AT91C_US_NBSTOP_2_BIT	((unsigned int) 0x2 << 12)	/* USART 2 stop bits */
+#define AT91C_US_NBSTOP_1_BIT   ((unsigned int) 0x0 << 12)  /* USART 1 stop bit */
+#define AT91C_US_NBSTOP_15_BIT  ((unsigned int) 0x1 << 12)  /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */
+#define AT91C_US_NBSTOP_2_BIT   ((unsigned int) 0x2 << 12)  /* USART 2 stop bits */
 
-#define MCK		48054857
-#define BR    	115200			/* Baud Rate */
-#define BRD  	(MCK/16/BR)		/* Baud Rate Divisor */
+#define MCK     48054857
+#define BR      115200          /* Baud Rate */
+#define BRD     (MCK/16/BR)     /* Baud Rate Divisor */
 
 #endif
diff --git a/libcpu/arm/AT91SAM7S/stack.c b/libcpu/arm/AT91SAM7S/stack.c
index 6f8bd13bf9..23fce8e6e2 100644
--- a/libcpu/arm/AT91SAM7S/stack.c
+++ b/libcpu/arm/AT91SAM7S/stack.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/arm/AT91SAM7S/trap.c b/libcpu/arm/AT91SAM7S/trap.c
index 208e568950..aa9df7c74b 100644
--- a/libcpu/arm/AT91SAM7S/trap.c
+++ b/libcpu/arm/AT91SAM7S/trap.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -20,12 +20,12 @@
 
 void rt_hw_trap_irq()
 {
-	rt_isr_handler_t hander = (rt_isr_handler_t)AT91C_AIC_IVR;
+    rt_isr_handler_t hander = (rt_isr_handler_t)AT91C_AIC_IVR;
 
-	hander(AT91C_AIC_ISR);
+    hander(AT91C_AIC_ISR);
 
-	/* end of interrupt */
-	AT91C_AIC_EOICR = 0;
+    /* end of interrupt */
+    AT91C_AIC_EOICR = 0;
 }
 
 void rt_hw_trap_fiq()