Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5

[lts 3.1.x] format codes

8 files changed, 230 insertions, 230 deletions

diff --git a/libcpu/arm/am335x/am33xx.h b/libcpu/arm/am335x/am33xx.h
index 99a65ac915..3112a8ac15 100644
--- a/libcpu/arm/am335x/am33xx.h
+++ b/libcpu/arm/am335x/am33xx.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -9,8 +9,8 @@
 #ifndef __AM33XX_H__
 #define __AM33XX_H__
 
-#define REG32(x) 	(*((volatile unsigned int *)(x)))
-#define REG16(x) 	(*((volatile unsigned short *)(x)))
+#define REG32(x)    (*((volatile unsigned int *)(x)))
+#define REG16(x)    (*((volatile unsigned short *)(x)))
 
 /** Cache Line size in ARM Cortex-A8.                                         */
 #define AM33XX_CACHELINE_SIZE                   (64)
@@ -198,22 +198,22 @@
 #define CM_DPLL_CLKSEL_TIMER2_CLK(base)    REG32(CM_DPLL(base) + 0x8)
 
 /* timer registers */
-#define DMTIMER_TIDR(base)   		REG32(base + 0x0)
-#define DMTIMER_TIOCP_CFG(base)   	REG32(base + 0x10)
-#define DMTIMER_IRQ_EOI(base)   	REG32(base + 0x20)
-#define DMTIMER_IRQSTATUS_RAW(base)	REG32(base + 0x24)
-#define DMTIMER_IRQSTATUS(base)   	REG32(base + 0x28)
-#define DMTIMER_IRQENABLE_SET(base)	REG32(base + 0x2C)
-#define DMTIMER_IRQENABLE_CLR(base)	REG32(base + 0x30)
-#define DMTIMER_IRQWAKEEN(base)   	REG32(base + 0x34)
-#define DMTIMER_TCLR(base)   		REG32(base + 0x38)
-#define DMTIMER_TCRR(base)   		REG32(base + 0x3C)
-#define DMTIMER_TLDR(base)   		REG32(base + 0x40)
-#define DMTIMER_TTGR(base)   		REG32(base + 0x44)
-#define DMTIMER_TWPS(base)   		REG32(base + 0x48)
-#define DMTIMER_TMAR(base)   		REG32(base + 0x4C)
-#define DMTIMER_TCAR(base, n)		REG32(base + 0x50 + (((n) - 1) * 8))
-#define DMTIMER_TSICR(base)   		REG32(base + 0x54)
+#define DMTIMER_TIDR(base)          REG32(base + 0x0)
+#define DMTIMER_TIOCP_CFG(base)     REG32(base + 0x10)
+#define DMTIMER_IRQ_EOI(base)       REG32(base + 0x20)
+#define DMTIMER_IRQSTATUS_RAW(base) REG32(base + 0x24)
+#define DMTIMER_IRQSTATUS(base)     REG32(base + 0x28)
+#define DMTIMER_IRQENABLE_SET(base) REG32(base + 0x2C)
+#define DMTIMER_IRQENABLE_CLR(base) REG32(base + 0x30)
+#define DMTIMER_IRQWAKEEN(base)     REG32(base + 0x34)
+#define DMTIMER_TCLR(base)          REG32(base + 0x38)
+#define DMTIMER_TCRR(base)          REG32(base + 0x3C)
+#define DMTIMER_TLDR(base)          REG32(base + 0x40)
+#define DMTIMER_TTGR(base)          REG32(base + 0x44)
+#define DMTIMER_TWPS(base)          REG32(base + 0x48)
+#define DMTIMER_TMAR(base)          REG32(base + 0x4C)
+#define DMTIMER_TCAR(base, n)       REG32(base + 0x50 + (((n) - 1) * 8))
+#define DMTIMER_TSICR(base)         REG32(base + 0x54)
 
 #define EMU_INT               0
 #define COMMTX_INT            1
@@ -317,33 +317,33 @@
 
 struct rt_hw_register
 {
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long sp;
-	unsigned long lr;
-	unsigned long pc;
-	unsigned long cpsr;
-	unsigned long ORIG_r0;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
+    unsigned long ORIG_r0;
 };
 
-#define USERMODE	0x10
-#define FIQMODE		0x11
-#define IRQMODE		0x12
-#define SVCMODE		0x13
-#define ABORTMODE	0x17
-#define UNDEFMODE	0x1b
-#define MODEMASK	0x1f
-#define NOINT		0xc0
+#define USERMODE    0x10
+#define FIQMODE     0x11
+#define IRQMODE     0x12
+#define SVCMODE     0x13
+#define ABORTMODE   0x17
+#define UNDEFMODE   0x1b
+#define MODEMASK    0x1f
+#define NOINT       0xc0
 
 #endif
diff --git a/libcpu/arm/am335x/cpu.c b/libcpu/arm/am335x/cpu.c
index cae865fe50..284e2ea260 100644
--- a/libcpu/arm/am335x/cpu.c
+++ b/libcpu/arm/am335x/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,74 +17,74 @@
  */
 /*@{*/
 
-#define ICACHE_MASK	(rt_uint32_t)(1 << 12)
-#define DCACHE_MASK	(rt_uint32_t)(1 << 2)
+#define ICACHE_MASK (rt_uint32_t)(1 << 12)
+#define DCACHE_MASK (rt_uint32_t)(1 << 2)
 
 #if defined(__CC_ARM)
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	__asm
-	{
-		mrc p15, 0, i, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, i, c1, c0, 0
+    }
 
-	return i;
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
+    rt_uint32_t value;
 
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		orr value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
+    rt_uint32_t value;
 
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		bic value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 #elif defined(__GNUC__)
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	return i;
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"orr  r0,r0,%0\n\t"			\
-	   	"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "orr  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"bic  r0,r0,%0\n\t"			\
-		"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "bic  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 #endif
 
@@ -96,7 +96,7 @@ rt_inline void cache_disable(rt_uint32_t bit)
  */
 void rt_hw_cpu_icache_enable()
 {
-	cache_enable(ICACHE_MASK);
+    cache_enable(ICACHE_MASK);
 }
 
 /**
@@ -105,7 +105,7 @@ void rt_hw_cpu_icache_enable()
  */
 void rt_hw_cpu_icache_disable()
 {
-	cache_disable(ICACHE_MASK);
+    cache_disable(ICACHE_MASK);
 }
 
 /**
@@ -114,7 +114,7 @@ void rt_hw_cpu_icache_disable()
  */
 rt_base_t rt_hw_cpu_icache_status()
 {
-	return (cp15_rd() & ICACHE_MASK);
+    return (cp15_rd() & ICACHE_MASK);
 }
 
 /**
@@ -123,7 +123,7 @@ rt_base_t rt_hw_cpu_icache_status()
  */
 void rt_hw_cpu_dcache_enable()
 {
-	cache_enable(DCACHE_MASK);
+    cache_enable(DCACHE_MASK);
 }
 
 /**
@@ -132,7 +132,7 @@ void rt_hw_cpu_dcache_enable()
  */
 void rt_hw_cpu_dcache_disable()
 {
-	cache_disable(DCACHE_MASK);
+    cache_disable(DCACHE_MASK);
 }
 
 /**
@@ -141,7 +141,7 @@ void rt_hw_cpu_dcache_disable()
  */
 rt_base_t rt_hw_cpu_dcache_status()
 {
-	return (cp15_rd() & DCACHE_MASK);
+    return (cp15_rd() & DCACHE_MASK);
 }
 #endif
 
@@ -151,14 +151,14 @@ rt_base_t rt_hw_cpu_dcache_status()
  */
 void rt_hw_cpu_shutdown()
 {
-	rt_uint32_t level;
-	rt_kprintf("shutdown...\n");
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
 
-	level = rt_hw_interrupt_disable();
-	while (level)
-	{
-		RT_ASSERT(0);
-	}
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
 }
 
 /*@}*/
diff --git a/libcpu/arm/am335x/interrupt.c b/libcpu/arm/am335x/interrupt.c
index 3acd868496..c4c5e8d7eb 100644
--- a/libcpu/arm/am335x/interrupt.c
+++ b/libcpu/arm/am335x/interrupt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,7 +17,7 @@
 
 #define AINTC_BASE  AM33XX_AINTC_REGS
 
-#define MAX_HANDLERS	128
+#define MAX_HANDLERS    128
 
 extern volatile rt_uint8_t rt_interrupt_nest;
 
@@ -59,13 +59,13 @@ extern int system_vectors;
 static void rt_hw_vector_init(void)
 {
     unsigned int *dest = (unsigned int *)AM335X_VECTOR_BASE;
-    
+
 #ifdef __ICCARM__
     unsigned int *src =  (unsigned int *)&__vector;
 #else
     unsigned int *src =  (unsigned int *)&system_vectors;
 #endif
-    
+
     rt_memcpy(dest, src, 16 * 4);
     rt_cpu_vector_set_base(AM335X_VECTOR_BASE);
 }
diff --git a/libcpu/arm/am335x/interrupt.h b/libcpu/arm/am335x/interrupt.h
index 7461f94da0..90f392f407 100644
--- a/libcpu/arm/am335x/interrupt.h
+++ b/libcpu/arm/am335x/interrupt.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -14,28 +14,28 @@
 #define INT_IRQ     0x00
 #define INT_FIQ     0x01
 
-#define INTC_REVISION(hw_base) 		    REG32((hw_base) + 0x0)
-#define INTC_SYSCONFIG(hw_base) 		REG32((hw_base) + 0x10)
-#define INTC_SYSSTATUS(hw_base) 		REG32((hw_base) + 0x14)
-#define INTC_SIR_IRQ(hw_base) 		    REG32((hw_base) + 0x40)
-#define INTC_SIR_FIQ(hw_base) 		    REG32((hw_base) + 0x44)
-#define INTC_CONTROL(hw_base) 		    REG32((hw_base) + 0x48)
-#define INTC_PROTECTION(hw_base) 	    REG32((hw_base) + 0x4c)
-#define INTC_IDLE(hw_base)  			REG32((hw_base) + 0x50)
-#define INTC_IRQ_PRIORITY(hw_base) 	    REG32((hw_base) + 0x60)
-#define INTC_FIQ_PRIORITY(hw_base) 	    REG32((hw_base) + 0x64)
-#define INTC_THRESHOLD(hw_base) 		REG32((hw_base) + 0x68)
-#define INTC_SICR(hw_base)  			REG32((hw_base) + 0x6c)
-#define INTC_SCR(hw_base, n) 		    REG32((hw_base) + 0x70 + ((n) * 0x04))
-#define INTC_ITR(hw_base, n) 		    REG32((hw_base) + 0x80 + ((n) * 0x20))
-#define INTC_MIR(hw_base, n) 		    REG32((hw_base) + 0x84 + ((n) * 0x20))
-#define INTC_MIR_CLEAR(hw_base, n)  	REG32((hw_base) + 0x88 + ((n) * 0x20))
-#define INTC_MIR_SET(hw_base, n) 	    REG32((hw_base) + 0x8c + ((n) * 0x20))
-#define INTC_ISR_SET(hw_base, n) 	    REG32((hw_base) + 0x90 + ((n) * 0x20))
-#define INTC_ISR_CLEAR(hw_base, n) 	    REG32((hw_base) + 0x94 + ((n) * 0x20))
+#define INTC_REVISION(hw_base)          REG32((hw_base) + 0x0)
+#define INTC_SYSCONFIG(hw_base)         REG32((hw_base) + 0x10)
+#define INTC_SYSSTATUS(hw_base)         REG32((hw_base) + 0x14)
+#define INTC_SIR_IRQ(hw_base)           REG32((hw_base) + 0x40)
+#define INTC_SIR_FIQ(hw_base)           REG32((hw_base) + 0x44)
+#define INTC_CONTROL(hw_base)           REG32((hw_base) + 0x48)
+#define INTC_PROTECTION(hw_base)        REG32((hw_base) + 0x4c)
+#define INTC_IDLE(hw_base)              REG32((hw_base) + 0x50)
+#define INTC_IRQ_PRIORITY(hw_base)      REG32((hw_base) + 0x60)
+#define INTC_FIQ_PRIORITY(hw_base)      REG32((hw_base) + 0x64)
+#define INTC_THRESHOLD(hw_base)         REG32((hw_base) + 0x68)
+#define INTC_SICR(hw_base)              REG32((hw_base) + 0x6c)
+#define INTC_SCR(hw_base, n)            REG32((hw_base) + 0x70 + ((n) * 0x04))
+#define INTC_ITR(hw_base, n)            REG32((hw_base) + 0x80 + ((n) * 0x20))
+#define INTC_MIR(hw_base, n)            REG32((hw_base) + 0x84 + ((n) * 0x20))
+#define INTC_MIR_CLEAR(hw_base, n)      REG32((hw_base) + 0x88 + ((n) * 0x20))
+#define INTC_MIR_SET(hw_base, n)        REG32((hw_base) + 0x8c + ((n) * 0x20))
+#define INTC_ISR_SET(hw_base, n)        REG32((hw_base) + 0x90 + ((n) * 0x20))
+#define INTC_ISR_CLEAR(hw_base, n)      REG32((hw_base) + 0x94 + ((n) * 0x20))
 #define INTC_PENDING_IRQ(hw_base, n)    REG32((hw_base) + 0x98 + ((n) * 0x20))
 #define INTC_PENDING_FIQ(hw_base, n)    REG32((hw_base) + 0x9c + ((n) * 0x20))
-#define INTC_ILR(hw_base, n)  		    REG32((hw_base) + 0x100 + ((n) * 0x04))
+#define INTC_ILR(hw_base, n)            REG32((hw_base) + 0x100 + ((n) * 0x04))
 
 void rt_hw_interrupt_control(int vector, int priority, int route);
 int rt_hw_interrupt_get_active(int fiq_irq);
diff --git a/libcpu/arm/am335x/mmu.c b/libcpu/arm/am335x/mmu.c
index babe825298..fbd886d0e6 100644
--- a/libcpu/arm/am335x/mmu.c
+++ b/libcpu/arm/am335x/mmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,122 +22,122 @@ extern void rt_cpu_tlb_set(register rt_uint32_t i);
 
 void mmu_disable_dcache()
 {
-	rt_cpu_dcache_disable();
+    rt_cpu_dcache_disable();
 }
 
 void mmu_enable_dcache()
 {
-	rt_hw_cpu_dcache_enable();
+    rt_hw_cpu_dcache_enable();
 }
 
 void mmu_disable_icache()
 {
-	rt_cpu_icache_disable();
+    rt_cpu_icache_disable();
 }
 
 void mmu_enable_icache()
 {
-	rt_hw_cpu_icache_enable();
+    rt_hw_cpu_icache_enable();
 }
 
 void mmu_disable()
 {
-	rt_cpu_mmu_disable();
+    rt_cpu_mmu_disable();
 }
 
 void mmu_enable()
 {
-	rt_cpu_mmu_enable();
+    rt_cpu_mmu_enable();
 }
 
 void mmu_setttbase(register rt_uint32_t i)
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
    /* Invalidates all TLBs.Domain access is selected as
     * client by configuring domain access register,
     * in that case access controlled by permission value
     * set by page table entry
     */
-	value = 0;
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
+    value = 0;
+    asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
 
-	value = 0x55555555;
-	asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
-	
-	rt_cpu_tlb_set(i);
+    value = 0x55555555;
+    asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
+
+    rt_cpu_tlb_set(i);
 }
 
 void mmu_set_domain(register rt_uint32_t i)
 {
-	asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+    asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
 }
 
 void mmu_enable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 1);
+    i |= (1 << 1);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 1);
+    i &= ~(1 << 1);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+    asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
 }
 
 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~0x1f;
+    ptr = buffer & ~0x1f;
 
-	while (ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
-		ptr += 32;
-	}
+    while (ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+        ptr += 32;
+    }
 }
 
 void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~0x1f;
+    ptr = buffer & ~0x1f;
 
-	while (ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
-		ptr += 32;
-	}
+    while (ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+        ptr += 32;
+    }
 }
 
 void mmu_invalidate_tlb()
 {
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
 }
 
 void mmu_invalidate_icache()
 {
-	asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
 
 /* level1 page table */
@@ -150,8 +150,8 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrS
     nSec=(vaddrEnd>>20)-(vaddrStart>>20);
     for(i=0;i<=nSec;i++)
     {
-		*pTT = attr |(((paddrStart>>20)+i)<<20);
-		pTT++;
+        *pTT = attr |(((paddrStart>>20)+i)<<20);
+        pTT++;
     }
 }
 
@@ -161,21 +161,21 @@ RT_WEAK void mmu_setmtts(void)
     mmu_setmtt(0x00000000, 0xFFFFFFFF,     0x00000000, RW_NCNB);  /* None cached for 4G memory   */
     mmu_setmtt(0x80200000, 0x80800000 - 1, 0x80200000, RW_CB);    /* 126M cached DDR memory      */
     mmu_setmtt(0x80000000, 0x80200000 - 1, 0x80000000, RW_NCNB);  /* 2M none-cached DDR memory   */
-    mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB);    /* 63K OnChip memory 			 */
+    mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB);    /* 63K OnChip memory           */
 }
 
 void rt_hw_mmu_init(void)
 {
-	/* disable I/D cache */
-	mmu_disable_dcache();
-	mmu_disable_icache();
-	mmu_disable();
-	mmu_invalidate_tlb();
+    /* disable I/D cache */
+    mmu_disable_dcache();
+    mmu_disable_icache();
+    mmu_disable();
+    mmu_invalidate_tlb();
 
     mmu_setmtts();
 
-	/* set MMU table address */
-	mmu_setttbase((rt_uint32_t)_page_table);
+    /* set MMU table address */
+    mmu_setttbase((rt_uint32_t)_page_table);
 
     /* enables MMU */
     mmu_enable();
diff --git a/libcpu/arm/am335x/mmu.h b/libcpu/arm/am335x/mmu.h
index 73635d3a0e..706d669844 100644
--- a/libcpu/arm/am335x/mmu.h
+++ b/libcpu/arm/am335x/mmu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -13,27 +13,27 @@
 
 #include <rtthread.h>
 
-#define DESC_SEC		(0x2)
-#define CB				(3<<2)  //cache_on, write_back
-#define CNB				(2<<2)  //cache_on, write_through
-#define NCB				(1<<2)  //cache_off,WR_BUF on
-#define NCNB			(0<<2)  //cache_off,WR_BUF off
-#define AP_RW			(3<<10) //supervisor=RW, user=RW
-#define AP_RO			(2<<10) //supervisor=RW, user=RO
+#define DESC_SEC        (0x2)
+#define CB              (3<<2)  //cache_on, write_back
+#define CNB             (2<<2)  //cache_on, write_through
+#define NCB             (1<<2)  //cache_off,WR_BUF on
+#define NCNB            (0<<2)  //cache_off,WR_BUF off
+#define AP_RW           (3<<10) //supervisor=RW, user=RW
+#define AP_RO           (2<<10) //supervisor=RW, user=RO
 
-#define DOMAIN_FAULT	(0x0)
-#define DOMAIN_CHK		(0x1)
-#define DOMAIN_NOTCHK	(0x3)
-#define DOMAIN0			(0x0<<5)
-#define DOMAIN1			(0x1<<5)
+#define DOMAIN_FAULT    (0x0)
+#define DOMAIN_CHK      (0x1)
+#define DOMAIN_NOTCHK   (0x3)
+#define DOMAIN0         (0x0<<5)
+#define DOMAIN1         (0x1<<5)
 
-#define DOMAIN0_ATTR	(DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR	(DOMAIN_FAULT<<2)
+#define DOMAIN0_ATTR    (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR    (DOMAIN_FAULT<<2)
 
-#define RW_CB		    (AP_RW|DOMAIN0|CB|DESC_SEC)		/* Read/Write, cache, write back */
-#define RW_CNB		    (AP_RW|DOMAIN0|CNB|DESC_SEC)	/* Read/Write, cache, write through */
-#define RW_NCNB		    (AP_RW|DOMAIN0|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
-#define RW_FAULT	    (AP_RW|DOMAIN1|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
+#define RW_CB           (AP_RW|DOMAIN0|CB|DESC_SEC)     /* Read/Write, cache, write back */
+#define RW_CNB          (AP_RW|DOMAIN0|CNB|DESC_SEC)    /* Read/Write, cache, write through */
+#define RW_NCNB         (AP_RW|DOMAIN0|NCNB|DESC_SEC)   /* Read/Write without cache and write buffer */
+#define RW_FAULT        (AP_RW|DOMAIN1|NCNB|DESC_SEC)   /* Read/Write without cache and write buffer */
 
 void rt_hw_mmu_init(void);
 
diff --git a/libcpu/arm/am335x/stack.c b/libcpu/arm/am335x/stack.c
index 1dad930818..db3cb37e73 100644
--- a/libcpu/arm/am335x/stack.c
+++ b/libcpu/arm/am335x/stack.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/arm/am335x/trap.c b/libcpu/arm/am335x/trap.c
index b77543da64..7c73ce93d3 100644
--- a/libcpu/arm/am335x/trap.c
+++ b/libcpu/arm/am335x/trap.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -36,13 +36,13 @@ extern long list_thread(void);
 
 void rt_hw_show_register (struct rt_hw_register *regs)
 {
-	rt_kprintf("Execption:\n");
-	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-	rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-	rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
 }
 
 /**
@@ -62,15 +62,15 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
         return;
 #endif
 
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("undefined instruction\n");
-	rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name);
+    rt_kprintf("undefined instruction\n");
+    rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -84,10 +84,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs)
  */
 void rt_hw_trap_swi(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("software interrupt\n");
-	rt_hw_cpu_shutdown();
+    rt_kprintf("software interrupt\n");
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -100,15 +100,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
  */
 void rt_hw_trap_pabt(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("prefetch abort\n");
-	rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name);
+    rt_kprintf("prefetch abort\n");
+    rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -124,29 +124,29 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs)
 
 #ifdef RT_USING_GDB
     if (gdb_mem_fault_handler) {
-        regs->pc = (unsigned long)gdb_mem_fault_handler; 
+        regs->pc = (unsigned long)gdb_mem_fault_handler;
         return;
     }
 #endif
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("data abort\n");
-	rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name);
+    rt_kprintf("data abort\n");
+    rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name);
 
 #ifdef RT_USING_FINSH
-	list_thread();
+    list_thread();
 #endif
-	rt_hw_cpu_shutdown();
+    rt_hw_cpu_shutdown();
 }
 
 void rt_hw_trap_irq()
 {
     void *param;
-	unsigned long ir;
+    unsigned long ir;
     rt_isr_handler_t isr_func;
     extern struct rt_irq_desc isr_table[];
 
-	ir = rt_hw_interrupt_get_active(INT_IRQ);
+    ir = rt_hw_interrupt_get_active(INT_IRQ);
     if (ir == 127)
     {
         /* new IRQ generation */
@@ -169,18 +169,18 @@ void rt_hw_trap_irq()
     if (isr_func != RT_NULL)
         isr_func(ir, param);
 
-	/* new IRQ generation */
+    /* new IRQ generation */
     rt_hw_interrupt_ack(INT_IRQ);
 }
 
 void rt_hw_trap_fiq()
 {
     void *param;
-	unsigned long ir;
+    unsigned long ir;
     rt_isr_handler_t isr_func;
     extern struct rt_irq_desc isr_table[];
 
-	ir = rt_hw_interrupt_get_active(INT_FIQ);
+    ir = rt_hw_interrupt_get_active(INT_FIQ);
 
     /* get interrupt service routine */
     isr_func = isr_table[ir].handler;
@@ -189,7 +189,7 @@ void rt_hw_trap_fiq()
     /* turn to interrupt service routine */
     isr_func(ir, param);
 
-	/* new FIQ generation */
+    /* new FIQ generation */
     rt_hw_interrupt_ack(INT_FIQ);
 }