Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5

[lts 3.1.x] format codes

7 files changed, 446 insertions, 446 deletions

diff --git a/libcpu/arm/armv6/armv6.h b/libcpu/arm/armv6/armv6.h
index 659ce90721..522c35845f 100644
--- a/libcpu/arm/armv6/armv6.h
+++ b/libcpu/arm/armv6/armv6.h
@@ -1,12 +1,12 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  */
- 
+
 #ifndef __ARMV6_H__
 #define __ARMV6_H__
 
@@ -26,7 +26,7 @@
 #ifndef __ASSEMBLY__
 struct rt_hw_register
 {
-	rt_uint32_t cpsr;
+    rt_uint32_t cpsr;
     rt_uint32_t r0;
     rt_uint32_t r1;
     rt_uint32_t r2;
@@ -46,24 +46,24 @@ struct rt_hw_register
 };
 #if(0)
 struct rt_hw_register{
-	rt_uint32_t r0;
-	rt_uint32_t r1;
-	rt_uint32_t r2;
-	rt_uint32_t r3;
-	rt_uint32_t r4;
-	rt_uint32_t r5;
-	rt_uint32_t r6;
-	rt_uint32_t r7;
-	rt_uint32_t r8;
-	rt_uint32_t r9;
-	rt_uint32_t r10;
-	rt_uint32_t fp;
-	rt_uint32_t ip;
-	rt_uint32_t sp;
-	rt_uint32_t lr;
-	rt_uint32_t pc;
-	rt_uint32_t cpsr;
-	rt_uint32_t ORIG_r0;
+    rt_uint32_t r0;
+    rt_uint32_t r1;
+    rt_uint32_t r2;
+    rt_uint32_t r3;
+    rt_uint32_t r4;
+    rt_uint32_t r5;
+    rt_uint32_t r6;
+    rt_uint32_t r7;
+    rt_uint32_t r8;
+    rt_uint32_t r9;
+    rt_uint32_t r10;
+    rt_uint32_t fp;
+    rt_uint32_t ip;
+    rt_uint32_t sp;
+    rt_uint32_t lr;
+    rt_uint32_t pc;
+    rt_uint32_t cpsr;
+    rt_uint32_t ORIG_r0;
 };
 #endif
 #endif
diff --git a/libcpu/arm/armv6/cpuport.c b/libcpu/arm/armv6/cpuport.c
index c8e9201722..eda87225d5 100644
--- a/libcpu/arm/armv6/cpuport.c
+++ b/libcpu/arm/armv6/cpuport.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,8 +11,8 @@
 #include <rthw.h>
 #include <rtthread.h>
 
-#define ICACHE_MASK	(rt_uint32_t)(1 << 12)
-#define DCACHE_MASK	(rt_uint32_t)(1 << 2)
+#define ICACHE_MASK (rt_uint32_t)(1 << 12)
+#define DCACHE_MASK (rt_uint32_t)(1 << 2)
 
 extern void machine_reset(void);
 extern void machine_shutdown(void);
@@ -20,32 +20,32 @@ extern void machine_shutdown(void);
 #ifdef __GNUC__
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	return i;
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"orr  r0,r0,%0\n\t"			\
-	   	"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "orr  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"bic  r0,r0,%0\n\t"			\
-		"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "bic  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 
 
@@ -54,38 +54,38 @@ rt_inline void cache_disable(rt_uint32_t bit)
 #ifdef __CC_ARM
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	__asm
-	{
-		mrc p15, 0, i, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, i, c1, c0, 0
+    }
 
-	return i;
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
+    rt_uint32_t value;
 
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		orr value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
+    rt_uint32_t value;
 
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		bic value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 #endif
 
@@ -95,7 +95,7 @@ rt_inline void cache_disable(rt_uint32_t bit)
  */
 void rt_hw_cpu_icache_enable()
 {
-	cache_enable(ICACHE_MASK);
+    cache_enable(ICACHE_MASK);
 }
 
 /**
@@ -104,7 +104,7 @@ void rt_hw_cpu_icache_enable()
  */
 void rt_hw_cpu_icache_disable()
 {
-	cache_disable(ICACHE_MASK);
+    cache_disable(ICACHE_MASK);
 }
 
 /**
@@ -113,7 +113,7 @@ void rt_hw_cpu_icache_disable()
  */
 rt_base_t rt_hw_cpu_icache_status()
 {
-	return (cp15_rd() & ICACHE_MASK);
+    return (cp15_rd() & ICACHE_MASK);
 }
 
 /**
@@ -122,7 +122,7 @@ rt_base_t rt_hw_cpu_icache_status()
  */
 void rt_hw_cpu_dcache_enable()
 {
-	cache_enable(DCACHE_MASK);
+    cache_enable(DCACHE_MASK);
 }
 
 /**
@@ -131,7 +131,7 @@ void rt_hw_cpu_dcache_enable()
  */
 void rt_hw_cpu_dcache_disable()
 {
-	cache_disable(DCACHE_MASK);
+    cache_disable(DCACHE_MASK);
 }
 
 /**
@@ -140,7 +140,7 @@ void rt_hw_cpu_dcache_disable()
  */
 rt_base_t rt_hw_cpu_dcache_status()
 {
-	return (cp15_rd() & DCACHE_MASK);
+    return (cp15_rd() & DCACHE_MASK);
 }
 
 /**
@@ -149,13 +149,13 @@ rt_base_t rt_hw_cpu_dcache_status()
  */
 void rt_hw_cpu_reset()
 {
-	
-	rt_kprintf("Restarting system...\n");
-	machine_reset();
 
-	while(1);	/* loop forever and wait for reset to happen */
+    rt_kprintf("Restarting system...\n");
+    machine_reset();
 
-	/* NEVER REACHED */
+    while(1);   /* loop forever and wait for reset to happen */
+
+    /* NEVER REACHED */
 }
 
 /**
@@ -164,67 +164,67 @@ void rt_hw_cpu_reset()
  */
 void rt_hw_cpu_shutdown()
 {
-	rt_uint32_t level;
-	rt_kprintf("shutdown...\n");
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
 
-	level = rt_hw_interrupt_disable();
-	machine_shutdown();
-	while (level)
-	{
-		RT_ASSERT(0);
-	}
+    level = rt_hw_interrupt_disable();
+    machine_shutdown();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
 }
 
 #ifdef RT_USING_CPU_FFS
 /**
- * This function finds the first bit set (beginning with the least significant bit) 
+ * This function finds the first bit set (beginning with the least significant bit)
  * in value and return the index of that bit.
  *
- * Bits are numbered starting at 1 (the least significant bit).  A return value of 
+ * Bits are numbered starting at 1 (the least significant bit).  A return value of
  * zero from any of these functions means that the argument was zero.
- * 
- * @return return the index of the first bit set. If value is 0, then this function 
+ *
+ * @return return the index of the first bit set. If value is 0, then this function
  * shall return 0.
  */
 #if defined(__CC_ARM)
 int __rt_ffs(int value)
 {
-	register rt_uint32_t x;
+    register rt_uint32_t x;
+
+    if (value == 0)
+        return value;
 
-	if (value == 0)
-		return value;
-	
-	__asm
-	{
-		rsb x, value, #0
-		and x, x, value
-		clz x, x
-		rsb x, x, #32
-	}
+    __asm
+    {
+        rsb x, value, #0
+        and x, x, value
+        clz x, x
+        rsb x, x, #32
+    }
 
-	return x;
+    return x;
 }
 #elif defined(__IAR_SYSTEMS_ICC__)
 int __rt_ffs(int value)
 {
-	if (value == 0)
-		return value;
+    if (value == 0)
+        return value;
 
-	__ASM("RSB  r4, r0, #0");
-	__ASM("AND  r4, r4, r0");
-	__ASM("CLZ  r4, r4");
-	__ASM("RSB  r0, r4, #32");
+    __ASM("RSB  r4, r0, #0");
+    __ASM("AND  r4, r4, r0");
+    __ASM("CLZ  r4, r4");
+    __ASM("RSB  r0, r4, #32");
 }
 #elif defined(__GNUC__)
 int __rt_ffs(int value)
 {
-	if (value == 0)
-		return value;
+    if (value == 0)
+        return value;
 
-	value &= (-value);
-	asm ("clz %0, %1": "=r"(value) :"r"(value));
+    value &= (-value);
+    asm ("clz %0, %1": "=r"(value) :"r"(value));
 
-	return (32 - value);
+    return (32 - value);
 }
 #endif
 
diff --git a/libcpu/arm/armv6/mmu.c b/libcpu/arm/armv6/mmu.c
index ae3cf73559..deb2f8365f 100644
--- a/libcpu/arm/armv6/mmu.c
+++ b/libcpu/arm/armv6/mmu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,411 +12,411 @@
 #ifdef __CC_ARM
 void mmu_setttbase(rt_uint32_t i)
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	/* Invalidates all TLBs.Domain access is selected as
-	 * client by configuring domain access register,
-	 * in that case access controlled by permission value
-	 * set by page table entry
-	 */
-	value = 0;
-	__asm volatile
-	{
-		mcr p15, 0, value, c8, c7, 0
-	}
+    /* Invalidates all TLBs.Domain access is selected as
+     * client by configuring domain access register,
+     * in that case access controlled by permission value
+     * set by page table entry
+     */
+    value = 0;
+    __asm volatile
+    {
+        mcr p15, 0, value, c8, c7, 0
+    }
 
-	value = 0x55555555;
-	__asm volatile
-	{
-		mcr p15, 0, value, c3, c0, 0
-			mcr p15, 0, i, c2, c0, 0
-	}
+    value = 0x55555555;
+    __asm volatile
+    {
+        mcr p15, 0, value, c3, c0, 0
+            mcr p15, 0, i, c2, c0, 0
+    }
 }
 
 void mmu_set_domain(rt_uint32_t i)
 {
-	__asm volatile
-	{
-		mcr p15,0, i, c3, c0,  0
-	}
+    __asm volatile
+    {
+        mcr p15,0, i, c3, c0,  0
+    }
 }
 
 void mmu_enable()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			orr value, value, #0x01
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            orr value, value, #0x01
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_disable()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			bic value, value, #0x01
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            bic value, value, #0x01
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_enable_icache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			orr value, value, #0x1000
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            orr value, value, #0x1000
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_enable_dcache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			orr value, value, #0x04
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            orr value, value, #0x04
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_disable_icache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			bic value, value, #0x1000
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            bic value, value, #0x1000
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_disable_dcache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			bic value, value, #0x04
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            bic value, value, #0x04
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_enable_alignfault()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			orr value, value, #0x02
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            orr value, value, #0x02
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_disable_alignfault()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	__asm volatile
-	{
-		mrc p15, 0, value, c1, c0, 0
-			bic value, value, #0x02
-			mcr p15, 0, value, c1, c0, 0
-	}
+    __asm volatile
+    {
+        mrc p15, 0, value, c1, c0, 0
+            bic value, value, #0x02
+            mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	__asm volatile
-	{
-		mcr p15, 0, index, c7, c14, 2
-	}
+    __asm volatile
+    {
+        mcr p15, 0, index, c7, c14, 2
+    }
 }
 
 void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while(ptr < buffer + size)
-	{
-		__asm volatile
-		{
-			MCR p15, 0, ptr, c7, c14, 1
-		}
-		ptr += CACHE_LINE_SIZE;
-	}
+    while(ptr < buffer + size)
+    {
+        __asm volatile
+        {
+            MCR p15, 0, ptr, c7, c14, 1
+        }
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		__asm volatile
-		{
-			MCR p15, 0, ptr, c7, c10, 1
-		}
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        __asm volatile
+        {
+            MCR p15, 0, ptr, c7, c10, 1
+        }
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		__asm volatile
-		{
-			MCR p15, 0, ptr, c7, c6, 1
-		}
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        __asm volatile
+        {
+            MCR p15, 0, ptr, c7, c6, 1
+        }
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_tlb()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	value = 0;
-	__asm volatile
-	{
-		mcr p15, 0, value, c8, c7, 0
-	}
+    value = 0;
+    __asm volatile
+    {
+        mcr p15, 0, value, c8, c7, 0
+    }
 }
 
 void mmu_invalidate_icache()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	value = 0;
+    value = 0;
 
-	__asm volatile
-	{
-		mcr p15, 0, value, c7, c5, 0
-	}
+    __asm volatile
+    {
+        mcr p15, 0, value, c7, c5, 0
+    }
 }
 
 
 void mmu_invalidate_dcache_all()
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	value = 0;
+    value = 0;
 
-	__asm volatile
-	{
-		mcr p15, 0, value, c7, c6, 0
-	}
+    __asm volatile
+    {
+        mcr p15, 0, value, c7, c6, 0
+    }
 }
 #elif defined(__GNUC__)
 void mmu_setttbase(register rt_uint32_t i)
 {
-	register rt_uint32_t value;
+    register rt_uint32_t value;
 
-	/* Invalidates all TLBs.Domain access is selected as
-	 * client by configuring domain access register,
-	 * in that case access controlled by permission value
-	 * set by page table entry
-	 */
-	value = 0;
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
+    /* Invalidates all TLBs.Domain access is selected as
+     * client by configuring domain access register,
+     * in that case access controlled by permission value
+     * set by page table entry
+     */
+    value = 0;
+    asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value));
 
-	value = 0x55555555;
-	asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
-	asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
+    value = 0x55555555;
+    asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value));
+    asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i));
 }
 
 void mmu_set_domain(register rt_uint32_t i)
 {
-	asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
+    asm volatile ("mcr p15,0, %0, c3, c0,  0": :"r" (i));
 }
 
 void mmu_enable()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= 0x1;
-	/* Enables the extended page tables to be configured for
-	   the hardware page translation mechanism, Subpage AP bits disabled */
-	i |= (1 << 23); /* support for ARMv6 MMU features */
-	i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
+    i |= 0x1;
+    /* Enables the extended page tables to be configured for
+       the hardware page translation mechanism, Subpage AP bits disabled */
+    i |= (1 << 23); /* support for ARMv6 MMU features */
+    i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~0x1;
+    i &= ~0x1;
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_icache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 12);
+    i |= (1 << 12);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_dcache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 2);
+    i |= (1 << 2);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_icache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 12);
+    i &= ~(1 << 12);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_dcache()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 2);
+    i &= ~(1 << 2);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_enable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i |= (1 << 1);
+    i |= (1 << 1);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_disable_alignfault()
 {
-	register rt_uint32_t i;
+    register rt_uint32_t i;
 
-	/* read control register */
-	asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    /* read control register */
+    asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
 
-	i &= ~(1 << 1);
+    i &= ~(1 << 1);
 
-	/* write back to control register */
-	asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
+    /* write back to control register */
+    asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i));
 }
 
 void mmu_clean_invalidated_cache_index(int index)
 {
-	asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
+    asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index));
 }
 
 void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while(ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
-		ptr += CACHE_LINE_SIZE;
-	}
+    while(ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 
 void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size)
 {
-	unsigned int ptr;
+    unsigned int ptr;
 
-	ptr = buffer & ~(CACHE_LINE_SIZE - 1);
+    ptr = buffer & ~(CACHE_LINE_SIZE - 1);
 
-	while (ptr < buffer + size)
-	{
-		asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
-		ptr += CACHE_LINE_SIZE;
-	}
+    while (ptr < buffer + size)
+    {
+        asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr));
+        ptr += CACHE_LINE_SIZE;
+    }
 }
 
 void mmu_invalidate_tlb()
 {
-	asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0));
 }
 
 void mmu_invalidate_icache()
 {
-	asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));
 }
 
 void mmu_invalidate_dcache_all()
 {
-	asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
+    asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0));
 }
 #endif
 
@@ -426,123 +426,123 @@ static volatile unsigned int _pgd_table[4*1024] ALIGN(16*1024);
  * level2 page table
  * RT_MMU_PTE_SIZE must be 1024*n
  */
-#define RT_MMU_PTE_SIZE		4096
+#define RT_MMU_PTE_SIZE     4096
 static volatile unsigned int _pte_table[RT_MMU_PTE_SIZE] ALIGN(1*1024);
 
 void mmu_create_pgd(struct mem_desc *mdesc)
 {
-	volatile rt_uint32_t *pTT;
-	volatile int i, nSec;
-	pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20);
-	nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20);
-	for(i = 0; i <= nSec; i++)
-	{
-		*pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20);
-		pTT++;
-	}
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20);
+    nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20);
+    for(i = 0; i <= nSec; i++)
+    {
+        *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20);
+        pTT++;
+    }
 }
 
 void mmu_create_pte(struct mem_desc *mdesc)
 {
-	volatile rt_uint32_t *pTT;
-	volatile rt_uint32_t *p_pteentry;
-	int i;
-	rt_uint32_t vaddr;
-	rt_uint32_t total_page = 0;
-	rt_uint32_t pte_offset = 0;
-	rt_uint32_t sect_attr = 0;
+    volatile rt_uint32_t *pTT;
+    volatile rt_uint32_t *p_pteentry;
+    int i;
+    rt_uint32_t vaddr;
+    rt_uint32_t total_page = 0;
+    rt_uint32_t pte_offset = 0;
+    rt_uint32_t sect_attr = 0;
 
-	total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1;
-	pte_offset = mdesc->sect_attr & 0xfffffc00;
-	sect_attr = mdesc->sect_attr & 0x3ff;
-	vaddr = mdesc->vaddr_start;
+    total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1;
+    pte_offset = mdesc->sect_attr & 0xfffffc00;
+    sect_attr = mdesc->sect_attr & 0x3ff;
+    vaddr = mdesc->vaddr_start;
 
-	for(i = 0; i < total_page; i++)
-	{
-		pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20);
-		if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */
-		{
-			*pTT = pte_offset | sect_attr;
-			p_pteentry = (rt_uint32_t *)pte_offset +
-				((vaddr & 0x000ff000) >> 12);
-			pte_offset += 1024;
-		}
-		else /* using old Level 1 page table item */
-		{
-			p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) +
-				((vaddr & 0x000ff000) >> 12);
-		}
+    for(i = 0; i < total_page; i++)
+    {
+        pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20);
+        if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */
+        {
+            *pTT = pte_offset | sect_attr;
+            p_pteentry = (rt_uint32_t *)pte_offset +
+                ((vaddr & 0x000ff000) >> 12);
+            pte_offset += 1024;
+        }
+        else /* using old Level 1 page table item */
+        {
+            p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) +
+                ((vaddr & 0x000ff000) >> 12);
+        }
 
 
-		*p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12);
-		vaddr += 0x1000;
-	}
+        *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12);
+        vaddr += 0x1000;
+    }
 }
 
 static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size)
 {
-	rt_uint32_t pte_offset = 0;
-	rt_uint32_t nsec = 0;
-	/* set page table */
-	for (; size > 0; size--)
-	{
-		if (mdesc->mapped_mode == PAGE_MAPPED)
-		{
-			nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20;
-			mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset;
-			pte_offset += nsec << 10;
-		}
-		if (pte_offset >= RT_MMU_PTE_SIZE)
-		{
-			rt_kprintf("PTE table size too little\n");
-			RT_ASSERT(0);
-		}
+    rt_uint32_t pte_offset = 0;
+    rt_uint32_t nsec = 0;
+    /* set page table */
+    for (; size > 0; size--)
+    {
+        if (mdesc->mapped_mode == PAGE_MAPPED)
+        {
+            nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20;
+            mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset;
+            pte_offset += nsec << 10;
+        }
+        if (pte_offset >= RT_MMU_PTE_SIZE)
+        {
+            rt_kprintf("PTE table size too little\n");
+            RT_ASSERT(0);
+        }
 
-		mdesc++;
-	}
+        mdesc++;
+    }
 }
 
 
 void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size)
 {
-	/* disable I/D cache */
-	mmu_disable_dcache();
-	mmu_disable_icache();
-	mmu_disable();
-	mmu_invalidate_tlb();
+    /* disable I/D cache */
+    mmu_disable_dcache();
+    mmu_disable_icache();
+    mmu_disable();
+    mmu_invalidate_tlb();
 
-	/* clear pgd and pte table */
-	rt_memset((void *)_pgd_table, 0, 16*1024);
-	rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE);
-	build_pte_mem_desc(mdesc, size);
-	/* set page table */
-	for (; size > 0; size--)
-	{
-		if (mdesc->mapped_mode == SECT_MAPPED)
-		{
-			mmu_create_pgd(mdesc);
-		}
-		else
-		{
-			mmu_create_pte(mdesc);
-		}
+    /* clear pgd and pte table */
+    rt_memset((void *)_pgd_table, 0, 16*1024);
+    rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE);
+    build_pte_mem_desc(mdesc, size);
+    /* set page table */
+    for (; size > 0; size--)
+    {
+        if (mdesc->mapped_mode == SECT_MAPPED)
+        {
+            mmu_create_pgd(mdesc);
+        }
+        else
+        {
+            mmu_create_pte(mdesc);
+        }
 
-		mdesc++;
-	}
+        mdesc++;
+    }
 
-	/* set MMU table address */
-	mmu_setttbase((rt_uint32_t)_pgd_table);
+    /* set MMU table address */
+    mmu_setttbase((rt_uint32_t)_pgd_table);
 
-	/* enables MMU */
-	mmu_enable();
+    /* enables MMU */
+    mmu_enable();
 
-	/* enable Instruction Cache */
-	mmu_enable_icache();
+    /* enable Instruction Cache */
+    mmu_enable_icache();
 
-	/* enable Data Cache */
-	mmu_enable_dcache();
+    /* enable Data Cache */
+    mmu_enable_dcache();
 
-	mmu_invalidate_icache();
-	mmu_invalidate_dcache_all();
+    mmu_invalidate_icache();
+    mmu_invalidate_dcache_all();
 }
 
diff --git a/libcpu/arm/armv6/mmu.h b/libcpu/arm/armv6/mmu.h
index 4df61ac21d..18355378bd 100644
--- a/libcpu/arm/armv6/mmu.h
+++ b/libcpu/arm/armv6/mmu.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -12,7 +12,7 @@
 
 #include <rtthread.h>
 
-#define CACHE_LINE_SIZE	32
+#define CACHE_LINE_SIZE 32
 
 /*
  * Hardware page table definitions.
@@ -30,7 +30,7 @@
 /*
  *   - section
  */
-#define PGD_SECT_BUFFERABLE	(1 << 2)
+#define PGD_SECT_BUFFERABLE (1 << 2)
 #define PGD_SECT_CACHEABLE  (1 << 3)
 #define PGD_SECT_XN         (1 << 4)    /* ARMv6 */
 #define PGD_SECT_AP0        (1 << 10)
@@ -155,35 +155,35 @@
 #define PAGE_RONX_FAULT  (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */
 
 
-#define DESC_SEC		(0x2|(1<<4))
-#define CB				(3<<2)  //cache_on, write_back
-#define CNB				(2<<2)  //cache_on, write_through
-#define NCB				(1<<2)  //cache_off,WR_BUF on
-#define NCNB			(0<<2)  //cache_off,WR_BUF off
-#define AP_RW			(3<<10) //supervisor=RW, user=RW
-#define AP_RO			(2<<10) //supervisor=RW, user=RO
+#define DESC_SEC        (0x2|(1<<4))
+#define CB              (3<<2)  //cache_on, write_back
+#define CNB             (2<<2)  //cache_on, write_through
+#define NCB             (1<<2)  //cache_off,WR_BUF on
+#define NCNB            (0<<2)  //cache_off,WR_BUF off
+#define AP_RW           (3<<10) //supervisor=RW, user=RW
+#define AP_RO           (2<<10) //supervisor=RW, user=RO
 
-#define DOMAIN_FAULT	(0x0)
-#define DOMAIN_CHK		(0x1)
-#define DOMAIN_NOTCHK	(0x3)
-#define DOMAIN0			(0x0<<5)
-#define DOMAIN1			(0x1<<5)
+#define DOMAIN_FAULT    (0x0)
+#define DOMAIN_CHK      (0x1)
+#define DOMAIN_NOTCHK   (0x3)
+#define DOMAIN0         (0x0<<5)
+#define DOMAIN1         (0x1<<5)
 
-#define DOMAIN0_ATTR	(DOMAIN_CHK<<0)
-#define DOMAIN1_ATTR	(DOMAIN_FAULT<<2)
+#define DOMAIN0_ATTR    (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR    (DOMAIN_FAULT<<2)
 
-#define RW_CB		(AP_RW|DOMAIN0|CB|DESC_SEC)		/* Read/Write, cache, write back */
-#define RW_CNB		(AP_RW|DOMAIN0|CNB|DESC_SEC)	/* Read/Write, cache, write through */
-#define RW_NCNB		(AP_RW|DOMAIN0|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
-#define RW_FAULT	(AP_RW|DOMAIN1|NCNB|DESC_SEC)	/* Read/Write without cache and write buffer */
+#define RW_CB       (AP_RW|DOMAIN0|CB|DESC_SEC)     /* Read/Write, cache, write back */
+#define RW_CNB      (AP_RW|DOMAIN0|CNB|DESC_SEC)    /* Read/Write, cache, write through */
+#define RW_NCNB     (AP_RW|DOMAIN0|NCNB|DESC_SEC)   /* Read/Write without cache and write buffer */
+#define RW_FAULT    (AP_RW|DOMAIN1|NCNB|DESC_SEC)   /* Read/Write without cache and write buffer */
 
 struct mem_desc {
-	rt_uint32_t vaddr_start;
-	rt_uint32_t vaddr_end;
-	rt_uint32_t paddr_start;
-	rt_uint32_t sect_attr;   /* when page mapped */
-	rt_uint32_t page_attr;   /* only sector mapped valid */
-	rt_uint32_t mapped_mode;
+    rt_uint32_t vaddr_start;
+    rt_uint32_t vaddr_end;
+    rt_uint32_t paddr_start;
+    rt_uint32_t sect_attr;   /* when page mapped */
+    rt_uint32_t page_attr;   /* only sector mapped valid */
+    rt_uint32_t mapped_mode;
 #define     SECT_MAPPED  0
 #define     PAGE_MAPPED  1
 };
diff --git a/libcpu/arm/armv6/stack.c b/libcpu/arm/armv6/stack.c
index 52de999fc2..33a8d96d48 100644
--- a/libcpu/arm/armv6/stack.c
+++ b/libcpu/arm/armv6/stack.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/arm/armv6/vfp.c b/libcpu/arm/armv6/vfp.c
index 9aa8d34fcc..fc07f5a309 100644
--- a/libcpu/arm/armv6/vfp.c
+++ b/libcpu/arm/armv6/vfp.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/arm/armv6/vfp.h b/libcpu/arm/armv6/vfp.h
index c347dbe0a6..fd084f3aef 100644
--- a/libcpu/arm/armv6/vfp.h
+++ b/libcpu/arm/armv6/vfp.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -87,7 +87,7 @@
  })
 
 #define vmsr(vfp, var) \
-    asm("vmsr  "#vfp",  %0"	\
+    asm("vmsr  "#vfp",  %0" \
        : : "r" (var) : "cc")