diff options
| author | WangHuachen <[email protected]> | 2020-11-08 19:30:50 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2020-11-08 19:30:50 +0800 |
| commit | 9756c77f0447f9ce4f00a37600298a1f1fd90cda (patch) | |
| tree | 093247a1719c087dba33783be3a4ee44c1026b2d /libcpu/arm/cortex-a | |
| parent | 9545529b33cbaae137f1e389dd0e3a5233d516da (diff) | |
| parent | 4b2b9a87c6f0a87b125e5c5a18bcfcf663de9fbb (diff) | |
Merge pull request #1 from RT-Thread/master
同步原有仓库
Diffstat (limited to 'libcpu/arm/cortex-a')
| -rw-r--r-- | libcpu/arm/cortex-a/gic.c | 3 | ||||
| -rw-r--r-- | libcpu/arm/cortex-a/start_gcc.S | 20 |
2 files changed, 21 insertions, 2 deletions
diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c index 2a46142b54..2e94b88277 100644 --- a/libcpu/arm/cortex-a/gic.c +++ b/libcpu/arm/cortex-a/gic.c @@ -74,9 +74,8 @@ void arm_gic_ack(rt_uint32_t index, int irq) irq = irq - _gic_table[index].offset; RT_ASSERT(irq >= 0); - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; } void arm_gic_mask(rt_uint32_t index, int irq) diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index 268cc7ef56..2e99db7218 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -52,6 +52,26 @@ stack_top: /* reset entry */ .globl _reset _reset: +#ifdef ARCH_ARMV8 + /* Check for HYP mode */ + mrs r0, cpsr_all + and r0, r0, #0x1F + mov r8, #0x1A + cmp r0, r8 + beq overHyped + b continue + +overHyped: /* Get out of HYP mode */ + adr r1, continue + msr ELR_hyp, r1 + mrs r1, cpsr_all + and r1, r1, #0x1f ;@ CPSR_MODE_MASK + orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR + msr SPSR_hyp, r1 + eret + +continue: +#endif /* set the cpu to SVC32 mode and disable interrupt */ cps #Mode_SVC |