diff options
| author | WangHuachen <[email protected]> | 2020-11-08 19:30:50 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2020-11-08 19:30:50 +0800 |
| commit | 9756c77f0447f9ce4f00a37600298a1f1fd90cda (patch) | |
| tree | 093247a1719c087dba33783be3a4ee44c1026b2d /libcpu/arm/cortex-m0 | |
| parent | 9545529b33cbaae137f1e389dd0e3a5233d516da (diff) | |
| parent | 4b2b9a87c6f0a87b125e5c5a18bcfcf663de9fbb (diff) | |
Merge pull request #1 from RT-Thread/master
同步原有仓库
Diffstat (limited to 'libcpu/arm/cortex-m0')
| -rw-r--r-- | libcpu/arm/cortex-m0/context_gcc.S | 4 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m0/context_iar.S | 4 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m0/context_rvds.S | 4 |
3 files changed, 6 insertions, 6 deletions
diff --git a/libcpu/arm/cortex-m0/context_gcc.S b/libcpu/arm/cortex-m0/context_gcc.S index d9993247e2..a504ee076e 100644 --- a/libcpu/arm/cortex-m0/context_gcc.S +++ b/libcpu/arm/cortex-m0/context_gcc.S @@ -22,7 +22,7 @@ .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ .equ NVIC_SHPR3, 0xE000ED20 /* system priority register (3) */ - .equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ + .equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */ .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ /* @@ -159,7 +159,7 @@ rt_hw_context_switch_to: MOVS R0, #1 STR R0, [R1] - /* set the PendSV exception priority */ + /* set the PendSV and SysTick exception priority */ LDR R0, =NVIC_SHPR3 LDR R1, =NVIC_PENDSV_PRI LDR R2, [R0,#0x00] /* read */ diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S index 50d3781359..6f410d1a24 100644 --- a/libcpu/arm/cortex-m0/context_iar.S +++ b/libcpu/arm/cortex-m0/context_iar.S @@ -19,7 +19,7 @@ SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception SECTION .text:CODE(2) @@ -163,7 +163,7 @@ rt_hw_context_switch_to: MOVS r0, #1 STR r0, [r1] - ; set the PendSV exception priority + ; set the PendSV and SysTick exception priority LDR r0, =NVIC_SHPR3 LDR r1, =NVIC_PENDSV_PRI LDR r2, [r0,#0x00] ; read diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S index fb9ce9b4bf..072486587c 100644 --- a/libcpu/arm/cortex-m0/context_rvds.S +++ b/libcpu/arm/cortex-m0/context_rvds.S @@ -19,7 +19,7 @@ SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SHPR3 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception AREA |.text|, CODE, READONLY, ALIGN=2 @@ -168,7 +168,7 @@ rt_hw_context_switch_to PROC MOVS r0, #1 STR r0, [r1] - ; set the PendSV exception priority + ; set the PendSV and SysTick exception priority LDR r0, =NVIC_SHPR3 LDR r1, =NVIC_PENDSV_PRI LDR r2, [r0,#0x00] ; read |