[arm][cortex-m4] Add hardware stack guard support

Enable RT_USING_HW_STACK_GUARD on Cortex-M4, which was previously only
available on Cortex-M7 and Cortex-M33.

Core porting (libcpu/arm/cortex-m4/):
- Add mpu.c/mpu.h/mputype.h aligned with the Cortex-M7 MPU layer. The only
  difference is the default memory type attribute: Cortex-M4 has no L1 cache,
  so the cacheability bits are reduced to three cases.
- Add rt_hw_stack_guard_init() to cpuport.c.
- Add missing #include <rtconfig.h> to context_gcc.S and invoke
  rt_hw_mpu_table_switch() in the PendSV context switch path.
- Update SConscript to exclude mpu.c when memory protection is disabled.

BSP reference (bsp/stm32/stm32f407-fk407m2-zgt6/):
- board.h: include rtthread.h and define NUM_STATIC_REGIONS.
- board.c: define static_regions[] marking the Flash region read-only,
  guarded by RT_USING_MEM_PROTECTION so it is not enabled by default.

1 files changed, 13 insertions, 0 deletions

diff --git a/libcpu/arm/cortex-m4/SConscript b/libcpu/arm/cortex-m4/SConscript
index 3ecbea8de3..2ac22c8e4d 100644
--- a/libcpu/arm/cortex-m4/SConscript
+++ b/libcpu/arm/cortex-m4/SConscript
@@ -21,6 +21,19 @@ if rtconfig.PLATFORM in ['gcc', 'llvm-arm']:
 if rtconfig.PLATFORM in ['iccarm']:
     src += Glob('*_iar.S')
 
+using_mpu = (
+    GetDepend('RT_USING_MEM_PROTECTION') or
+    GetDepend('RT_USING_HW_STACK_GUARD')
+)
+
+if using_mpu:
+    if rtconfig.PLATFORM not in ['gcc', 'llvm-arm']:
+        raise RuntimeError(
+            'Cortex-M4 memory protection currently supports GCC only'
+        )
+else:
+    SrcRemove(src, 'mpu.c')
+
 group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH)
 
 Return('group')