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| author | Bernard Xiong <[email protected]> | 2021-03-31 13:52:30 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-03-31 13:52:30 +0800 |
| commit | 3f64efd2a3c8265f1e5ddcea83e2dededf8eea8b (patch) | |
| tree | ad064f1ab426c4a46dec87fa807993ce07d42e9b /libcpu/arm/cortex-m7/cpu_cache.c | |
| parent | ac41503a4ab45ca3a647912e5b36fff7301c1399 (diff) | |
| parent | 6c907c3a477b1f34ca1adb277748c3306110cabf (diff) | |
Merge pull request #4534 from mysterywolf/libcpu
[libcpu] auto formatted
Diffstat (limited to 'libcpu/arm/cortex-m7/cpu_cache.c')
| -rw-r--r-- | libcpu/arm/cortex-m7/cpu_cache.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c index 350b819c00..417558e285 100644 --- a/libcpu/arm/cortex-m7/cpu_cache.c +++ b/libcpu/arm/cortex-m7/cpu_cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #include <rtdef.h> #include <board.h> -/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ +/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ #define L1CACHE_LINESIZE_BYTE (32) void rt_hw_cpu_icache_enable(void) |