diff options
| author | WangHuachen <[email protected]> | 2020-11-08 19:30:50 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2020-11-08 19:30:50 +0800 |
| commit | 9756c77f0447f9ce4f00a37600298a1f1fd90cda (patch) | |
| tree | 093247a1719c087dba33783be3a4ee44c1026b2d /libcpu/arm/cortex-m7 | |
| parent | 9545529b33cbaae137f1e389dd0e3a5233d516da (diff) | |
| parent | 4b2b9a87c6f0a87b125e5c5a18bcfcf663de9fbb (diff) | |
Merge pull request #1 from RT-Thread/master
同步原有仓库
Diffstat (limited to 'libcpu/arm/cortex-m7')
| -rw-r--r-- | libcpu/arm/cortex-m7/context_gcc.S | 4 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m7/context_iar.S | 4 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m7/context_rvds.S | 4 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m7/cpuport.c | 4 |
4 files changed, 8 insertions, 8 deletions
diff --git a/libcpu/arm/cortex-m7/context_gcc.S b/libcpu/arm/cortex-m7/context_gcc.S index 420f4f8ae3..f569a35863 100644 --- a/libcpu/arm/cortex-m7/context_gcc.S +++ b/libcpu/arm/cortex-m7/context_gcc.S @@ -25,7 +25,7 @@ .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ .equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ -.equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ +.equ NVIC_PENDSV_PRI, 0xFFFF0000 /* PendSV and SysTick priority value (lowest) */ .equ NVIC_PENDSVSET, 0x10000000 /* value to trigger PendSV exception */ /* @@ -182,7 +182,7 @@ rt_hw_context_switch_to: MOV r0, #1 STR r0, [r1] - /* set the PendSV exception priority */ + /* set the PendSV and SysTick exception priority */ LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI LDR.W r2, [r0,#0x00] /* read */ diff --git a/libcpu/arm/cortex-m7/context_iar.S b/libcpu/arm/cortex-m7/context_iar.S index 06b8c7f884..18d6a3f784 100644 --- a/libcpu/arm/cortex-m7/context_iar.S +++ b/libcpu/arm/cortex-m7/context_iar.S @@ -21,7 +21,7 @@ SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception SECTION .text:CODE(2) @@ -186,7 +186,7 @@ rt_hw_context_switch_to: MOV r0, #1 STR r0, [r1] - ; set the PendSV exception priority + ; set the PendSV and SysTick exception priority LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI LDR.W r2, [r0,#0x00] ; read diff --git a/libcpu/arm/cortex-m7/context_rvds.S b/libcpu/arm/cortex-m7/context_rvds.S index ea9e9cb8b3..d051f819c1 100644 --- a/libcpu/arm/cortex-m7/context_rvds.S +++ b/libcpu/arm/cortex-m7/context_rvds.S @@ -20,7 +20,7 @@ SCB_VTOR EQU 0xE000ED08 ; Vector Table Offset Register NVIC_INT_CTRL EQU 0xE000ED04 ; interrupt control state register NVIC_SYSPRI2 EQU 0xE000ED20 ; system priority register (2) -NVIC_PENDSV_PRI EQU 0x00FF0000 ; PendSV priority value (lowest) +NVIC_PENDSV_PRI EQU 0xFFFF0000 ; PendSV and SysTick priority value (lowest) NVIC_PENDSVSET EQU 0x10000000 ; value to trigger PendSV exception AREA |.text|, CODE, READONLY, ALIGN=2 @@ -186,7 +186,7 @@ rt_hw_context_switch_to PROC MOV r0, #1 STR r0, [r1] - ; set the PendSV exception priority + ; set the PendSV and SysTick exception priority LDR r0, =NVIC_SYSPRI2 LDR r1, =NVIC_PENDSV_PRI LDR.W r2, [r0,#0x00] ; read diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c index c22242f140..e701a52307 100644 --- a/libcpu/arm/cortex-m7/cpuport.c +++ b/libcpu/arm/cortex-m7/cpuport.c @@ -472,13 +472,13 @@ int __rt_ffs(int value) { __asm volatile( "CMP r0, #0x00 \n" - "BEQ exit \n" + "BEQ 1f \n" "RBIT r0, r0 \n" "CLZ r0, r0 \n" "ADDS r0, r0, #0x01 \n" - "exit: \n" + "1: \n" : "=r"(value) : "r"(value) |