diff options
| author | Bernard Xiong <[email protected]> | 2021-05-28 16:20:08 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-05-28 16:20:08 +0800 |
| commit | 92beddf3bccf6346e26aa097f82464456fb8e6bd (patch) | |
| tree | 197e4a108118dda016ea02274172f0c40e7ee8ed /libcpu/arm/dm36x/mmu.h | |
| parent | b18a99b44240ec3152011e159cc24a5af8dff0ce (diff) | |
| parent | 03f4d40e30f3c94e1db0b3a65b3610dee695694a (diff) | |
Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5
[lts 3.1.x] format codes
Diffstat (limited to 'libcpu/arm/dm36x/mmu.h')
| -rw-r--r-- | libcpu/arm/dm36x/mmu.h | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/libcpu/arm/dm36x/mmu.h b/libcpu/arm/dm36x/mmu.h index 3410b881ac..60a4e3c6e9 100644 --- a/libcpu/arm/dm36x/mmu.h +++ b/libcpu/arm/dm36x/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ #include <rtthread.h> -#define CACHE_LINE_SIZE 32 +#define CACHE_LINE_SIZE 32 /* * Hardware page table definitions. @@ -30,7 +30,7 @@ /* * - section */ -#define PGD_SECT_BUFFERABLE (1 << 2) +#define PGD_SECT_BUFFERABLE (1 << 2) #define PGD_SECT_CACHEABLE (1 << 3) #define PGD_SECT_XN (1 << 4) /* ARMv6 */ #define PGD_SECT_AP0 (1 << 10) @@ -133,14 +133,14 @@ #define PAGE_RO_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */ struct mem_desc { - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t sect_attr; /* when page mapped */ - rt_uint32_t page_attr; /* only sector mapped valid */ - rt_uint32_t mapped_mode; - #define SECT_MAPPED 0 - #define PAGE_MAPPED 1 + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t sect_attr; /* when page mapped */ + rt_uint32_t page_attr; /* only sector mapped valid */ + rt_uint32_t mapped_mode; + #define SECT_MAPPED 0 + #define PAGE_MAPPED 1 }; |