Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5

[lts 3.1.x] format codes

1 files changed, 63 insertions, 63 deletions

diff --git a/libcpu/arm/s3c24x0/cpu.c b/libcpu/arm/s3c24x0/cpu.c
index 4d3bf3c1ab..ac4037c7b8 100644
--- a/libcpu/arm/s3c24x0/cpu.c
+++ b/libcpu/arm/s3c24x0/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,76 +17,76 @@
  */
 /*@{*/
 
-#define ICACHE_MASK	(rt_uint32_t)(1 << 12)
-#define DCACHE_MASK	(rt_uint32_t)(1 << 2)
+#define ICACHE_MASK (rt_uint32_t)(1 << 12)
+#define DCACHE_MASK (rt_uint32_t)(1 << 2)
 
 #ifdef __GNUC__
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
-	return i;
+    asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"orr  r0,r0,%0\n\t"			\
-	   	"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "orr  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	__asm__ __volatile__(			\
-		"mrc  p15,0,r0,c1,c0,0\n\t"	\
-		"bic  r0,r0,%0\n\t"			\
-		"mcr  p15,0,r0,c1,c0,0"		\
-		:							\
-		:"r" (bit)					\
-		:"memory");
+    __asm__ __volatile__(           \
+        "mrc  p15,0,r0,c1,c0,0\n\t" \
+        "bic  r0,r0,%0\n\t"         \
+        "mcr  p15,0,r0,c1,c0,0"     \
+        :                           \
+        :"r" (bit)                  \
+        :"memory");
 }
 #endif
 
 #ifdef __CC_ARM
 rt_inline rt_uint32_t cp15_rd(void)
 {
-	rt_uint32_t i;
+    rt_uint32_t i;
 
-	__asm
-	{
-		mrc p15, 0, i, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, i, c1, c0, 0
+    }
 
-	return i;
+    return i;
 }
 
 rt_inline void cache_enable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
+    rt_uint32_t value;
 
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		orr value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        orr value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 
 rt_inline void cache_disable(rt_uint32_t bit)
 {
-	rt_uint32_t value;
+    rt_uint32_t value;
 
-	__asm
-	{
-		mrc p15, 0, value, c1, c0, 0
-		bic value, value, bit
-		mcr p15, 0, value, c1, c0, 0
-	}
+    __asm
+    {
+        mrc p15, 0, value, c1, c0, 0
+        bic value, value, bit
+        mcr p15, 0, value, c1, c0, 0
+    }
 }
 #endif
 
@@ -96,7 +96,7 @@ rt_inline void cache_disable(rt_uint32_t bit)
  */
 void rt_hw_cpu_icache_enable()
 {
-	cache_enable(ICACHE_MASK);
+    cache_enable(ICACHE_MASK);
 }
 
 /**
@@ -105,7 +105,7 @@ void rt_hw_cpu_icache_enable()
  */
 void rt_hw_cpu_icache_disable()
 {
-	cache_disable(ICACHE_MASK);
+    cache_disable(ICACHE_MASK);
 }
 
 /**
@@ -114,7 +114,7 @@ void rt_hw_cpu_icache_disable()
  */
 rt_base_t rt_hw_cpu_icache_status()
 {
-	return (cp15_rd() & ICACHE_MASK);
+    return (cp15_rd() & ICACHE_MASK);
 }
 
 /**
@@ -123,7 +123,7 @@ rt_base_t rt_hw_cpu_icache_status()
  */
 void rt_hw_cpu_dcache_enable()
 {
-	cache_enable(DCACHE_MASK);
+    cache_enable(DCACHE_MASK);
 }
 
 /**
@@ -132,7 +132,7 @@ void rt_hw_cpu_dcache_enable()
  */
 void rt_hw_cpu_dcache_disable()
 {
-	cache_disable(DCACHE_MASK);
+    cache_disable(DCACHE_MASK);
 }
 
 /**
@@ -141,7 +141,7 @@ void rt_hw_cpu_dcache_disable()
  */
 rt_base_t rt_hw_cpu_dcache_status()
 {
-	return (cp15_rd() & DCACHE_MASK);
+    return (cp15_rd() & DCACHE_MASK);
 }
 
 /**
@@ -150,21 +150,21 @@ rt_base_t rt_hw_cpu_dcache_status()
  */
 void rt_hw_cpu_reset()
 {
-	/* Disable all interrupt except the WDT */
-	INTMSK = (~((rt_uint32_t)1 << INTWDT));
+    /* Disable all interrupt except the WDT */
+    INTMSK = (~((rt_uint32_t)1 << INTWDT));
 
-	/* Disable watchdog */
-	WTCON = 0x0000;
+    /* Disable watchdog */
+    WTCON = 0x0000;
 
-	/* Initialize watchdog timer count register */
-	WTCNT = 0x0001;
+    /* Initialize watchdog timer count register */
+    WTCNT = 0x0001;
 
-	/* Enable watchdog timer; assert reset at timer timeout */
-	WTCON = 0x0021;
+    /* Enable watchdog timer; assert reset at timer timeout */
+    WTCON = 0x0021;
 
-	while(1);	/* loop forever and wait for reset to happen */
+    while(1);   /* loop forever and wait for reset to happen */
 
-	/* NEVER REACHED */
+    /* NEVER REACHED */
 }
 
 /**
@@ -173,14 +173,14 @@ void rt_hw_cpu_reset()
  */
 void rt_hw_cpu_shutdown()
 {
-	rt_uint32_t level;
-	rt_kprintf("shutdown...\n");
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
 
-	level = rt_hw_interrupt_disable();
-	while (level)
-	{
-		RT_ASSERT(0);
-	}
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
 }
 
 /*@}*/