Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5

[lts 3.1.x] format codes

6 files changed, 422 insertions, 422 deletions

diff --git a/libcpu/arm/s3c44b0/cpu.c b/libcpu/arm/s3c44b0/cpu.c
index 03ebefba18..c9af445307 100644
--- a/libcpu/arm/s3c44b0/cpu.c
+++ b/libcpu/arm/s3c44b0/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,29 +22,29 @@
  */
 void rt_hw_cpu_icache_enable()
 {
-	rt_base_t reg;
+    rt_base_t reg;
 
-	volatile int i;
-	/* flush cycle */
-	for(i = 0x10002000; i < 0x10004800; i+=16)
-	{
-		*((int *)i)=0x0;
-	}
+    volatile int i;
+    /* flush cycle */
+    for(i = 0x10002000; i < 0x10004800; i+=16)
+    {
+        *((int *)i)=0x0;
+    }
 
-	/*
-	 *	Init cache
-	 *	Non-cacheable area (everything outside RAM)
-	 *	0x0000:0000 - 0x0C00:0000
-	 */
-	NCACHBE0 = 0xC0000000;
-	NCACHBE1 = 0x00000000;
+    /*
+     *  Init cache
+     *  Non-cacheable area (everything outside RAM)
+     *  0x0000:0000 - 0x0C00:0000
+     */
+    NCACHBE0 = 0xC0000000;
+    NCACHBE1 = 0x00000000;
 
-	/*
-		Enable chache
-	*/
-	reg = SYSCFG;
-	reg |= 0x00000006; /* 8kB */
-	SYSCFG = reg;
+    /*
+        Enable chache
+    */
+    reg = SYSCFG;
+    reg |= 0x00000006; /* 8kB */
+    SYSCFG = reg;
 }
 
 /**
@@ -53,11 +53,11 @@ void rt_hw_cpu_icache_enable()
  */
 void rt_hw_cpu_icache_disable()
 {
-	rt_base_t reg;
+    rt_base_t reg;
 
-	reg = SYSCFG;
-	reg &= ~0x00000006; /* 8kB */
-	SYSCFG = reg;
+    reg = SYSCFG;
+    reg &= ~0x00000006; /* 8kB */
+    SYSCFG = reg;
 }
 
 /**
@@ -66,7 +66,7 @@ void rt_hw_cpu_icache_disable()
  */
 rt_base_t rt_hw_cpu_icache_status()
 {
-	return 0;
+    return 0;
 }
 
 /**
@@ -75,7 +75,7 @@ rt_base_t rt_hw_cpu_icache_status()
  */
 void rt_hw_cpu_dcache_enable()
 {
-	rt_hw_cpu_icache_enable();
+    rt_hw_cpu_icache_enable();
 }
 
 /**
@@ -84,7 +84,7 @@ void rt_hw_cpu_dcache_enable()
  */
 void rt_hw_cpu_dcache_disable()
 {
-	rt_hw_cpu_icache_disable();
+    rt_hw_cpu_icache_disable();
 }
 
 /**
@@ -93,7 +93,7 @@ void rt_hw_cpu_dcache_disable()
  */
 rt_base_t rt_hw_cpu_dcache_status()
 {
-	return rt_hw_cpu_icache_status();
+    return rt_hw_cpu_icache_status();
 }
 
 /**
@@ -110,9 +110,9 @@ void rt_hw_cpu_reset()
  */
 void rt_hw_cpu_shutdown()
 {
-	rt_kprintf("shutdown...\n");
+    rt_kprintf("shutdown...\n");
 
-	while (1);
+    while (1);
 }
 
 /*@}*/
diff --git a/libcpu/arm/s3c44b0/interrupt.c b/libcpu/arm/s3c44b0/interrupt.c
index 6b3eed4a39..5464011dd2 100644
--- a/libcpu/arm/s3c44b0/interrupt.c
+++ b/libcpu/arm/s3c44b0/interrupt.c
@@ -1,19 +1,19 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2006-09-06     XuXinming    first version
- * 2006-09-15     Bernard      add interrupt bank 0..3 for more effective 
+ * 2006-09-15     Bernard      add interrupt bank 0..3 for more effective
  *                             in irq trap
  */
 
 #include <rtthread.h>
 #include "s3c44b0.h"
 
-#define MAX_HANDLERS	26
+#define MAX_HANDLERS    26
 
 extern rt_uint32_t rt_interrupt_nest;
 
@@ -34,7 +34,7 @@ unsigned char interrupt_bank3[256];
 
 void rt_hw_interrupt_handle(int vector)
 {
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
 }
 
 /**
@@ -42,70 +42,70 @@ void rt_hw_interrupt_handle(int vector)
  */
 void rt_hw_interrupt_init()
 {
-	register int i;
+    register int i;
 
-	/* all interrupt disabled include global bit */
-	INTMSK = 0x07ffffff;
-	
-	/* clear pending register */
-   	I_ISPC = 0x03ffffff;
-   	
-	/* non-vector mode IRQ enable */
-	INTCON = 0x5;
-	
-	/* all IRQ mode */
-	INTMOD = 0x0;
+    /* all interrupt disabled include global bit */
+    INTMSK = 0x07ffffff;
 
-	/* init exceptions table */
-	for(i=0; i<MAX_HANDLERS; i++)
-	{
-		isr_table[i] = rt_hw_interrupt_handle;
-	}
+    /* clear pending register */
+    I_ISPC = 0x03ffffff;
 
-	for ( i = 0; i < 256; i++)
-	{
-		interrupt_bank0[i] = 0;
-		interrupt_bank1[i] = 0;
-		interrupt_bank2[i] = 0;
-		interrupt_bank3[i] = 0;
-	}
+    /* non-vector mode IRQ enable */
+    INTCON = 0x5;
 
-	/* setup interrupt bank table */
-	interrupt_bank0[1]	= 0;
-	interrupt_bank0[2]	= 1;
-	interrupt_bank0[4]	= 2;
-	interrupt_bank0[8]	= 3;
-	interrupt_bank0[16]	= 4;
-	interrupt_bank0[32]	= 5;
-	interrupt_bank0[64]	= 6;
-	interrupt_bank0[128]= 7;
+    /* all IRQ mode */
+    INTMOD = 0x0;
 
-	interrupt_bank1[1]	= 8;
-	interrupt_bank1[2]	= 9;
-	interrupt_bank1[4]	= 10;
-	interrupt_bank1[8]	= 11;
-	interrupt_bank1[16]	= 12;
-	interrupt_bank1[32]	= 13;
-	interrupt_bank1[64]	= 14;
-	interrupt_bank1[128]= 15;
+    /* init exceptions table */
+    for(i=0; i<MAX_HANDLERS; i++)
+    {
+        isr_table[i] = rt_hw_interrupt_handle;
+    }
 
-	interrupt_bank2[1]	= 16;
-	interrupt_bank2[2]	= 17;
-	interrupt_bank2[4]	= 18;
-	interrupt_bank2[8]	= 19;
-	interrupt_bank2[16]	= 20;
-	interrupt_bank2[32]	= 21;
-	interrupt_bank2[64]	= 22;
-	interrupt_bank2[128]= 23;
+    for ( i = 0; i < 256; i++)
+    {
+        interrupt_bank0[i] = 0;
+        interrupt_bank1[i] = 0;
+        interrupt_bank2[i] = 0;
+        interrupt_bank3[i] = 0;
+    }
 
-	interrupt_bank3[1]	= 24;
-	interrupt_bank3[2]	= 25;
+    /* setup interrupt bank table */
+    interrupt_bank0[1]  = 0;
+    interrupt_bank0[2]  = 1;
+    interrupt_bank0[4]  = 2;
+    interrupt_bank0[8]  = 3;
+    interrupt_bank0[16] = 4;
+    interrupt_bank0[32] = 5;
+    interrupt_bank0[64] = 6;
+    interrupt_bank0[128]= 7;
 
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
+    interrupt_bank1[1]  = 8;
+    interrupt_bank1[2]  = 9;
+    interrupt_bank1[4]  = 10;
+    interrupt_bank1[8]  = 11;
+    interrupt_bank1[16] = 12;
+    interrupt_bank1[32] = 13;
+    interrupt_bank1[64] = 14;
+    interrupt_bank1[128]= 15;
+
+    interrupt_bank2[1]  = 16;
+    interrupt_bank2[2]  = 17;
+    interrupt_bank2[4]  = 18;
+    interrupt_bank2[8]  = 19;
+    interrupt_bank2[16] = 20;
+    interrupt_bank2[32] = 21;
+    interrupt_bank2[64] = 22;
+    interrupt_bank2[128]= 23;
+
+    interrupt_bank3[1]  = 24;
+    interrupt_bank3[2]  = 25;
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
 }
 
 /**
@@ -114,7 +114,7 @@ void rt_hw_interrupt_init()
  */
 void rt_hw_interrupt_mask(int vector)
 {
-	INTMSK |= 1 << vector;
+    INTMSK |= 1 << vector;
 }
 
 /**
@@ -123,7 +123,7 @@ void rt_hw_interrupt_mask(int vector)
  */
 void rt_hw_interrupt_umask(int vector)
 {
-	INTMSK &= ~(1 << vector);
+    INTMSK &= ~(1 << vector);
 }
 
 /**
@@ -134,11 +134,11 @@ void rt_hw_interrupt_umask(int vector)
  */
 void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler)
 {
-	if(vector < MAX_HANDLERS)
-	{
-		if (old_handler != RT_NULL) *old_handler = isr_table[vector];
-		if (new_handler != RT_NULL) isr_table[vector] = new_handler;
-	}
+    if(vector < MAX_HANDLERS)
+    {
+        if (old_handler != RT_NULL) *old_handler = isr_table[vector];
+        if (new_handler != RT_NULL) isr_table[vector] = new_handler;
+    }
 }
 
 /*@}*/
diff --git a/libcpu/arm/s3c44b0/s3c44b0.h b/libcpu/arm/s3c44b0/s3c44b0.h
index 7b854b718a..a40946b573 100644
--- a/libcpu/arm/s3c44b0/s3c44b0.h
+++ b/libcpu/arm/s3c44b0/s3c44b0.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,315 +22,315 @@ extern "C" {
 /*@{*/
 
 /*------------------------------------------------------------------------
- *	  ASIC Address Definition
+ *    ASIC Address Definition
  *----------------------------------------------------------------------*/
-#define S3C_REG		*(volatile unsigned int *)
-#define S3C_REGW	*(volatile unsigned short *)
-#define S3C_REGB	*(volatile unsigned char *)
+#define S3C_REG     *(volatile unsigned int *)
+#define S3C_REGW    *(volatile unsigned short *)
+#define S3C_REGB    *(volatile unsigned char *)
 
 /* System */
-#define SYSCFG		(S3C_REG(0x1c00000))
+#define SYSCFG      (S3C_REG(0x1c00000))
 
 /* Cache */
-#define NCACHBE0	(S3C_REG(0x1c00004))
-#define NCACHBE1	(S3C_REG(0x1c00008))
+#define NCACHBE0    (S3C_REG(0x1c00004))
+#define NCACHBE1    (S3C_REG(0x1c00008))
 
 /* Bus control */
-#define SBUSCON		(S3C_REG(0x1c40000))
+#define SBUSCON     (S3C_REG(0x1c40000))
 
 /* Memory control */
-#define BWSCON		(S3C_REG(0x1c80000))
-#define BANKCON0	(S3C_REG(0x1c80004))
-#define BANKCON1	(S3C_REG(0x1c80008))
-#define BANKCON2	(S3C_REG(0x1c8000c))
-#define BANKCON3	(S3C_REG(0x1c80010))
-#define BANKCON4	(S3C_REG(0x1c80014))
-#define BANKCON5	(S3C_REG(0x1c80018))
-#define BANKCON6	(S3C_REG(0x1c8001c))
-#define BANKCON7	(S3C_REG(0x1c80020))
-#define REFRESH		(S3C_REG(0x1c80024))
-#define BANKSIZE	(S3C_REG(0x1c80028))
-#define MRSRB6		(S3C_REG(0x1c8002c))
-#define MRSRB7		(S3C_REG(0x1c80030))
+#define BWSCON      (S3C_REG(0x1c80000))
+#define BANKCON0    (S3C_REG(0x1c80004))
+#define BANKCON1    (S3C_REG(0x1c80008))
+#define BANKCON2    (S3C_REG(0x1c8000c))
+#define BANKCON3    (S3C_REG(0x1c80010))
+#define BANKCON4    (S3C_REG(0x1c80014))
+#define BANKCON5    (S3C_REG(0x1c80018))
+#define BANKCON6    (S3C_REG(0x1c8001c))
+#define BANKCON7    (S3C_REG(0x1c80020))
+#define REFRESH     (S3C_REG(0x1c80024))
+#define BANKSIZE    (S3C_REG(0x1c80028))
+#define MRSRB6      (S3C_REG(0x1c8002c))
+#define MRSRB7      (S3C_REG(0x1c80030))
 
 /* UART */
-#define ULCON0		(S3C_REG(0x1d00000))
-#define ULCON1		(S3C_REG(0x1d04000))
-#define UCON0		(S3C_REG(0x1d00004))
-#define UCON1		(S3C_REG(0x1d04004))
-#define UFCON0		(S3C_REG(0x1d00008))
-#define UFCON1		(S3C_REG(0x1d04008))
-#define UMCON0		(S3C_REG(0x1d0000c))
-#define UMCON1		(S3C_REG(0x1d0400c))
-#define UTRSTAT0	(S3C_REG(0x1d00010))
-#define UTRSTAT1	(S3C_REG(0x1d04010))
-#define UERSTAT0	(S3C_REG(0x1d00014))
-#define UERSTAT1	(S3C_REG(0x1d04014))
-#define UFSTAT0		(S3C_REG(0x1d00018))
-#define UFSTAT1		(S3C_REG(0x1d04018))
-#define UMSTAT0		(S3C_REG(0x1d0001c))
-#define UMSTAT1		(S3C_REG(0x1d0401c))
-#define UBRDIV0		(S3C_REG(0x1d00028))
-#define UBRDIV1		(S3C_REG(0x1d04028))
+#define ULCON0      (S3C_REG(0x1d00000))
+#define ULCON1      (S3C_REG(0x1d04000))
+#define UCON0       (S3C_REG(0x1d00004))
+#define UCON1       (S3C_REG(0x1d04004))
+#define UFCON0      (S3C_REG(0x1d00008))
+#define UFCON1      (S3C_REG(0x1d04008))
+#define UMCON0      (S3C_REG(0x1d0000c))
+#define UMCON1      (S3C_REG(0x1d0400c))
+#define UTRSTAT0    (S3C_REG(0x1d00010))
+#define UTRSTAT1    (S3C_REG(0x1d04010))
+#define UERSTAT0    (S3C_REG(0x1d00014))
+#define UERSTAT1    (S3C_REG(0x1d04014))
+#define UFSTAT0     (S3C_REG(0x1d00018))
+#define UFSTAT1     (S3C_REG(0x1d04018))
+#define UMSTAT0     (S3C_REG(0x1d0001c))
+#define UMSTAT1     (S3C_REG(0x1d0401c))
+#define UBRDIV0     (S3C_REG(0x1d00028))
+#define UBRDIV1     (S3C_REG(0x1d04028))
 
-#define UTXH0		(S3C_REGB(0x1d00020))
-#define UTXH1		(S3C_REGB(0x1d04020))
-#define URXH0		(S3C_REGB(0x1d00024))
-#define URXH1		(S3C_REGB(0x1d04024))
+#define UTXH0       (S3C_REGB(0x1d00020))
+#define UTXH1       (S3C_REGB(0x1d04020))
+#define URXH0       (S3C_REGB(0x1d00024))
+#define URXH1       (S3C_REGB(0x1d04024))
 
 /* SIO */
-#define SIOCON		(S3C_REG(0x1d14000))
-#define SIODAT		(S3C_REG(0x1d14004))
-#define SBRDR		(S3C_REG(0x1d14008))
-#define IVTCNT		(S3C_REG(0x1d1400c))
-#define DCNTZ		(S3C_REG(0x1d14010))
+#define SIOCON      (S3C_REG(0x1d14000))
+#define SIODAT      (S3C_REG(0x1d14004))
+#define SBRDR       (S3C_REG(0x1d14008))
+#define IVTCNT      (S3C_REG(0x1d1400c))
+#define DCNTZ       (S3C_REG(0x1d14010))
 
 /* IIS */
-#define IISCON		(S3C_REG(0x1d18000))
-#define IISMOD		(S3C_REG(0x1d18004))
-#define IISPSR		(S3C_REG(0x1d18008))
-#define IISFCON		(S3C_REG(0x1d1800c))
+#define IISCON      (S3C_REG(0x1d18000))
+#define IISMOD      (S3C_REG(0x1d18004))
+#define IISPSR      (S3C_REG(0x1d18008))
+#define IISFCON     (S3C_REG(0x1d1800c))
 
-#define IISFIF		(S3C_REQW(0x1d18010))
+#define IISFIF      (S3C_REQW(0x1d18010))
 
 /* I/O Port */
-#define PCONA		(S3C_REG(0x1d20000))
-#define PDATA		(S3C_REG(0x1d20004))
+#define PCONA       (S3C_REG(0x1d20000))
+#define PDATA       (S3C_REG(0x1d20004))
 
-#define PCONB		(S3C_REG(0x1d20008))
-#define PDATB		(S3C_REG(0x1d2000c))
+#define PCONB       (S3C_REG(0x1d20008))
+#define PDATB       (S3C_REG(0x1d2000c))
 
-#define PCONC		(S3C_REG(0x1d20010))
-#define PDATC		(S3C_REG(0x1d20014))
-#define PUPC		(S3C_REG(0x1d20018))
+#define PCONC       (S3C_REG(0x1d20010))
+#define PDATC       (S3C_REG(0x1d20014))
+#define PUPC        (S3C_REG(0x1d20018))
 
-#define PCOND		(S3C_REG(0x1d2001c))
-#define PDATD		(S3C_REG(0x1d20020))
-#define PUPD		(S3C_REG(0x1d20024))
+#define PCOND       (S3C_REG(0x1d2001c))
+#define PDATD       (S3C_REG(0x1d20020))
+#define PUPD        (S3C_REG(0x1d20024))
 
-#define PCONE		(S3C_REG(0x1d20028))
-#define PDATE		(S3C_REG(0x1d2002c))
-#define PUPE		(S3C_REG(0x1d20030))
+#define PCONE       (S3C_REG(0x1d20028))
+#define PDATE       (S3C_REG(0x1d2002c))
+#define PUPE        (S3C_REG(0x1d20030))
 
-#define PCONF		(S3C_REG(0x1d20034))
-#define PDATF		(S3C_REG(0x1d20038))
-#define PUPF		(S3C_REG(0x1d2003c))
+#define PCONF       (S3C_REG(0x1d20034))
+#define PDATF       (S3C_REG(0x1d20038))
+#define PUPF        (S3C_REG(0x1d2003c))
 
-#define PCONG		(S3C_REG(0x1d20040))
-#define PDATG		(S3C_REG(0x1d20044))
-#define PUPG		(S3C_REG(0x1d20048))
+#define PCONG       (S3C_REG(0x1d20040))
+#define PDATG       (S3C_REG(0x1d20044))
+#define PUPG        (S3C_REG(0x1d20048))
 
-#define SPUCR		(S3C_REG(0x1d2004c))
-#define EXTINT		(S3C_REG(0x1d20050))
-#define EXTINTPND	(S3C_REG(0x1d20054))
+#define SPUCR       (S3C_REG(0x1d2004c))
+#define EXTINT      (S3C_REG(0x1d20050))
+#define EXTINTPND   (S3C_REG(0x1d20054))
 
 /* Watchdog */
-#define WTCON		(S3C_REG(0x1d30000))
-#define WTDAT		(S3C_REG(0x1d30004))
-#define WTCNT		(S3C_REG(0x1d30008))
+#define WTCON       (S3C_REG(0x1d30000))
+#define WTDAT       (S3C_REG(0x1d30004))
+#define WTCNT       (S3C_REG(0x1d30008))
 
 /* ADC */
-#define ADCCON		(S3C_REG(0x1d40000))
-#define ADCPSR		(S3C_REG(0x1d40004))
-#define ADCDAT		(S3C_REG(0x1d40008))
+#define ADCCON      (S3C_REG(0x1d40000))
+#define ADCPSR      (S3C_REG(0x1d40004))
+#define ADCDAT      (S3C_REG(0x1d40008))
 
 /* Timer */
-#define TCFG0		(S3C_REG(0x1d50000))
-#define TCFG1		(S3C_REG(0x1d50004))
-#define TCON		(S3C_REG(0x1d50008))
+#define TCFG0       (S3C_REG(0x1d50000))
+#define TCFG1       (S3C_REG(0x1d50004))
+#define TCON        (S3C_REG(0x1d50008))
 
-#define TCNTB0		(S3C_REG(0x1d5000c))
-#define TCMPB0		(S3C_REG(0x1d50010))
-#define TCNTO0		(S3C_REG(0x1d50014))
+#define TCNTB0      (S3C_REG(0x1d5000c))
+#define TCMPB0      (S3C_REG(0x1d50010))
+#define TCNTO0      (S3C_REG(0x1d50014))
 
-#define TCNTB1		(S3C_REG(0x1d50018))
-#define TCMPB1		(S3C_REG(0x1d5001c))
-#define TCNTO1		(S3C_REG(0x1d50020))
+#define TCNTB1      (S3C_REG(0x1d50018))
+#define TCMPB1      (S3C_REG(0x1d5001c))
+#define TCNTO1      (S3C_REG(0x1d50020))
 
-#define TCNTB2		(S3C_REG(0x1d50024))
-#define TCMPB2		(S3C_REG(0x1d50028))
-#define TCNTO2		(S3C_REG(0x1d5002c))
+#define TCNTB2      (S3C_REG(0x1d50024))
+#define TCMPB2      (S3C_REG(0x1d50028))
+#define TCNTO2      (S3C_REG(0x1d5002c))
 
-#define TCNTB3		(S3C_REG(0x1d50030))
-#define TCMPB3		(S3C_REG(0x1d50034))
-#define TCNTO3		(S3C_REG(0x1d50038))
+#define TCNTB3      (S3C_REG(0x1d50030))
+#define TCMPB3      (S3C_REG(0x1d50034))
+#define TCNTO3      (S3C_REG(0x1d50038))
 
-#define TCNTB4		(S3C_REG(0x1d5003c))
-#define TCMPB4		(S3C_REG(0x1d50040))
-#define TCNTO4		(S3C_REG(0x1d50044))
+#define TCNTB4      (S3C_REG(0x1d5003c))
+#define TCMPB4      (S3C_REG(0x1d50040))
+#define TCNTO4      (S3C_REG(0x1d50044))
 
-#define TCNTB5		(S3C_REG(0x1d50048))
-#define TCNTO5		(S3C_REG(0x1d5004c))
+#define TCNTB5      (S3C_REG(0x1d50048))
+#define TCNTO5      (S3C_REG(0x1d5004c))
 
 /* IIC */
-#define IICCON		(S3C_REG(0x1d60000))
-#define IICSTAT    	(S3C_REG(0x1d60004))
-#define IICADD     	(S3C_REG(0x1d60008))
-#define IICDS		(S3C_REG(0x1d6000c))
+#define IICCON      (S3C_REG(0x1d60000))
+#define IICSTAT     (S3C_REG(0x1d60004))
+#define IICADD      (S3C_REG(0x1d60008))
+#define IICDS       (S3C_REG(0x1d6000c))
 
 /* RTC */
-#define RTCCON		(S3C_REGB(0x1d70040)
-#define RTCALM		(S3C_REGB(0x1d70050)
-#define ALMSEC		(S3C_REGB(0x1d70054)
-#define ALMMIN		(S3C_REGB(0x1d70058)
-#define ALMHOUR		(S3C_REGB(0x1d7005c)
-#define ALMDAY		(S3C_REGB(0x1d70060)
-#define ALMMON		(S3C_REGB(0x1d70064)
-#define ALMYEAR		(S3C_REGB(0x1d70068)
-#define RTCRST		(S3C_REGB(0x1d7006c)
-#define BCDSEC		(S3C_REGB(0x1d70070)
-#define BCDMIN		(S3C_REGB(0x1d70074)
-#define BCDHOUR		(S3C_REGB(0x1d70078)
-#define BCDDAY		(S3C_REGB(0x1d7007c)
-#define BCDDATE		(S3C_REGB(0x1d70080)
-#define BCDMON		(S3C_REGB(0x1d70084)
-#define BCDYEAR		(S3C_REGB(0x1d70088)
-#define TICINT		(S3C_REGB(0x1d7008c)
+#define RTCCON      (S3C_REGB(0x1d70040)
+#define RTCALM      (S3C_REGB(0x1d70050)
+#define ALMSEC      (S3C_REGB(0x1d70054)
+#define ALMMIN      (S3C_REGB(0x1d70058)
+#define ALMHOUR     (S3C_REGB(0x1d7005c)
+#define ALMDAY      (S3C_REGB(0x1d70060)
+#define ALMMON      (S3C_REGB(0x1d70064)
+#define ALMYEAR     (S3C_REGB(0x1d70068)
+#define RTCRST      (S3C_REGB(0x1d7006c)
+#define BCDSEC      (S3C_REGB(0x1d70070)
+#define BCDMIN      (S3C_REGB(0x1d70074)
+#define BCDHOUR     (S3C_REGB(0x1d70078)
+#define BCDDAY      (S3C_REGB(0x1d7007c)
+#define BCDDATE     (S3C_REGB(0x1d70080)
+#define BCDMON      (S3C_REGB(0x1d70084)
+#define BCDYEAR     (S3C_REGB(0x1d70088)
+#define TICINT      (S3C_REGB(0x1d7008c)
 
 /* Clock & Power management */
-#define PLLCON		(S3C_REG(0x1d80000))
-#define CLKCON		(S3C_REG(0x1d80004))
-#define CLKSLOW		(S3C_REG(0x1d80008))
-#define LOCKTIME	(S3C_REG(0x1d8000c))
+#define PLLCON      (S3C_REG(0x1d80000))
+#define CLKCON      (S3C_REG(0x1d80004))
+#define CLKSLOW     (S3C_REG(0x1d80008))
+#define LOCKTIME    (S3C_REG(0x1d8000c))
 
 /* Interrupt */
-#define INTCON		(S3C_REG(0x1e00000))
-#define INTPND		(S3C_REG(0x1e00004))
-#define INTMOD		(S3C_REG(0x1e00008))
-#define INTMSK		(S3C_REG(0x1e0000c))
+#define INTCON      (S3C_REG(0x1e00000))
+#define INTPND      (S3C_REG(0x1e00004))
+#define INTMOD      (S3C_REG(0x1e00008))
+#define INTMSK      (S3C_REG(0x1e0000c))
 
-#define I_PSLV		(S3C_REG(0x1e00010))
-#define I_PMST		(S3C_REG(0x1e00014))
-#define I_CSLV		(S3C_REG(0x1e00018))
-#define I_CMST		(S3C_REG(0x1e0001c))
-#define I_ISPR		(S3C_REG(0x1e00020))
-#define I_ISPC		(S3C_REG(0x1e00024))
+#define I_PSLV      (S3C_REG(0x1e00010))
+#define I_PMST      (S3C_REG(0x1e00014))
+#define I_CSLV      (S3C_REG(0x1e00018))
+#define I_CMST      (S3C_REG(0x1e0001c))
+#define I_ISPR      (S3C_REG(0x1e00020))
+#define I_ISPC      (S3C_REG(0x1e00024))
 
-#define F_ISPR		(S3C_REG(0x1e00038))
-#define F_ISPC		(S3C_REG(0x1e0003c))
+#define F_ISPR      (S3C_REG(0x1e00038))
+#define F_ISPC      (S3C_REG(0x1e0003c))
 
 /********************************/
 /* LCD Controller Registers     */
 /********************************/
-#define LCDCON1		(S3C_REG(0x300000))
-#define LCDCON2		(S3C_REG(0x300004))
-#define LCDSADDR1	(S3C_REG(0x300008))
-#define LCDSADDR2	(S3C_REG(0x30000c))
-#define LCDSADDR3	(S3C_REG(0x300010))
-#define REDLUT		(S3C_REG(0x300014))
-#define GREENLUT	(S3C_REG(0x300018))
-#define BLUELUT		(S3C_REG(0x30001c))
-#define DP1_2		(S3C_REG(0x300020))
-#define DP4_7		(S3C_REG(0x300024))
-#define DP3_5		(S3C_REG(0x300028))
-#define DP2_3		(S3C_REG(0x30002c))
-#define DP5_7		(S3C_REG(0x300030))
-#define DP3_4		(S3C_REG(0x300034))
-#define DP4_5		(S3C_REG(0x300038))
-#define DP6_7		(S3C_REG(0x30003c))
-#define LCDCON3		(S3C_REG(0x300040))
-#define DITHMODE	(S3C_REG(0x300044))
+#define LCDCON1     (S3C_REG(0x300000))
+#define LCDCON2     (S3C_REG(0x300004))
+#define LCDSADDR1   (S3C_REG(0x300008))
+#define LCDSADDR2   (S3C_REG(0x30000c))
+#define LCDSADDR3   (S3C_REG(0x300010))
+#define REDLUT      (S3C_REG(0x300014))
+#define GREENLUT    (S3C_REG(0x300018))
+#define BLUELUT     (S3C_REG(0x30001c))
+#define DP1_2       (S3C_REG(0x300020))
+#define DP4_7       (S3C_REG(0x300024))
+#define DP3_5       (S3C_REG(0x300028))
+#define DP2_3       (S3C_REG(0x30002c))
+#define DP5_7       (S3C_REG(0x300030))
+#define DP3_4       (S3C_REG(0x300034))
+#define DP4_5       (S3C_REG(0x300038))
+#define DP6_7       (S3C_REG(0x30003c))
+#define LCDCON3     (S3C_REG(0x300040))
+#define DITHMODE    (S3C_REG(0x300044))
 
 /* ZDMA0 */
-#define ZDCON0		(S3C_REG(0x1e80000))
-#define ZDISRC0		(S3C_REG(0x1e80004))
-#define ZDIDES0		(S3C_REG(0x1e80008))
-#define ZDICNT0		(S3C_REG(0x1e8000c))
-#define ZDCSRC0		(S3C_REG(0x1e80010))
-#define ZDCDES0		(S3C_REG(0x1e80014))
-#define ZDCCNT0		(S3C_REG(0x1e80018))
+#define ZDCON0      (S3C_REG(0x1e80000))
+#define ZDISRC0     (S3C_REG(0x1e80004))
+#define ZDIDES0     (S3C_REG(0x1e80008))
+#define ZDICNT0     (S3C_REG(0x1e8000c))
+#define ZDCSRC0     (S3C_REG(0x1e80010))
+#define ZDCDES0     (S3C_REG(0x1e80014))
+#define ZDCCNT0     (S3C_REG(0x1e80018))
 
 /* ZDMA1 */
-#define ZDCON1		(S3C_REG(0x1e80020))
-#define ZDISRC1		(S3C_REG(0x1e80024))
-#define ZDIDES1		(S3C_REG(0x1e80028))
-#define ZDICNT1		(S3C_REG(0x1e8002c))
-#define ZDCSRC1		(S3C_REG(0x1e80030))
-#define ZDCDES1		(S3C_REG(0x1e80034))
-#define ZDCCNT1		(S3C_REG(0x1e80038))
+#define ZDCON1      (S3C_REG(0x1e80020))
+#define ZDISRC1     (S3C_REG(0x1e80024))
+#define ZDIDES1     (S3C_REG(0x1e80028))
+#define ZDICNT1     (S3C_REG(0x1e8002c))
+#define ZDCSRC1     (S3C_REG(0x1e80030))
+#define ZDCDES1     (S3C_REG(0x1e80034))
+#define ZDCCNT1     (S3C_REG(0x1e80038))
 
 /* BDMA0 */
-#define BDCON0		(S3C_REG(0x1f80000))
-#define BDISRC0		(S3C_REG(0x1f80004))
-#define BDIDES0		(S3C_REG(0x1f80008))
-#define BDICNT0		(S3C_REG(0x1f8000c))
-#define BDCSRC0		(S3C_REG(0x1f80010))
-#define BDCDES0		(S3C_REG(0x1f80014))
-#define BDCCNT0		(S3C_REG(0x1f80018))
+#define BDCON0      (S3C_REG(0x1f80000))
+#define BDISRC0     (S3C_REG(0x1f80004))
+#define BDIDES0     (S3C_REG(0x1f80008))
+#define BDICNT0     (S3C_REG(0x1f8000c))
+#define BDCSRC0     (S3C_REG(0x1f80010))
+#define BDCDES0     (S3C_REG(0x1f80014))
+#define BDCCNT0     (S3C_REG(0x1f80018))
 
 /* BDMA1 */
-#define BDCON1		(S3C_REG(0x1f80020))
-#define BDISRC1		(S3C_REG(0x1f80024))
-#define BDIDES1		(S3C_REG(0x1f80028))
-#define BDICNT1		(S3C_REG(0x1f8002c))
-#define BDCSRC1		(S3C_REG(0x1f80030))
-#define BDCDES1		(S3C_REG(0x1f80034))
-#define BDCCNT1		(S3C_REG(0x1f80038))
+#define BDCON1      (S3C_REG(0x1f80020))
+#define BDISRC1     (S3C_REG(0x1f80024))
+#define BDIDES1     (S3C_REG(0x1f80028))
+#define BDICNT1     (S3C_REG(0x1f8002c))
+#define BDCSRC1     (S3C_REG(0x1f80030))
+#define BDCDES1     (S3C_REG(0x1f80034))
+#define BDCCNT1     (S3C_REG(0x1f80038))
 
 /*****************************/
 /* CPU Mode                  */
 /*****************************/
-#define USERMODE	0x10		/* User Mode(USR) */
-#define FIQMODE		0x11		/* Fast Interrupt Mode (FIQ) */
-#define IRQMODE		0x12		/* Interrupt Mode (IRQ) */
-#define SVCMODE		0x13		/* Supervisor Mode (SVC) */
-#define ABORTMODE	0x17		/* Abort Mode(ABT) */
-#define UNDEFMODE	0x1b		/* Undefine Mode(UDF) */
-#define MODEMASK	0x1f		/* Processor Mode Mask */
-#define NOINT		0xc0
+#define USERMODE    0x10        /* User Mode(USR) */
+#define FIQMODE     0x11        /* Fast Interrupt Mode (FIQ) */
+#define IRQMODE     0x12        /* Interrupt Mode (IRQ) */
+#define SVCMODE     0x13        /* Supervisor Mode (SVC) */
+#define ABORTMODE   0x17        /* Abort Mode(ABT) */
+#define UNDEFMODE   0x1b        /* Undefine Mode(UDF) */
+#define MODEMASK    0x1f        /* Processor Mode Mask */
+#define NOINT       0xc0
 
 /*****************************/
 /* INT Define                */
 /*****************************/
-#define INT_ADC		0x00
-#define INT_RTC		0x01
-#define INT_UTXD1	0x02
-#define INT_UTXD0	0x03
-#define INT_SIO		0x04
-#define INT_IIC		0x05
-#define INT_URXD1	0x06
-#define INT_URXD0	0x07
-#define INT_TIMER5	0x08
-#define INT_TIMER4	0x09
-#define INT_TIMER3	0x0A
-#define INT_TIMER2	0x0B
-#define INT_TIMER1	0x0C
-#define INT_TIMER0	0x0D
-#define INT_UERR01	0x0E
-#define INT_WDT		0x1F
-#define INT_BDMA1	0x10
-#define INT_BDMA0	0x11
-#define INT_ZDMA1	0x12
-#define INT_ZDMA0	0x13
-#define INT_TICK	0x14
-#define INT_EINT4567	0x15
-#define INT_EINT3	0x16
-#define INT_EINT2	0x17
-#define INT_EINT1	0x18
-#define INT_EINT0	0x19
+#define INT_ADC     0x00
+#define INT_RTC     0x01
+#define INT_UTXD1   0x02
+#define INT_UTXD0   0x03
+#define INT_SIO     0x04
+#define INT_IIC     0x05
+#define INT_URXD1   0x06
+#define INT_URXD0   0x07
+#define INT_TIMER5  0x08
+#define INT_TIMER4  0x09
+#define INT_TIMER3  0x0A
+#define INT_TIMER2  0x0B
+#define INT_TIMER1  0x0C
+#define INT_TIMER0  0x0D
+#define INT_UERR01  0x0E
+#define INT_WDT     0x1F
+#define INT_BDMA1   0x10
+#define INT_BDMA0   0x11
+#define INT_ZDMA1   0x12
+#define INT_ZDMA0   0x13
+#define INT_TICK    0x14
+#define INT_EINT4567    0x15
+#define INT_EINT3   0x16
+#define INT_EINT2   0x17
+#define INT_EINT1   0x18
+#define INT_EINT0   0x19
 
-#define INT_GLOBAL	26
+#define INT_GLOBAL  26
 
 struct rt_hw_register
 {
-	unsigned long r0;
-	unsigned long r1;
-	unsigned long r2;
-	unsigned long r3;
-	unsigned long r4;
-	unsigned long r5;
-	unsigned long r6;
-	unsigned long r7;
-	unsigned long r8;
-	unsigned long r9;
-	unsigned long r10;
-	unsigned long fp;
-	unsigned long ip;
-	unsigned long sp;
-	unsigned long lr;
-	unsigned long pc;
-	unsigned long cpsr;
-	unsigned long ORIG_r0;
+    unsigned long r0;
+    unsigned long r1;
+    unsigned long r2;
+    unsigned long r3;
+    unsigned long r4;
+    unsigned long r5;
+    unsigned long r6;
+    unsigned long r7;
+    unsigned long r8;
+    unsigned long r9;
+    unsigned long r10;
+    unsigned long fp;
+    unsigned long ip;
+    unsigned long sp;
+    unsigned long lr;
+    unsigned long pc;
+    unsigned long cpsr;
+    unsigned long ORIG_r0;
 };
 
 /*@}*/
diff --git a/libcpu/arm/s3c44b0/serial.c b/libcpu/arm/s3c44b0/serial.c
index 6af515b027..95f8cb3487 100644
--- a/libcpu/arm/s3c44b0/serial.c
+++ b/libcpu/arm/s3c44b0/serial.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -18,21 +18,21 @@ void rt_serial_init(void);
 void rt_console_puts(const char* str);
 void rt_serial_putc(const char c);
 
-#define	USTAT_RCV_READY		0x01	/* receive data ready */
-#define	USTAT_TXB_EMPTY		0x02	/* tx buffer empty */
+#define USTAT_RCV_READY     0x01    /* receive data ready */
+#define USTAT_TXB_EMPTY     0x02    /* tx buffer empty */
 
 rt_inline void serial_flush_input(void)
 {
-	volatile unsigned int tmp;
+    volatile unsigned int tmp;
 
-	/* keep on reading as long as the receiver is not empty */
-	while(UTRSTAT0 & USTAT_RCV_READY) tmp = URXH0;
+    /* keep on reading as long as the receiver is not empty */
+    while(UTRSTAT0 & USTAT_RCV_READY) tmp = URXH0;
 }
 
 rt_inline void serial_flush_output(void)
 {
-	/* wait until the transmitter is no longer busy */
-	while(!(UTRSTAT0 & USTAT_TXB_EMPTY)) ;
+    /* wait until the transmitter is no longer busy */
+    while(!(UTRSTAT0 & USTAT_TXB_EMPTY)) ;
 }
 
 /**
@@ -48,10 +48,10 @@ rt_inline void serial_flush_output(void)
  */
 void rt_console_puts(const char* str)
 {
-	while (*str)
-	{
-		rt_serial_putc (*str++);
-	}
+    while (*str)
+    {
+        rt_serial_putc (*str++);
+    }
 }
 
 /**
@@ -59,25 +59,25 @@ void rt_console_puts(const char* str)
  */
 void rt_serial_init()
 {
-	rt_uint32_t divisor = 0;
+    rt_uint32_t divisor = 0;
 
-	divisor = 0x20;
+    divisor = 0x20;
 
-	serial_flush_output();
-	serial_flush_input();
+    serial_flush_output();
+    serial_flush_input();
 
-	/* UART interrupt off */
-	UCON0 	= 0;
-	/* FIFO disable */
-	UFCON0	=0x0;
-	UMCON0	=0x0;
-	/* set baudrate */
- 	UBRDIV0 = divisor;
+    /* UART interrupt off */
+    UCON0   = 0;
+    /* FIFO disable */
+    UFCON0  =0x0;
+    UMCON0  =0x0;
+    /* set baudrate */
+    UBRDIV0 = divisor;
 
-	/* word length=8bit, stop bit = 1, no parity, use external clock */
-	ULCON0 	= 0x03|0x00|0x00;
+    /* word length=8bit, stop bit = 1, no parity, use external clock */
+    ULCON0  = 0x03|0x00|0x00;
 
- 	UCON0 	= 0x5;
+    UCON0   = 0x5;
 }
 
 /**
@@ -87,9 +87,9 @@ void rt_serial_init()
  */
 char rt_serial_getc()
 {
-	while ((UTRSTAT0 & USTAT_RCV_READY) == 0);
+    while ((UTRSTAT0 & USTAT_RCV_READY) == 0);
 
-	return URXH0;
+    return URXH0;
 }
 
 /**
@@ -99,16 +99,16 @@ char rt_serial_getc()
  */
 void rt_serial_putc(const char c)
 {
-	/*
-		to be polite with serial console add a line feed
-		to the carriage return character
-	*/
-	if (c=='\n')rt_serial_putc('\r');
+    /*
+        to be polite with serial console add a line feed
+        to the carriage return character
+    */
+    if (c=='\n')rt_serial_putc('\r');
 
-	/* wait for room in the transmit FIFO */
-	while(!(UTRSTAT0 & USTAT_TXB_EMPTY));
+    /* wait for room in the transmit FIFO */
+    while(!(UTRSTAT0 & USTAT_TXB_EMPTY));
 
-	UTXH0 = (rt_uint8_t)c;
+    UTXH0 = (rt_uint8_t)c;
 }
 
 /*@}*/
diff --git a/libcpu/arm/s3c44b0/stack.c b/libcpu/arm/s3c44b0/stack.c
index 12da611d5a..4ed4693994 100644
--- a/libcpu/arm/s3c44b0/stack.c
+++ b/libcpu/arm/s3c44b0/stack.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/libcpu/arm/s3c44b0/trap.c b/libcpu/arm/s3c44b0/trap.c
index 3b93d5457e..106a990262 100644
--- a/libcpu/arm/s3c44b0/trap.c
+++ b/libcpu/arm/s3c44b0/trap.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -33,13 +33,13 @@ extern struct rt_thread *rt_current_thread;
  */
 void rt_hw_show_register (struct rt_hw_register *regs)
 {
-	rt_kprintf("Execption:\n");
-	rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
-	rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
-	rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
-	rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
-	rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
-	rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
 }
 
 /**
@@ -52,10 +52,10 @@ void rt_hw_show_register (struct rt_hw_register *regs)
  */
 void rt_hw_trap_udef(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("undefined instruction\n");
-	rt_hw_cpu_shutdown();
+    rt_kprintf("undefined instruction\n");
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -84,10 +84,10 @@ void rt_hw_trap_swi(struct rt_hw_register *regs)
  */
 void rt_hw_trap_pabt(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("prefetch abort\n");
-	rt_hw_cpu_shutdown();
+    rt_kprintf("prefetch abort\n");
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -100,10 +100,10 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs)
  */
 void rt_hw_trap_dabt(struct rt_hw_register *regs)
 {
-	rt_hw_show_register(regs);
+    rt_hw_show_register(regs);
 
-	rt_kprintf("data abort\n");
-	rt_hw_cpu_shutdown();
+    rt_kprintf("data abort\n");
+    rt_hw_cpu_shutdown();
 }
 
 /**
@@ -123,50 +123,50 @@ void rt_hw_trap_resv(struct rt_hw_register *regs)
 extern rt_isr_handler_t isr_table[];
 void rt_hw_trap_irq()
 {
-	register unsigned long ispr, intstat;
-	register rt_isr_handler_t isr_func;
+    register unsigned long ispr, intstat;
+    register rt_isr_handler_t isr_func;
 
 #ifdef BSP_INT_DEBUG
-	rt_kprintf("irq coming, ");
+    rt_kprintf("irq coming, ");
 #endif
-	intstat = I_ISPR & 0x7ffffff;
+    intstat = I_ISPR & 0x7ffffff;
 #ifdef BSP_INT_DEBUG
-	rt_kprintf("I_ISPR: %d\n", intstat);
+    rt_kprintf("I_ISPR: %d\n", intstat);
 #endif
 
-	ispr = intstat;
+    ispr = intstat;
 
-	/* to find interrupt */
-	if ( intstat & 0xff ) /* lowest 8bits */
-	{
-		intstat = interrupt_bank0[intstat & 0xff];
-		isr_func = (rt_isr_handler_t)isr_table[ intstat ];
-	}
-	else if ( intstat & 0xff00 ) /* low 8bits */
-	{
-		intstat = interrupt_bank1[(intstat & 0xff00) >> 8];
-		isr_func = (rt_isr_handler_t)isr_table[ intstat ];
-	}
-	else if ( intstat & 0xff0000 ) /* high 8bits */
-	{
-		intstat = interrupt_bank2[(intstat & 0xff0000) >> 16];
-		isr_func = (rt_isr_handler_t)isr_table[ intstat ];
-	}
-	else if ( intstat & 0xff000000 ) /* highest 8bits */
-	{
-		intstat = interrupt_bank3[(intstat & 0xff000000) >> 24];
-		isr_func = (rt_isr_handler_t)isr_table[ intstat ];
-	}
-	else return;
+    /* to find interrupt */
+    if ( intstat & 0xff ) /* lowest 8bits */
+    {
+        intstat = interrupt_bank0[intstat & 0xff];
+        isr_func = (rt_isr_handler_t)isr_table[ intstat ];
+    }
+    else if ( intstat & 0xff00 ) /* low 8bits */
+    {
+        intstat = interrupt_bank1[(intstat & 0xff00) >> 8];
+        isr_func = (rt_isr_handler_t)isr_table[ intstat ];
+    }
+    else if ( intstat & 0xff0000 ) /* high 8bits */
+    {
+        intstat = interrupt_bank2[(intstat & 0xff0000) >> 16];
+        isr_func = (rt_isr_handler_t)isr_table[ intstat ];
+    }
+    else if ( intstat & 0xff000000 ) /* highest 8bits */
+    {
+        intstat = interrupt_bank3[(intstat & 0xff000000) >> 24];
+        isr_func = (rt_isr_handler_t)isr_table[ intstat ];
+    }
+    else return;
 
 #ifdef BSP_INT_DEBUG
-	rt_kprintf("irq: %d happen\n", intstat);
+    rt_kprintf("irq: %d happen\n", intstat);
 #endif
 
-	/* turn to interrupt service routine */
-	isr_func(intstat);
+    /* turn to interrupt service routine */
+    isr_func(intstat);
 
-	I_ISPC = ispr;		/* clear interrupt */
+    I_ISPC = ispr;      /* clear interrupt */
 }
 
 void rt_hw_trap_fiq()