Merge pull request #4737 from mysterywolf/3,1,xformatv3.1.5

[lts 3.1.x] format codes

1 files changed, 51 insertions, 51 deletions

diff --git a/libcpu/arm/sep4020/clk.c b/libcpu/arm/sep4020/clk.c
index da69e25b6d..031d310fcf 100644
--- a/libcpu/arm/sep4020/clk.c
+++ b/libcpu/arm/sep4020/clk.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -11,46 +11,46 @@
 #include <rtthread.h>
 #include "sep4020.h"
 
-#define	CLK_IN	        4000000		/* Fin = 4.00MHz  */
-#define SYSCLK		    72000000	/* system clock we want */
+#define CLK_IN          4000000     /* Fin = 4.00MHz  */
+#define SYSCLK          72000000    /* system clock we want */
 
-#define CLK_ESRAM		0
-#define CLK_LCDC		1
-#define CLK_PWM			2
-#define CLK_DMAC		3
-#define CLK_EMI			4
-#define CLK_MMCSD		5
-#define CLK_SSI			7
-#define CLK_UART0		8
-#define CLK_UART1		9
-#define CLK_UART2		10
-#define CLK_UART3		11
-#define CLK_USB			12
-#define CLK_MAC			13
-#define CLK_SMC			14
-#define CLK_I2C			15
-#define CLK_GPT			16
+#define CLK_ESRAM       0
+#define CLK_LCDC        1
+#define CLK_PWM         2
+#define CLK_DMAC        3
+#define CLK_EMI         4
+#define CLK_MMCSD       5
+#define CLK_SSI         7
+#define CLK_UART0       8
+#define CLK_UART1       9
+#define CLK_UART2       10
+#define CLK_UART3       11
+#define CLK_USB         12
+#define CLK_MAC         13
+#define CLK_SMC         14
+#define CLK_I2C         15
+#define CLK_GPT         16
 
 static void rt_hw_set_system_clock(void)
 {
-	rt_uint8_t pv;
+    rt_uint8_t pv;
 
-	/* pv value*/
-	pv  = SYSCLK/2/CLK_IN;
-	/* go to normal mode*/
-	*(RP)PMU_PMDR = 0x01;
-	/* set the clock */
-	*(RP)PMU_PMCR = 0x4000 | pv;
-	/* trige configurate*/
-	*(RP)PMU_PMCR = 0xc000 | pv;
+    /* pv value*/
+    pv  = SYSCLK/2/CLK_IN;
+    /* go to normal mode*/
+    *(RP)PMU_PMDR = 0x01;
+    /* set the clock */
+    *(RP)PMU_PMCR = 0x4000 | pv;
+    /* trige configurate*/
+    *(RP)PMU_PMCR = 0xc000 | pv;
 }
 
 static void rt_hw_set_usb_clock(void)
 {
-	/* set the clock */
-	*(RP)PMU_PUCR = 0x000c;
-	/* trige configurate*/
-	*(RP)PMU_PMCR = 0x800c;
+    /* set the clock */
+    *(RP)PMU_PUCR = 0x000c;
+    /* trige configurate*/
+    *(RP)PMU_PMCR = 0x800c;
 
 }
 
@@ -59,10 +59,10 @@ static void rt_hw_set_usb_clock(void)
  */
 void rt_hw_clock_init(void)
 {
-	/* set system clock */
-	rt_hw_set_system_clock();
-	/* set usb clock */
-	rt_hw_set_usb_clock();
+    /* set system clock */
+    rt_hw_set_system_clock();
+    /* set usb clock */
+    rt_hw_set_usb_clock();
 }
 
 /**
@@ -70,22 +70,22 @@ void rt_hw_clock_init(void)
  */
 rt_uint32_t rt_hw_get_clock(void)
 {
-	rt_uint32_t val;
-	rt_uint8_t pv, pd, npd;
+    rt_uint32_t val;
+    rt_uint8_t pv, pd, npd;
 
-	/* get PMCR value */
-	val =*(RP) PMU_PMCR;
-	/* get NPD */
-	npd = (val >> 14) & 0x01;
-	/* get PD  */
-	pd  = (val >> 10) & 0x0f;
-	/* get PV  */
-	pv  = val & 0x7f;
-	/* caculate the system clock */
-	if(npd)
-		val = 2 * CLK_IN * pv;
-	else
-		val = CLK_IN * pv / (pd + 1);
+    /* get PMCR value */
+    val =*(RP) PMU_PMCR;
+    /* get NPD */
+    npd = (val >> 14) & 0x01;
+    /* get PD  */
+    pd  = (val >> 10) & 0x0f;
+    /* get PV  */
+    pv  = val & 0x7f;
+    /* caculate the system clock */
+    if(npd)
+        val = 2 * CLK_IN * pv;
+    else
+        val = CLK_IN * pv / (pd + 1);
 
     return(val);
 }