diff options
| author | Bernard Xiong <[email protected]> | 2020-07-28 05:44:20 +0800 |
|---|---|---|
| committer | Bernard Xiong <[email protected]> | 2020-07-28 05:44:20 +0800 |
| commit | 6bf76a375c53c1de3f1a4b1d0f7fc6506833f6dd (patch) | |
| tree | 13147a2fa7afeec29d7ee6d00e2afe7afa3879d8 /libcpu/arm | |
| parent | a0897d684a8e88b76a72b2124d81d20bfdc2429d (diff) | |
| parent | fa599be08cb79b16d9bdb1456e195ac134b0f34f (diff) | |
Merge branch 'master' into gitee_master
Diffstat (limited to 'libcpu/arm')
| -rw-r--r-- | libcpu/arm/cortex-a/gic.c | 3 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m23/context_gcc.S | 2 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m23/context_iar.S | 2 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m23/context_rvds.S | 2 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m3/cpuport.c | 4 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m33/cpuport.c | 4 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m4/cpuport.c | 4 | ||||
| -rw-r--r-- | libcpu/arm/cortex-m7/cpuport.c | 4 | ||||
| -rw-r--r-- | libcpu/arm/zynq7000/gic.c | 5 |
9 files changed, 14 insertions, 16 deletions
diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c index 2a46142b54..2e94b88277 100644 --- a/libcpu/arm/cortex-a/gic.c +++ b/libcpu/arm/cortex-a/gic.c @@ -74,9 +74,8 @@ void arm_gic_ack(rt_uint32_t index, int irq) irq = irq - _gic_table[index].offset; RT_ASSERT(irq >= 0); - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; } void arm_gic_mask(rt_uint32_t index, int irq) diff --git a/libcpu/arm/cortex-m23/context_gcc.S b/libcpu/arm/cortex-m23/context_gcc.S index 067348181d..48f90413d9 100644 --- a/libcpu/arm/cortex-m23/context_gcc.S +++ b/libcpu/arm/cortex-m23/context_gcc.S @@ -137,7 +137,7 @@ pendsv_exit: /* restore interrupt */ MSR PRIMASK, R2 - MOVS R0, #0x04 + MOVS R0, #0x03 RSBS R0, R0, #0x00 BX R0 /* diff --git a/libcpu/arm/cortex-m23/context_iar.S b/libcpu/arm/cortex-m23/context_iar.S index 4d50d0fdec..c7d85cc5e2 100644 --- a/libcpu/arm/cortex-m23/context_iar.S +++ b/libcpu/arm/cortex-m23/context_iar.S @@ -139,7 +139,7 @@ pendsv_exit ; restore interrupt MSR PRIMASK, r2 - MOVS r0, #0x04 + MOVS r0, #0x03 RSBS r0, r0, #0x00 BX r0 diff --git a/libcpu/arm/cortex-m23/context_rvds.S b/libcpu/arm/cortex-m23/context_rvds.S index 4486ceaf08..ca381d0f8f 100644 --- a/libcpu/arm/cortex-m23/context_rvds.S +++ b/libcpu/arm/cortex-m23/context_rvds.S @@ -143,7 +143,7 @@ pendsv_exit ; restore interrupt MSR PRIMASK, r2 - MOVS r0, #0x04 + MOVS r0, #0x03 RSBS r0, r0, #0x00 BX r0 ENDP diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c index d17d4fdf2e..d58782e2c5 100644 --- a/libcpu/arm/cortex-m3/cpuport.c +++ b/libcpu/arm/cortex-m3/cpuport.c @@ -388,13 +388,13 @@ int __rt_ffs(int value) { __asm volatile( "CMP r0, #0x00 \n" - "BEQ exit \n" + "BEQ 1f \n" "RBIT r0, r0 \n" "CLZ r0, r0 \n" "ADDS r0, r0, #0x01 \n" - "exit: \n" + "1: \n" : "=r"(value) : "r"(value) diff --git a/libcpu/arm/cortex-m33/cpuport.c b/libcpu/arm/cortex-m33/cpuport.c index 415f560911..a589ba3462 100644 --- a/libcpu/arm/cortex-m33/cpuport.c +++ b/libcpu/arm/cortex-m33/cpuport.c @@ -475,13 +475,13 @@ int __rt_ffs(int value) { __asm volatile( "CMP r0, #0x00 \n" - "BEQ exit \n" + "BEQ 1f \n" "RBIT r0, r0 \n" "CLZ r0, r0 \n" "ADDS r0, r0, #0x01 \n" - "exit: \n" + "1: \n" "BX lr \n" : "=r"(value) diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c index f556ba0c26..dc8a9aab59 100644 --- a/libcpu/arm/cortex-m4/cpuport.c +++ b/libcpu/arm/cortex-m4/cpuport.c @@ -472,13 +472,13 @@ int __rt_ffs(int value) { __asm volatile( "CMP r0, #0x00 \n" - "BEQ exit \n" + "BEQ 1f \n" "RBIT r0, r0 \n" "CLZ r0, r0 \n" "ADDS r0, r0, #0x01 \n" - "exit: \n" + "1: \n" : "=r"(value) : "r"(value) diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c index c22242f140..e701a52307 100644 --- a/libcpu/arm/cortex-m7/cpuport.c +++ b/libcpu/arm/cortex-m7/cpuport.c @@ -472,13 +472,13 @@ int __rt_ffs(int value) { __asm volatile( "CMP r0, #0x00 \n" - "BEQ exit \n" + "BEQ 1f \n" "RBIT r0, r0 \n" "CLZ r0, r0 \n" "ADDS r0, r0, #0x01 \n" - "exit: \n" + "1: \n" : "=r"(value) : "r"(value) diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c index e23a359e6e..76404d4c46 100644 --- a/libcpu/arm/zynq7000/gic.c +++ b/libcpu/arm/zynq7000/gic.c @@ -37,7 +37,7 @@ static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + (n/32) * 4) #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + (n/32) * 4) #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + (n/32) * 4) #define GIC_DIST_ACTIVE_BIT(hw_base) __REG32((hw_base) + 0x300) #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + (n/4) * 4) #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + (n/4) * 4) @@ -68,9 +68,8 @@ void arm_gic_ack(rt_uint32_t index, int irq) irq = irq - _gic_table[index].offset; RT_ASSERT(irq >= 0); - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; + GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; } void arm_gic_mask(rt_uint32_t index, int irq) |
