diff options
| author | Wang-Huachen <[email protected]> | 2021-05-16 10:00:17 +0800 |
|---|---|---|
| committer | Wang-Huachen <[email protected]> | 2021-05-16 10:00:17 +0800 |
| commit | b57278f83021875dee66b6c0c438c82fa34e9539 (patch) | |
| tree | ebc47b06f1b9c1a34b0a986cfc4112a6d9a924c2 /libcpu/arm | |
| parent | 41d55a4d474464090df9c4e19cafb9fd176c9463 (diff) | |
remove redundant code in zynqmp-r5-axu4ev bsp
Diffstat (limited to 'libcpu/arm')
| -rw-r--r-- | libcpu/arm/zynqmp-r5/cache.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/libcpu/arm/zynqmp-r5/cache.c b/libcpu/arm/zynqmp-r5/cache.c index ed0efa4824..6053b2fe47 100644 --- a/libcpu/arm/zynqmp-r5/cache.c +++ b/libcpu/arm/zynqmp-r5/cache.c @@ -108,14 +108,6 @@ void Xil_DCacheInvalidate(void) currmask = mfcpsr(); mtcpsr(currmask | IRQ_FIQ_MASK); -#if 0 - stack_end = (u32 )&_stack_end; - stack_start = (u32 )&__undef_stack; - stack_size = stack_start-stack_end; - - /* Flush stack memory to save return address */ - Xil_DCacheFlushRange(stack_end, stack_size); -#endif mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); /*invalidate all D cache*/ |