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authorGUI <[email protected]>2026-10-17 09:44:26 +0800
committerGitHub <[email protected]>2026-10-17 09:44:26 +0800
commit8d8dc96b67eee53af2841a8819364d52fbec39cb (patch)
treeeb2ac2f0984261f526c5d9c14462db47eceeb193 /libcpu/risc-v/common/SConscript
parentc1d931bcc78915f24c3526a07bdecc64d5110d51 (diff)
[ARCH/RISC-V] Next RISC-V (#10320)
* [libcpu][risc-v] Refactor the RISC-V architecture port Introduce an opt-in unified RISC-V common layer for RV32 and RV64 while keeping existing BSPs on the legacy implementation during migration. - use ARCH_RISCV and ARCH_CPU_64BIT for architecture and XLEN selection - unify context, trap, MMU, cache, timer, SBI, SMP and ISA handling - add PLIC, CLIC, ACLINT, APLIC and IMSIC support - map physical hart IDs to contiguous logical CPU IDs - add T-Head vendor overrides while preserving legacy ports - migrate qemu-virt64-riscv with RV32 and RV64 support - update clock_time, MM, LWP, OFW, PCI and Rust integration Existing BSPs continue using legacy_common or common64 unless they select RT_USING_RISCV_NEW_COMMON. Signed-off-by: GuEe-GUI <[email protected]> * [libcpu][risc-v] skip disabled CPU nodes in early FDT walk Rbb666 noted that rt_hw_fdt_install_early() walked every /cpus child without checking status, so disabled cores still joined hart registration and MMU capability probing. Skip nodes that are not okay/ok via rt_fdt_device_is_available() before reading reg or mmu-type. Signed-off-by: seteiro <[email protected]> * [libcpu][risc-v] Fix per-CPU page table mapping - reuse existing non-leaf page table entries when mapping per-CPU areas - reject leaf entry conflicts instead of overwriting mappings Signed-off-by: GuEe-GUI <[email protected]> --------- Signed-off-by: GuEe-GUI <[email protected]> Signed-off-by: seteiro <[email protected]> Co-authored-by: seteiro <[email protected]>
Diffstat (limited to 'libcpu/risc-v/common/SConscript')
-rw-r--r--libcpu/risc-v/common/SConscript94
1 files changed, 86 insertions, 8 deletions
diff --git a/libcpu/risc-v/common/SConscript b/libcpu/risc-v/common/SConscript
index 814cfb01d5..fe50f4fa96 100644
--- a/libcpu/risc-v/common/SConscript
+++ b/libcpu/risc-v/common/SConscript
@@ -1,15 +1,93 @@
-# RT-Thread building script for component
+# RT-Thread building script for the unified RISC-V CPU port
+import os
from building import *
-cwd = GetCurrentDir()
-src = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
-CPPPATH = [cwd]
-ASFLAGS = ' -I ' + cwd
+Import('rtconfig')
-if not GetDepend('RT_USING_HW_ATOMIC'):
- SrcRemove(src, 'atomic_riscv.c')
+cwd = GetCurrentDir()
+bsp_path = Dir('#').abspath
+CPPPATH = [cwd + '/include', cwd]
-group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+if GetDepend('ARCH_RISCV_VECTOR'):
+ CPPPATH += [os.path.join(cwd, '..', 'vector', 'rvv-1.0')]
+bsp_startup_obj = []
+builtin_fdt_obj = []
+src = [
+ 'backtrace.c',
+ 'cpu.c',
+ 'cpuport.c',
+ 'isa_ext.c',
+ 'riscv_timer.c',
+ 'stack.c',
+ 'trap.c',
+]
+
+if GetDepend('RT_USING_CACHE'):
+ src += ['cache.c']
+
+if rtconfig.PLATFORM in ['gcc']:
+ src += [
+ 'context_gcc.S',
+ 'cpu_gcc.S',
+ 'stack_gcc.S',
+ 'startup.c',
+ 'vector_gcc.S',
+ ]
+
+ bsp_startup = os.path.join(bsp_path, 'startup_gcc.S')
+ if os.path.isfile(bsp_startup):
+ bsp_startup_obj = Env.Object('startup_gcc.o', '#startup_gcc.S')
+ else:
+ src += ['startup_gcc.S']
+
+ if GetDepend('RT_USING_BUILTIN_FDT'):
+ dtb_path = os.path.join(bsp_path, GetDepend('RT_BUILTIN_FDT_PATH').strip('"'))
+ builtin_fdt_obj = Env.Object('builtin_fdt_gcc.o', 'builtin_fdt_gcc.S')
+ Env.Depends(builtin_fdt_obj, dtb_path)
+
+if GetDepend('ARCH_MM_MMU'):
+ src += ['mmu.c']
+
+if GetDepend('RT_USING_HW_ATOMIC'):
+ src += ['atomic_riscv.c']
+
+if GetDepend('RT_USING_LWP'):
+ src += ['syscall.c']
+
+if not GetDepend('ARCH_RISCV_M_MODE'):
+ src += ['sbi.c']
+
+ if not GetDepend('RT_USING_DM'):
+ src += ['console.c']
+
+if GetDepend('RT_USING_DM'):
+ src += ['setup.c']
+
+ if GetDepend('RT_USING_SMP'):
+ src += ['cpu_spinwait.c']
+
+ if not GetDepend('ARCH_RISCV_M_MODE'):
+ src += ['cpu_sbi.c']
+
+if not GetDepend('RT_USING_DM'):
+ src += ['interrupt.c']
+
+if GetDepend('ARCH_RISCV_USING_IRQ_STACK'):
+ src += ['irq_stack.c']
+
+group = DefineGroup('libcpu', src, depend = [''], CPPPATH = CPPPATH)
+group += bsp_startup_obj
+group += builtin_fdt_obj
+
+# build for sub-directory
+list = os.listdir(cwd)
+objs = []
+
+for d in list:
+ path = os.path.join(cwd, d)
+ if os.path.isfile(os.path.join(path, 'SConscript')):
+ objs = objs + SConscript(os.path.join(d, 'SConscript'))
+group = group + objs
Return('group')