feat: remove redundant codes under virt64, c906

Changes:

- create new folder name `common64` and save all common codes of rv64
  inside

Signed-off-by: Shell <[email protected]>

1 files changed, 0 insertions, 70 deletions

diff --git a/libcpu/risc-v/virt64/stack.h b/libcpu/risc-v/virt64/stack.h
deleted file mode 100644
index 4302b26e1f..0000000000
--- a/libcpu/risc-v/virt64/stack.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2006-2021, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2021-01-30     lizhirui     first version
- * 2021-11-18     JasonHu      add fpu member
- * 2022-10-22     Shell        Support kernel mode RVV
- */
-
-#ifndef __STACK_H__
-#define __STACK_H__
-
-#include "stackframe.h"
-
-#include <rtthread.h>
-
-typedef struct rt_hw_switch_frame
-{
-    uint64_t regs[RT_HW_SWITCH_CONTEXT_SIZE];
-} *rt_hw_switch_frame_t;
-
-
-struct rt_hw_stack_frame
-{
-    rt_ubase_t epc;        /* epc - epc    - program counter                     */
-    rt_ubase_t ra;         /* x1  - ra     - return address for jumps            */
-    rt_ubase_t sstatus;    /*              - supervisor status register          */
-    rt_ubase_t gp;         /* x3  - gp     - global pointer                      */
-    rt_ubase_t tp;         /* x4  - tp     - thread pointer                      */
-    rt_ubase_t t0;         /* x5  - t0     - temporary register 0                */
-    rt_ubase_t t1;         /* x6  - t1     - temporary register 1                */
-    rt_ubase_t t2;         /* x7  - t2     - temporary register 2                */
-    rt_ubase_t s0_fp;      /* x8  - s0/fp  - saved register 0 or frame pointer   */
-    rt_ubase_t s1;         /* x9  - s1     - saved register 1                    */
-    rt_ubase_t a0;         /* x10 - a0     - return value or function argument 0 */
-    rt_ubase_t a1;         /* x11 - a1     - return value or function argument 1 */
-    rt_ubase_t a2;         /* x12 - a2     - function argument 2                 */
-    rt_ubase_t a3;         /* x13 - a3     - function argument 3                 */
-    rt_ubase_t a4;         /* x14 - a4     - function argument 4                 */
-    rt_ubase_t a5;         /* x15 - a5     - function argument 5                 */
-    rt_ubase_t a6;         /* x16 - a6     - function argument 6                 */
-    rt_ubase_t a7;         /* x17 - s7     - function argument 7                 */
-    rt_ubase_t s2;         /* x18 - s2     - saved register 2                    */
-    rt_ubase_t s3;         /* x19 - s3     - saved register 3                    */
-    rt_ubase_t s4;         /* x20 - s4     - saved register 4                    */
-    rt_ubase_t s5;         /* x21 - s5     - saved register 5                    */
-    rt_ubase_t s6;         /* x22 - s6     - saved register 6                    */
-    rt_ubase_t s7;         /* x23 - s7     - saved register 7                    */
-    rt_ubase_t s8;         /* x24 - s8     - saved register 8                    */
-    rt_ubase_t s9;         /* x25 - s9     - saved register 9                    */
-    rt_ubase_t s10;        /* x26 - s10    - saved register 10                   */
-    rt_ubase_t s11;        /* x27 - s11    - saved register 11                   */
-    rt_ubase_t t3;         /* x28 - t3     - temporary register 3                */
-    rt_ubase_t t4;         /* x29 - t4     - temporary register 4                */
-    rt_ubase_t t5;         /* x30 - t5     - temporary register 5                */
-    rt_ubase_t t6;         /* x31 - t6     - temporary register 6                */
-    rt_ubase_t user_sp_exc_stack;    /* sscratch - user mode sp/exception stack  */
-    rt_ubase_t __padding;  /* align to 16bytes */
-#ifdef ARCH_RISCV_FPU
-    rt_ubase_t f[CTX_FPU_REG_NR];      /* f0~f31 */
-#endif /* ARCH_RISCV_FPU */
-#ifdef ARCH_RISCV_VECTOR
-    rt_ubase_t v[CTX_VECTOR_REG_NR];
-#endif /* ARCH_RISCV_VECTOR */
-};
-
-#endif