diff options
| author | Chen Wang <[email protected]> | 2025-01-08 16:39:27 +0800 |
|---|---|---|
| committer | Rbb666 <[email protected]> | 2025-01-10 17:14:13 +0800 |
| commit | 123ed1be1b17161e64b9b775f7fb9deb1d386416 (patch) | |
| tree | 7c38388dd9ec1d50f5b2cbf5d7c408969e5d5f15 /libcpu | |
| parent | bdd9447d709213b5076a152fbfa484fbb0f7ee19 (diff) | |
bsp: qemu-virt64-riscv: remove config RISCV_S_MODE
RISCV_S_MODE configuration only affects the code in
libcpu/risc-v/virt64, and the only bsp using this
libcpu is qemu-virt64-riscv.
Considering s-mode is the default mode RT-Thread
running on virt64 machine, it seems unnecessary to
make RISCV_S_MODE a Kconfig option.
Solution: Remove RISCV_S_MODE from Kconfig and define
it as a macro in the code in libcpu/risc-v/virt64.
Plus, due to this macro is only related to virt64, rename
RISCV_S_MODE to RISCV_VIRT64_S_MODE.
Update the .config/rtconfig.h in this patch.
Signed-off-by: Chen Wang <[email protected]>
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/risc-v/common64/README.md | 2 | ||||
| -rw-r--r-- | libcpu/risc-v/virt64/plic.c | 2 | ||||
| -rw-r--r-- | libcpu/risc-v/virt64/plic.h | 5 |
3 files changed, 6 insertions, 3 deletions
diff --git a/libcpu/risc-v/common64/README.md b/libcpu/risc-v/common64/README.md index 1d027216f1..5e7ea4bf92 100644 --- a/libcpu/risc-v/common64/README.md +++ b/libcpu/risc-v/common64/README.md @@ -33,7 +33,7 @@ | 选项 | 默认值 | 说明 | | --------------- | --- | ---------------------------------------------------------------------------------------------------- | -| RISCV_S_MODE | 打开 | 系统启动后是否运行在S态，关闭时系统将运行在M态；目前系统存在bug尚不可直接运行在M态，故此开关必须打开 | +| RISCV_VIRT64_S_MODE | 打开 | 系统启动后是否运行在S态，关闭时系统将运行在M态；目前系统存在bug尚不可直接运行在M态，故此开关必须打开 | | RT_USING_SMART | 关闭 | 是否开启RTThread SMART版本，开启后系统运行在S+U态，且会开启MMU页表(satp);关闭时系统仅运行在S态，MMU关闭(satp为bare translation) | | ARCH_USING_ASID | 关闭 | MMU是否支持asid | diff --git a/libcpu/risc-v/virt64/plic.c b/libcpu/risc-v/virt64/plic.c index f222146f34..8aab8b1292 100644 --- a/libcpu/risc-v/virt64/plic.c +++ b/libcpu/risc-v/virt64/plic.c @@ -52,7 +52,7 @@ void plic_irq_enable(int irq) { int hart = __raw_hartid(); *(uint32_t *)PLIC_ENABLE(hart) = ((*(uint32_t *)PLIC_ENABLE(hart)) | (1 << irq)); -#ifdef RISCV_S_MODE +#ifdef RISCV_VIRT64_S_MODE set_csr(sie, read_csr(sie) | MIP_SEIP); #else set_csr(mie, read_csr(mie) | MIP_MEIP); diff --git a/libcpu/risc-v/virt64/plic.h b/libcpu/risc-v/virt64/plic.h index 314210c66b..a13b6d9622 100644 --- a/libcpu/risc-v/virt64/plic.h +++ b/libcpu/risc-v/virt64/plic.h @@ -30,7 +30,10 @@ extern size_t plic_base; #define PLIC_ENABLE_STRIDE 0x80 #define PLIC_CONTEXT_STRIDE 0x1000 -#ifndef RISCV_S_MODE +/* RT-Thread runs in S-mode on virt64 by default */ +#define RISCV_VIRT64_S_MODE + +#ifndef RISCV_VIRT64_S_MODE #define PLIC_MENABLE_OFFSET (0x2000) #define PLIC_MTHRESHOLD_OFFSET (0x200000) #define PLIC_MCLAIM_OFFSET (0x200004) |