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authorrun.mao <[email protected]>2026-06-17 16:17:49 +0800
committerRbb666 <[email protected]>2026-06-26 17:54:38 +0800
commit187dc3fddfe45202f4c1000a724f38cdc742dd2e (patch)
tree387958745415b6397076390670e91d87d175ed3f /libcpu
parentcaca34c377f86d157381a260f4f39f79153165c9 (diff)
Fix:Always use vmalle1is for kernel aspace; only use aside1is for user aspace with non-global PTE.
Diffstat (limited to 'libcpu')
-rw-r--r--libcpu/aarch64/common/include/tlb.h20
1 files changed, 12 insertions, 8 deletions
diff --git a/libcpu/aarch64/common/include/tlb.h b/libcpu/aarch64/common/include/tlb.h
index bec19f6f2c..ede4c7fd83 100644
--- a/libcpu/aarch64/common/include/tlb.h
+++ b/libcpu/aarch64/common/include/tlb.h
@@ -51,14 +51,18 @@ static inline void rt_hw_tlb_invalidate_all_local(void)
static inline void rt_hw_tlb_invalidate_aspace(rt_aspace_t aspace)
{
#ifdef ARCH_USING_ASID
- __asm__ volatile(
- // ensure updates to pte completed
- "dsb nshst\n"
- "tlbi aside1is, %0\n"
- "dsb nsh\n"
- // after tlb in new context, refresh inst
- "isb\n" ::"r"(TLBI_ARG(0ul, aspace->asid))
- : "memory");
+ if (aspace == &rt_kernel_space) {
+ rt_hw_tlb_invalidate_all();
+ } else {
+ __asm__ volatile(
+ // ensure updates to pte completed
+ "dsb ishst\n"
+ "tlbi aside1is, %0\n"
+ "dsb ish\n"
+ // after tlb in new context, refresh inst
+ "isb\n" ::"r"(TLBI_ARG(0ul, aspace->asid))
+ : "memory");
+ }
#else
rt_hw_tlb_invalidate_all();
#endif