diff options
| author | Bernard Xiong <[email protected]> | 2021-08-09 08:53:42 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-08-09 08:53:42 +0800 |
| commit | 1e26128735023209f32ddbb5f8e6bb75cdfeb1ca (patch) | |
| tree | d19962817c21bd1e55f911bbacb8ad6e81d6fcb3 /libcpu | |
| parent | 0880b43498b9c783273fc011fc5838da734ec276 (diff) | |
| parent | f60514cd714405ff22d701af5aeb5424f6e9700b (diff) | |
Merge pull request #4871 from wormsX/master
Support T-HEAD Xuantie-E9xx Series CPU on Smart-EVB
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/risc-v/SConscript | 4 | ||||
| -rw-r--r-- | libcpu/risc-v/t-head/e9xx/SConscript (renamed from libcpu/risc-v/t-head/e906/SConscript) | 0 | ||||
| -rw-r--r-- | libcpu/risc-v/t-head/e9xx/context_gcc.S (renamed from libcpu/risc-v/t-head/e906/context_gcc.S) | 18 | ||||
| -rw-r--r-- | libcpu/risc-v/t-head/e9xx/cpuport.c (renamed from libcpu/risc-v/t-head/e906/cpuport.c) | 3 | ||||
| -rw-r--r-- | libcpu/risc-v/t-head/e9xx/cpuport.h (renamed from libcpu/risc-v/t-head/e906/cpuport.h) | 0 |
5 files changed, 23 insertions, 2 deletions
diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript index 18b4c2005d..2447aee65a 100644 --- a/libcpu/risc-v/SConscript +++ b/libcpu/risc-v/SConscript @@ -10,7 +10,7 @@ group = [] list = os.listdir(cwd) # add common code files -if rtconfig.CPU == "e906" : +if rtconfig.CPU == "e9xx" : group = group elif rtconfig.CPU == "nuclei" : group = group @@ -20,7 +20,7 @@ else : group = group + SConscript(os.path.join(cwd, 'common', 'SConscript')) # cpu porting code files -if rtconfig.CPU == "e906" : +if rtconfig.CPU == "e9xx" : group = group + SConscript(os.path.join(cwd, rtconfig.VENDOR, rtconfig.CPU, 'SConscript')) else : group = group + SConscript(os.path.join(cwd, rtconfig.CPU, 'SConscript')) diff --git a/libcpu/risc-v/t-head/e906/SConscript b/libcpu/risc-v/t-head/e9xx/SConscript index 92133bfb47..92133bfb47 100644 --- a/libcpu/risc-v/t-head/e906/SConscript +++ b/libcpu/risc-v/t-head/e9xx/SConscript diff --git a/libcpu/risc-v/t-head/e906/context_gcc.S b/libcpu/risc-v/t-head/e9xx/context_gcc.S index 2f5223ae63..9deaf80e41 100644 --- a/libcpu/risc-v/t-head/e906/context_gcc.S +++ b/libcpu/risc-v/t-head/e9xx/context_gcc.S @@ -181,7 +181,11 @@ PendSV_Handler: FSTORE f31, 31 * FREGBYTES(sp) #endif +#ifdef ARCH_RISCV_DSP + addi sp, sp, -33 * REGBYTES +#else addi sp, sp, -32 * REGBYTES +#endif STORE x1, 1 * REGBYTES(sp) csrr x1, mepc @@ -221,6 +225,10 @@ PendSV_Handler: STORE x29, 29 * REGBYTES(sp) STORE x30, 30 * REGBYTES(sp) STORE x31, 31 * REGBYTES(sp) +#ifdef ARCH_RISCV_DSP + csrr t0, vxsat + STORE t0, 32 * REGBYTES(sp) +#endif /* store from_thread sp */ la t0, rt_interrupt_from_thread @@ -237,6 +245,12 @@ PendSV_Handler: lw t0, (t0) LOAD sp, (t0) + +#ifdef ARCH_RISCV_DSP + LOAD a1, 32 * REGBYTES(sp) + csrw vxsat, a1 +#endif + /* restore ra to mepc */ LOAD a1, 0 * REGBYTES(sp) csrw mepc, a1 @@ -277,7 +291,11 @@ PendSV_Handler: LOAD x30, 30 * REGBYTES(sp) LOAD x31, 31 * REGBYTES(sp) +#ifdef ARCH_RISCV_DSP + addi sp, sp, 33 * REGBYTES +#else addi sp, sp, 32 * REGBYTES +#endif #ifdef ARCH_RISCV_FPU FLOAD f0, 0 * FREGBYTES(sp) diff --git a/libcpu/risc-v/t-head/e906/cpuport.c b/libcpu/risc-v/t-head/e9xx/cpuport.c index 0eaf5ffbce..6fa41b6da6 100644 --- a/libcpu/risc-v/t-head/e906/cpuport.c +++ b/libcpu/risc-v/t-head/e9xx/cpuport.c @@ -53,6 +53,9 @@ struct rt_hw_stack_frame rt_ubase_t t4; /* x29 - t4 - temporary register 4 */ rt_ubase_t t5; /* x30 - t5 - temporary register 5 */ rt_ubase_t t6; /* x31 - t6 - temporary register 6 */ +#ifdef ARCH_RISCV_DSP + rt_ubase_t vxsat; /* P-ext vxsat reg */ +#endif #ifdef ARCH_RISCV_FPU rv_floatreg_t f0; /* f0 */ rv_floatreg_t f1; /* f1 */ diff --git a/libcpu/risc-v/t-head/e906/cpuport.h b/libcpu/risc-v/t-head/e9xx/cpuport.h index 20302f44aa..20302f44aa 100644 --- a/libcpu/risc-v/t-head/e906/cpuport.h +++ b/libcpu/risc-v/t-head/e9xx/cpuport.h |