summaryrefslogtreecommitdiff
path: root/libcpu
diff options
context:
space:
mode:
authorRbb666 <[email protected]>2026-08-03 11:54:06 +0800
committerRbb666 <[email protected]>2026-08-12 12:54:50 +0800
commit1f23e3f27052a6b7fd75def2da634c79db5773e2 (patch)
treece553187fb7e2680569bbf13e767387f756cc657 /libcpu
parentf05fb1c0760f4791e22c62633650d9d52dc764af (diff)
fix(dm): route Cortex-M resets through power core
Diffstat (limited to 'libcpu')
-rw-r--r--libcpu/arm/cortex-m4/cpuport.c24
-rw-r--r--libcpu/arm/cortex-m7/cpuport.c23
-rw-r--r--libcpu/arm/cortex-m85/cpuport.c24
3 files changed, 68 insertions, 3 deletions
diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c
index 58a9a7c095..5db2fca7f3 100644
--- a/libcpu/arm/cortex-m4/cpuport.c
+++ b/libcpu/arm/cortex-m4/cpuport.c
@@ -20,6 +20,10 @@
#include <rtthread.h>
+#ifdef RT_USING_DM
+#include <drivers/core/power.h>
+#endif
+
#define DBG_TAG "cortex.m4"
#define DBG_LVL DBG_INFO
#include <rtdbg.h>
@@ -440,11 +444,29 @@ void rt_hw_hard_fault_exception(struct exception_info *exception_info)
/**
* reset CPU
*/
-void rt_hw_cpu_reset(void)
+static void cortex_m_cpu_reset(void)
{
SCB_AIRCR = SCB_RESET_VALUE;
}
+#ifdef RT_USING_DM
+static int cortex_m_cpu_reset_init(void)
+{
+ if (!rt_dm_machine_reset)
+ {
+ rt_dm_machine_reset = cortex_m_cpu_reset;
+ }
+
+ return RT_EOK;
+}
+INIT_BOARD_EXPORT(cortex_m_cpu_reset_init);
+#else
+void rt_hw_cpu_reset(void)
+{
+ cortex_m_cpu_reset();
+}
+#endif
+
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c
index 87677a012c..43d738fc2f 100644
--- a/libcpu/arm/cortex-m7/cpuport.c
+++ b/libcpu/arm/cortex-m7/cpuport.c
@@ -18,6 +18,9 @@
*/
#include <rtthread.h>
+#ifdef RT_USING_DM
+#include <drivers/core/power.h>
+#endif
#ifdef RT_USING_HW_STACK_GUARD
#include <mprotect.h>
#endif
@@ -460,11 +463,29 @@ void rt_hw_hard_fault_exception(struct exception_info *exception_info)
/**
* reset CPU
*/
-void rt_hw_cpu_reset(void)
+static void cortex_m_cpu_reset(void)
{
SCB_AIRCR = SCB_RESET_VALUE;
}
+#ifdef RT_USING_DM
+static int cortex_m_cpu_reset_init(void)
+{
+ if (!rt_dm_machine_reset)
+ {
+ rt_dm_machine_reset = cortex_m_cpu_reset;
+ }
+
+ return RT_EOK;
+}
+INIT_BOARD_EXPORT(cortex_m_cpu_reset_init);
+#else
+void rt_hw_cpu_reset(void)
+{
+ cortex_m_cpu_reset();
+}
+#endif
+
#ifdef RT_USING_CPU_FFS
/**
* This function finds the first bit set (beginning with the least significant bit)
diff --git a/libcpu/arm/cortex-m85/cpuport.c b/libcpu/arm/cortex-m85/cpuport.c
index cc07371710..4e38b2de95 100644
--- a/libcpu/arm/cortex-m85/cpuport.c
+++ b/libcpu/arm/cortex-m85/cpuport.c
@@ -19,6 +19,10 @@
#include <rtthread.h>
+#ifdef RT_USING_DM
+#include <drivers/core/power.h>
+#endif
+
rt_weak int rt_hw_cpu_id(void)
{
return 0;
@@ -443,11 +447,29 @@ rt_weak void rt_hw_cpu_shutdown(void)
/**
* reset CPU
*/
-rt_weak void rt_hw_cpu_reset(void)
+static void cortex_m_cpu_reset(void)
{
SCB_AIRCR = SCB_RESET_VALUE;
}
+#ifdef RT_USING_DM
+static int cortex_m_cpu_reset_init(void)
+{
+ if (!rt_dm_machine_reset)
+ {
+ rt_dm_machine_reset = cortex_m_cpu_reset;
+ }
+
+ return RT_EOK;
+}
+INIT_BOARD_EXPORT(cortex_m_cpu_reset_init);
+#else
+rt_weak void rt_hw_cpu_reset(void)
+{
+ cortex_m_cpu_reset();
+}
+#endif
+
void TaskSwitch_StackCheck(void)
{
volatile rt_uint32_t end_of_stack_val = (rt_uint32_t) rt_thread_self()->stack_addr;