diff options
| author | wirano <[email protected]> | 2024-04-18 20:37:48 -0400 |
|---|---|---|
| committer | Meco Man <[email protected]> | 2024-04-18 20:40:55 -0400 |
| commit | 202bacb44d9a4a253d74653d26714c1ae825822c (patch) | |
| tree | 266f686cf5005e19d28a8e45769b70c349848b8f /libcpu | |
| parent | 6493b2356f50ef41e1e85f4f43db3cf3c7cca97e (diff) | |
[cpu_cache] fix function replaced by macro
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/arm/cortex-m7/cpu_cache.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c index fe7acce2a1..6ec4c826d5 100644 --- a/libcpu/arm/cortex-m7/cpu_cache.c +++ b/libcpu/arm/cortex-m7/cpu_cache.c @@ -17,6 +17,8 @@ /* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ #define L1CACHE_LINESIZE_BYTE (32) +#ifdef RT_USING_CACHE + void rt_hw_cpu_icache_enable(void) { SCB_EnableICache(); @@ -89,3 +91,6 @@ void rt_hw_cpu_dcache_ops(int ops, void* addr, int size) RT_ASSERT(0); } } + +#endif /* RT_USING_CACHE */ + |