diff options
| author | Bernard Xiong <[email protected]> | 2021-03-31 14:15:21 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-03-31 14:15:21 +0800 |
| commit | 259144b2e658d6bdc543afb6b2e88f5461a070b4 (patch) | |
| tree | 7e4e1a241a70330b4f6a4e78d6549c9e68d4873d /libcpu | |
| parent | 28ec21671cfd8992b3ad2d6ea48989968ad23e7c (diff) | |
| parent | a15040d3a9175b13486d756eafe0dd03645368da (diff) | |
Merge branch 'master' into master
Diffstat (limited to 'libcpu')
256 files changed, 9661 insertions, 11552 deletions
diff --git a/libcpu/aarch64/common/armv8.h b/libcpu/aarch64/common/armv8.h index 4350890544..77fb4de8a2 100644 --- a/libcpu/aarch64/common/armv8.h +++ b/libcpu/aarch64/common/armv8.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,47 +14,47 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long long pc; - unsigned long long spsr; - unsigned long long x30; - unsigned long long xz; - unsigned long long x28; - unsigned long long x29; - unsigned long long x26; - unsigned long long x27; - unsigned long long x24; - unsigned long long x25; - unsigned long long x22; - unsigned long long x23; - unsigned long long x20; - unsigned long long x21; - unsigned long long x18; - unsigned long long x19; - unsigned long long x16; - unsigned long long x17; - unsigned long long x14; - unsigned long long x15; - unsigned long long x12; - unsigned long long x13; - unsigned long long x10; - unsigned long long x11; - unsigned long long x8; - unsigned long long x9; - unsigned long long x6; - unsigned long long x7; - unsigned long long x4; - unsigned long long x5; - unsigned long long x2; - unsigned long long x3; - unsigned long long x0; - unsigned long long x1; + unsigned long long pc; + unsigned long long spsr; + unsigned long long x30; + unsigned long long xz; + unsigned long long x28; + unsigned long long x29; + unsigned long long x26; + unsigned long long x27; + unsigned long long x24; + unsigned long long x25; + unsigned long long x22; + unsigned long long x23; + unsigned long long x20; + unsigned long long x21; + unsigned long long x18; + unsigned long long x19; + unsigned long long x16; + unsigned long long x17; + unsigned long long x14; + unsigned long long x15; + unsigned long long x12; + unsigned long long x13; + unsigned long long x10; + unsigned long long x11; + unsigned long long x8; + unsigned long long x9; + unsigned long long x6; + unsigned long long x7; + unsigned long long x4; + unsigned long long x5; + unsigned long long x2; + unsigned long long x3; + unsigned long long x0; + unsigned long long x1; }; -#define SP_ELx ( ( unsigned long long ) 0x01 ) -#define SP_EL0 ( ( unsigned long long ) 0x00 ) -#define PSTATE_EL1 ( ( unsigned long long ) 0x04 ) -#define PSTATE_EL2 ( ( unsigned long long ) 0x08 ) -#define PSTATE_EL3 ( ( unsigned long long ) 0x0c ) +#define SP_ELx ( ( unsigned long long ) 0x01 ) +#define SP_EL0 ( ( unsigned long long ) 0x00 ) +#define PSTATE_EL1 ( ( unsigned long long ) 0x04 ) +#define PSTATE_EL2 ( ( unsigned long long ) 0x08 ) +#define PSTATE_EL3 ( ( unsigned long long ) 0x0c ) rt_ubase_t rt_hw_get_current_el(void); void rt_hw_set_elx_env(void); diff --git a/libcpu/aarch64/common/cp15.h b/libcpu/aarch64/common/cp15.h index f3ffd6f857..e6d8626ab9 100644 --- a/libcpu/aarch64/common/cp15.h +++ b/libcpu/aarch64/common/cp15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -55,7 +55,7 @@ static inline void send_ipi_msg(int cpu, int ipi_vector) static inline void setup_bootstrap_addr(int cpu, int addr) { - CORE_MAILBOX3_SET(cpu) = addr; + CORE_MAILBOX3_SET(cpu) = addr; } static inline void enable_cpu_ipi_intr(int cpu) @@ -65,7 +65,7 @@ static inline void enable_cpu_ipi_intr(int cpu) static inline void enable_cpu_timer_intr(int cpu) { - CORETIMER_INTCTL(cpu) = 0x8; + CORETIMER_INTCTL(cpu) = 0x8; } static inline void enable_cntv(void) diff --git a/libcpu/aarch64/common/cpu.c b/libcpu/aarch64/common/cpu.c index 84d3df2e8a..66b540a5e5 100644 --- a/libcpu/aarch64/common/cpu.c +++ b/libcpu/aarch64/common/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c index 1f4d868636..ec690a1cc6 100644 --- a/libcpu/aarch64/common/gic/gic_pl400.c +++ b/libcpu/aarch64/common/gic/gic_pl400.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/common/gic/gic_pl400.h b/libcpu/aarch64/common/gic/gic_pl400.h index fa20846ea2..9ca4835b9a 100644 --- a/libcpu/aarch64/common/gic/gic_pl400.h +++ b/libcpu/aarch64/common/gic/gic_pl400.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/common/mmu.c b/libcpu/aarch64/common/mmu.c index b799143084..2a41c4f813 100644 --- a/libcpu/aarch64/common/mmu.c +++ b/libcpu/aarch64/common/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -52,7 +52,7 @@ void mmu_memset(char *dst, char v, size_t len) } static unsigned long __page_off = 0; -static unsigned long get_free_page(void) +static unsigned long get_free_page(void) { __page_off += 512; return (unsigned long)(main_tbl + __page_off); @@ -128,7 +128,7 @@ void mmu_enable(void) } -static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) +static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr) { int level; unsigned long* cur_lv_tbl = lv0_tbl; @@ -136,22 +136,22 @@ static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned unsigned long off; int level_shift = 39; - if (va & (0x200000UL - 1)) + if (va & (0x200000UL - 1)) { return MMU_MAP_ERROR_VANOTALIGN; } - if (pa & (0x200000UL - 1)) + if (pa & (0x200000UL - 1)) { return MMU_MAP_ERROR_PANOTALIGN; } - for (level = 0; level < 2; level++) + for (level = 0; level < 2; level++) { off = (va >> level_shift); off &= MMU_LEVEL_MASK; - if ((cur_lv_tbl[off] & 1) == 0) + if ((cur_lv_tbl[off] & 1) == 0) { page = get_free_page(); - if (!page) + if (!page) { return MMU_MAP_ERROR_NOPAGE; } @@ -159,7 +159,7 @@ static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned cur_lv_tbl[off] = page | 0x3UL; } page = cur_lv_tbl[off]; - if (!(page & 0x2)) + if (!(page & 0x2)) { //is block! error! return MMU_MAP_ERROR_CONFLICT; @@ -239,8 +239,8 @@ static int level2shift(int level) static uint64_t *get_level_table(uint64_t *pte) { uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK); - - if (pte_type(pte) != PMD_TYPE_TABLE) + + if (pte_type(pte) != PMD_TYPE_TABLE) { table = create_table(); set_table(pte, table); @@ -259,10 +259,10 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att int level = 0; addr = virt; - while (size) + while (size) { table = &main_tbl[0]; - for (level = 0; level < 4; level++) + for (level = 0; level < 4; level++) { block_shift = level2shift(level); idx = addr >> block_shift; @@ -270,7 +270,7 @@ static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t att block_size = (uint64_t)(1L << block_shift); pte = table + idx; - if (size >= block_size && IS_ALIGNED(addr, block_size)) + if (size >= block_size && IS_ALIGNED(addr, block_size)) { attr &= 0xfff0000000000ffcUL; if(level != 3) @@ -298,7 +298,7 @@ void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned void rt_hw_dcache_enable(void) { - if (!(get_sctlr() & CR_M)) + if (!(get_sctlr() & CR_M)) { rt_kprintf("please init mmu!\n"); } @@ -364,4 +364,4 @@ void rt_hw_icache_invalidate_all(void) void rt_hw_icache_disable(void) { set_sctlr(get_sctlr() & ~CR_I); -}
\ No newline at end of file +} diff --git a/libcpu/aarch64/common/mmu.h b/libcpu/aarch64/common/mmu.h index 6a66472c79..f3261c3a1d 100644 --- a/libcpu/aarch64/common/mmu.h +++ b/libcpu/aarch64/common/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/cortex-a53/interrupt.c b/libcpu/aarch64/cortex-a53/interrupt.c index a412ca1953..4a5d502a3c 100644 --- a/libcpu/aarch64/cortex-a53/interrupt.c +++ b/libcpu/aarch64/cortex-a53/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2018/5/3 Bernard first version * 2019-07-28 zdzn add smp support - * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, + * 2019-08-09 zhangjun fixup the problem of smp startup and scheduling issues, * write addr to mailbox3 to startup smp, and we use mailbox0 for ipi */ @@ -160,15 +160,15 @@ void rt_hw_ipi_send(int ipi_vector, unsigned int cpu_mask) } if(cpu_mask & 0x2) { - send_ipi_msg(1, ipi_vector); + send_ipi_msg(1, ipi_vector); } if(cpu_mask & 0x4) { - send_ipi_msg(2, ipi_vector); + send_ipi_msg(2, ipi_vector); } if(cpu_mask & 0x8) { - send_ipi_msg(3, ipi_vector); + send_ipi_msg(3, ipi_vector); } __DSB(); } diff --git a/libcpu/aarch64/cortex-a53/interrupt.h b/libcpu/aarch64/cortex-a53/interrupt.h index 8e741ed4e6..94a455550d 100644 --- a/libcpu/aarch64/cortex-a53/interrupt.h +++ b/libcpu/aarch64/cortex-a53/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/cortex-a53/stack.c b/libcpu/aarch64/cortex-a53/stack.c index 68222c2c67..751793d7a3 100644 --- a/libcpu/aarch64/cortex-a53/stack.c +++ b/libcpu/aarch64/cortex-a53/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,70 +21,70 @@ * This function will initialize thread stack * * @param tentry the entry of thread - * @param parameter the parameter of entry + * @param parameter the parameter of entry * @param stack_addr the beginning stack address * @param texit the function will be called when thread exit * * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - rt_ubase_t *stk; - rt_ubase_t current_el; + rt_ubase_t *stk; + rt_ubase_t current_el; - stk = (rt_ubase_t*)stack_addr; + stk = (rt_ubase_t*)stack_addr; - *(--stk) = ( rt_ubase_t ) 11; /* X1 */ - *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ - *(--stk) = ( rt_ubase_t ) 33; /* X3 */ - *(--stk) = ( rt_ubase_t ) 22; /* X2 */ - *(--stk) = ( rt_ubase_t ) 55; /* X5 */ - *(--stk) = ( rt_ubase_t ) 44; /* X4 */ - *(--stk) = ( rt_ubase_t ) 77; /* X7 */ - *(--stk) = ( rt_ubase_t ) 66; /* X6 */ - *(--stk) = ( rt_ubase_t ) 99; /* X9 */ - *(--stk) = ( rt_ubase_t ) 88; /* X8 */ - *(--stk) = ( rt_ubase_t ) 11; /* X11 */ - *(--stk) = ( rt_ubase_t ) 10; /* X10 */ - *(--stk) = ( rt_ubase_t ) 13; /* X13 */ - *(--stk) = ( rt_ubase_t ) 12; /* X12 */ - *(--stk) = ( rt_ubase_t ) 15; /* X15 */ - *(--stk) = ( rt_ubase_t ) 14; /* X14 */ - *(--stk) = ( rt_ubase_t ) 17; /* X17 */ - *(--stk) = ( rt_ubase_t ) 16; /* X16 */ - *(--stk) = ( rt_ubase_t ) 19; /* X19 */ - *(--stk) = ( rt_ubase_t ) 18; /* X18 */ - *(--stk) = ( rt_ubase_t ) 21; /* X21 */ - *(--stk) = ( rt_ubase_t ) 20; /* X20 */ - *(--stk) = ( rt_ubase_t ) 23; /* X23 */ - *(--stk) = ( rt_ubase_t ) 22; /* X22 */ - *(--stk) = ( rt_ubase_t ) 25; /* X25 */ - *(--stk) = ( rt_ubase_t ) 24; /* X24 */ - *(--stk) = ( rt_ubase_t ) 27; /* X27 */ - *(--stk) = ( rt_ubase_t ) 26; /* X26 */ - *(--stk) = ( rt_ubase_t ) 29; /* X29 */ - *(--stk) = ( rt_ubase_t ) 28; /* X28 */ - *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ - *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ + *(--stk) = ( rt_ubase_t ) 11; /* X1 */ + *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ + *(--stk) = ( rt_ubase_t ) 33; /* X3 */ + *(--stk) = ( rt_ubase_t ) 22; /* X2 */ + *(--stk) = ( rt_ubase_t ) 55; /* X5 */ + *(--stk) = ( rt_ubase_t ) 44; /* X4 */ + *(--stk) = ( rt_ubase_t ) 77; /* X7 */ + *(--stk) = ( rt_ubase_t ) 66; /* X6 */ + *(--stk) = ( rt_ubase_t ) 99; /* X9 */ + *(--stk) = ( rt_ubase_t ) 88; /* X8 */ + *(--stk) = ( rt_ubase_t ) 11; /* X11 */ + *(--stk) = ( rt_ubase_t ) 10; /* X10 */ + *(--stk) = ( rt_ubase_t ) 13; /* X13 */ + *(--stk) = ( rt_ubase_t ) 12; /* X12 */ + *(--stk) = ( rt_ubase_t ) 15; /* X15 */ + *(--stk) = ( rt_ubase_t ) 14; /* X14 */ + *(--stk) = ( rt_ubase_t ) 17; /* X17 */ + *(--stk) = ( rt_ubase_t ) 16; /* X16 */ + *(--stk) = ( rt_ubase_t ) 19; /* X19 */ + *(--stk) = ( rt_ubase_t ) 18; /* X18 */ + *(--stk) = ( rt_ubase_t ) 21; /* X21 */ + *(--stk) = ( rt_ubase_t ) 20; /* X20 */ + *(--stk) = ( rt_ubase_t ) 23; /* X23 */ + *(--stk) = ( rt_ubase_t ) 22; /* X22 */ + *(--stk) = ( rt_ubase_t ) 25; /* X25 */ + *(--stk) = ( rt_ubase_t ) 24; /* X24 */ + *(--stk) = ( rt_ubase_t ) 27; /* X27 */ + *(--stk) = ( rt_ubase_t ) 26; /* X26 */ + *(--stk) = ( rt_ubase_t ) 29; /* X29 */ + *(--stk) = ( rt_ubase_t ) 28; /* X28 */ + *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ + *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ - current_el = rt_hw_get_current_el(); + current_el = rt_hw_get_current_el(); - if(current_el == 3) - { - *(--stk) = INITIAL_SPSR_EL3; - } - else if(current_el == 2) - { - *(--stk) = INITIAL_SPSR_EL2; - } - else - { - *(--stk) = INITIAL_SPSR_EL1; - } + if(current_el == 3) + { + *(--stk) = INITIAL_SPSR_EL3; + } + else if(current_el == 2) + { + *(--stk) = INITIAL_SPSR_EL2; + } + else + { + *(--stk) = INITIAL_SPSR_EL1; + } - *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ + *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } diff --git a/libcpu/aarch64/cortex-a53/trap.c b/libcpu/aarch64/cortex-a53/trap.c index 41d4d620f6..d43e0e4d6a 100644 --- a/libcpu/aarch64/cortex-a53/trap.c +++ b/libcpu/aarch64/cortex-a53/trap.c @@ -1,8 +1,8 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * + * * Date Author Notes * 2018-10-06 ZhaoXiaowei the first version */ @@ -28,14 +28,14 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs) rt_kprintf("Execption:\n"); rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3); rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7); - rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); - rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); - rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); - rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); + rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); + rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); + rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); + rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27); - rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); - rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); - rt_kprintf("return pc:0x%16.16lx\n", regs->pc); + rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); + rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); + rt_kprintf("return pc:0x%16.16lx\n", regs->pc); } /** @@ -57,7 +57,7 @@ void rt_hw_trap_error(struct rt_hw_exp_stack *regs) } #define GIC_ACK_INTID_MASK (0x000003ff) -#define CORE0_IRQ_SOURCE (0x40000060) +#define CORE0_IRQ_SOURCE (0x40000060) void rt_hw_trap_irq(void) { diff --git a/libcpu/aarch64/cortex-a72/interrupt.c b/libcpu/aarch64/cortex-a72/interrupt.c index 3b689dceb3..3ecb7750ad 100644 --- a/libcpu/aarch64/cortex-a72/interrupt.c +++ b/libcpu/aarch64/cortex-a72/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/cortex-a72/interrupt.h b/libcpu/aarch64/cortex-a72/interrupt.h index 0d2d4867c7..72e69bd808 100644 --- a/libcpu/aarch64/cortex-a72/interrupt.h +++ b/libcpu/aarch64/cortex-a72/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/aarch64/cortex-a72/stack.c b/libcpu/aarch64/cortex-a72/stack.c index 68222c2c67..751793d7a3 100644 --- a/libcpu/aarch64/cortex-a72/stack.c +++ b/libcpu/aarch64/cortex-a72/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,70 +21,70 @@ * This function will initialize thread stack * * @param tentry the entry of thread - * @param parameter the parameter of entry + * @param parameter the parameter of entry * @param stack_addr the beginning stack address * @param texit the function will be called when thread exit * * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - rt_ubase_t *stk; - rt_ubase_t current_el; + rt_ubase_t *stk; + rt_ubase_t current_el; - stk = (rt_ubase_t*)stack_addr; + stk = (rt_ubase_t*)stack_addr; - *(--stk) = ( rt_ubase_t ) 11; /* X1 */ - *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ - *(--stk) = ( rt_ubase_t ) 33; /* X3 */ - *(--stk) = ( rt_ubase_t ) 22; /* X2 */ - *(--stk) = ( rt_ubase_t ) 55; /* X5 */ - *(--stk) = ( rt_ubase_t ) 44; /* X4 */ - *(--stk) = ( rt_ubase_t ) 77; /* X7 */ - *(--stk) = ( rt_ubase_t ) 66; /* X6 */ - *(--stk) = ( rt_ubase_t ) 99; /* X9 */ - *(--stk) = ( rt_ubase_t ) 88; /* X8 */ - *(--stk) = ( rt_ubase_t ) 11; /* X11 */ - *(--stk) = ( rt_ubase_t ) 10; /* X10 */ - *(--stk) = ( rt_ubase_t ) 13; /* X13 */ - *(--stk) = ( rt_ubase_t ) 12; /* X12 */ - *(--stk) = ( rt_ubase_t ) 15; /* X15 */ - *(--stk) = ( rt_ubase_t ) 14; /* X14 */ - *(--stk) = ( rt_ubase_t ) 17; /* X17 */ - *(--stk) = ( rt_ubase_t ) 16; /* X16 */ - *(--stk) = ( rt_ubase_t ) 19; /* X19 */ - *(--stk) = ( rt_ubase_t ) 18; /* X18 */ - *(--stk) = ( rt_ubase_t ) 21; /* X21 */ - *(--stk) = ( rt_ubase_t ) 20; /* X20 */ - *(--stk) = ( rt_ubase_t ) 23; /* X23 */ - *(--stk) = ( rt_ubase_t ) 22; /* X22 */ - *(--stk) = ( rt_ubase_t ) 25; /* X25 */ - *(--stk) = ( rt_ubase_t ) 24; /* X24 */ - *(--stk) = ( rt_ubase_t ) 27; /* X27 */ - *(--stk) = ( rt_ubase_t ) 26; /* X26 */ - *(--stk) = ( rt_ubase_t ) 29; /* X29 */ - *(--stk) = ( rt_ubase_t ) 28; /* X28 */ - *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ - *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ + *(--stk) = ( rt_ubase_t ) 11; /* X1 */ + *(--stk) = ( rt_ubase_t ) parameter; /* X0 */ + *(--stk) = ( rt_ubase_t ) 33; /* X3 */ + *(--stk) = ( rt_ubase_t ) 22; /* X2 */ + *(--stk) = ( rt_ubase_t ) 55; /* X5 */ + *(--stk) = ( rt_ubase_t ) 44; /* X4 */ + *(--stk) = ( rt_ubase_t ) 77; /* X7 */ + *(--stk) = ( rt_ubase_t ) 66; /* X6 */ + *(--stk) = ( rt_ubase_t ) 99; /* X9 */ + *(--stk) = ( rt_ubase_t ) 88; /* X8 */ + *(--stk) = ( rt_ubase_t ) 11; /* X11 */ + *(--stk) = ( rt_ubase_t ) 10; /* X10 */ + *(--stk) = ( rt_ubase_t ) 13; /* X13 */ + *(--stk) = ( rt_ubase_t ) 12; /* X12 */ + *(--stk) = ( rt_ubase_t ) 15; /* X15 */ + *(--stk) = ( rt_ubase_t ) 14; /* X14 */ + *(--stk) = ( rt_ubase_t ) 17; /* X17 */ + *(--stk) = ( rt_ubase_t ) 16; /* X16 */ + *(--stk) = ( rt_ubase_t ) 19; /* X19 */ + *(--stk) = ( rt_ubase_t ) 18; /* X18 */ + *(--stk) = ( rt_ubase_t ) 21; /* X21 */ + *(--stk) = ( rt_ubase_t ) 20; /* X20 */ + *(--stk) = ( rt_ubase_t ) 23; /* X23 */ + *(--stk) = ( rt_ubase_t ) 22; /* X22 */ + *(--stk) = ( rt_ubase_t ) 25; /* X25 */ + *(--stk) = ( rt_ubase_t ) 24; /* X24 */ + *(--stk) = ( rt_ubase_t ) 27; /* X27 */ + *(--stk) = ( rt_ubase_t ) 26; /* X26 */ + *(--stk) = ( rt_ubase_t ) 29; /* X29 */ + *(--stk) = ( rt_ubase_t ) 28; /* X28 */ + *(--stk) = ( rt_ubase_t ) 0; /* XZR - has no effect, used so there are an even number of registers. */ + *(--stk) = ( rt_ubase_t ) texit; /* X30 - procedure call link register. */ - current_el = rt_hw_get_current_el(); + current_el = rt_hw_get_current_el(); - if(current_el == 3) - { - *(--stk) = INITIAL_SPSR_EL3; - } - else if(current_el == 2) - { - *(--stk) = INITIAL_SPSR_EL2; - } - else - { - *(--stk) = INITIAL_SPSR_EL1; - } + if(current_el == 3) + { + *(--stk) = INITIAL_SPSR_EL3; + } + else if(current_el == 2) + { + *(--stk) = INITIAL_SPSR_EL2; + } + else + { + *(--stk) = INITIAL_SPSR_EL1; + } - *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ + *(--stk) = ( rt_ubase_t ) tentry; /* Exception return address. */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } diff --git a/libcpu/aarch64/cortex-a72/trap.c b/libcpu/aarch64/cortex-a72/trap.c index d93aa18fd6..bd76f7717b 100644 --- a/libcpu/aarch64/cortex-a72/trap.c +++ b/libcpu/aarch64/cortex-a72/trap.c @@ -1,8 +1,8 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * + * * Date Author Notes * 2018-10-06 ZhaoXiaowei the first version */ @@ -28,14 +28,14 @@ void rt_hw_show_register(struct rt_hw_exp_stack *regs) rt_kprintf("Execption:\n"); rt_kprintf("r00:0x%16.16lx r01:0x%16.16lx r02:0x%16.16lx r03:0x%16.16lx\n", regs->x0, regs->x1, regs->x2, regs->x3); rt_kprintf("r04:0x%16.16lx r05:0x%16.16lx r06:0x%16.16lx r07:0x%16.16lx\n", regs->x4, regs->x5, regs->x6, regs->x7); - rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); - rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); - rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); - rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); + rt_kprintf("r08:0x%16.16lx r09:0x%16.16lx r10:0x%16.16lx r11:0x%16.16lx\n", regs->x8, regs->x9, regs->x10, regs->x11); + rt_kprintf("r12:0x%16.16lx r13:0x%16.16lx r14:0x%16.16lx r15:0x%16.16lx\n", regs->x12, regs->x13, regs->x14, regs->x15); + rt_kprintf("r16:0x%16.16lx r17:0x%16.16lx r18:0x%16.16lx r19:0x%16.16lx\n", regs->x16, regs->x17, regs->x18, regs->x19); + rt_kprintf("r20:0x%16.16lx r21:0x%16.16lx r22:0x%16.16lx r23:0x%16.16lx\n", regs->x20, regs->x21, regs->x22, regs->x23); rt_kprintf("r24:0x%16.16lx r25:0x%16.16lx r26:0x%16.16lx r27:0x%16.16lx\n", regs->x24, regs->x25, regs->x26, regs->x27); - rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); - rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); - rt_kprintf("return pc:0x%16.16lx\n", regs->pc); + rt_kprintf("r28:0x%16.16lx r29:0x%16.16lx r30:0x%16.16lx\n", regs->x28, regs->x29, regs->x30); + rt_kprintf("spsr:0x%16.16lx\n", regs->spsr); + rt_kprintf("return pc:0x%16.16lx\n", regs->pc); } /** @@ -64,7 +64,7 @@ void rt_hw_interrupt_ack(int fiq_irq); void rt_hw_trap_irq(void) { void *param; - int ir; + int ir; rt_isr_handler_t isr_func; extern struct rt_irq_desc isr_table[]; diff --git a/libcpu/arc/em/cpuport.c b/libcpu/arc/em/cpuport.c index 1a2593644a..d3bd8af6fe 100644 --- a/libcpu/arc/em/cpuport.c +++ b/libcpu/arc/em/cpuport.c @@ -22,11 +22,11 @@ rt_uint32_t rt_interrupt_to_thread; rt_uint32_t exc_nest_count; struct init_stack_frame { - rt_uint32_t pc; - rt_uint32_t blink; - rt_uint32_t task; - rt_uint32_t status32; - rt_uint32_t r0; + rt_uint32_t pc; + rt_uint32_t blink; + rt_uint32_t task; + rt_uint32_t status32; + rt_uint32_t r0; }; /** @@ -55,7 +55,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, stack_frame->blink = (rt_uint32_t)texit; stack_frame->task = (rt_uint32_t)tentry; stack_frame->status32 = ARC_INIT_STATUS; - stack_frame->r0 = (rt_uint32_t)parameter; + stack_frame->r0 = (rt_uint32_t)parameter; return stk; } @@ -74,14 +74,14 @@ void rt_hw_exception_install(rt_err_t (*exception_handle)(void *context)) void set_hw_stack_check(rt_uint32_t *from, rt_uint32_t *to) { struct rt_thread *rt_thread_to; - if (to != NULL) { + if (to != NULL) { rt_thread_to = rt_container_of(to, struct rt_thread, sp); #if ARC_FEATURE_SEC_PRESENT - arc_aux_write(AUX_S_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr)); - arc_aux_write(AUX_S_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size); + arc_aux_write(AUX_S_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr)); + arc_aux_write(AUX_S_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size); #else - arc_aux_write(AUX_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr)); - arc_aux_write(AUX_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size); + arc_aux_write(AUX_KSTACK_TOP, (uint32_t)(rt_thread_to->stack_addr)); + arc_aux_write(AUX_KSTACK_BASE, (uint32_t)(rt_thread_to->stack_addr)+rt_thread_to->stack_size); #endif - } + } } diff --git a/libcpu/arm/AT91SAM7S/AT91SAM7S.h b/libcpu/arm/AT91SAM7S/AT91SAM7S.h index 130f9074d1..91b57053da 100644 --- a/libcpu/arm/AT91SAM7S/AT91SAM7S.h +++ b/libcpu/arm/AT91SAM7S/AT91SAM7S.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,276 +15,276 @@ extern "C" { #endif -#define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ +#define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ /* ========== Register definition for TC0 peripheral ========== */ -#define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ -#define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ -#define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ -#define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ -#define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ -#define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ -#define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ -#define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ -#define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ +#define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ +#define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ +#define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ +#define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ +#define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ +#define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ +#define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ +#define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ +#define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ /* ========== Register definition for TC1 peripheral ========== */ -#define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ -#define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ -#define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ -#define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ -#define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ -#define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ -#define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ -#define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ -#define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ +#define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ +#define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ +#define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ +#define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ +#define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ +#define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ +#define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ +#define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ +#define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ /* ========== Register definition for TC2 peripheral ========== */ -#define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ -#define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ -#define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ -#define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ -#define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ -#define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ -#define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ -#define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ -#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ -#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ +#define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ +#define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ +#define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ +#define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ +#define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ +#define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ +#define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ +#define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ +#define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ +#define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ /* ========== Register definition for PITC peripheral ========== */ -#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ -#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ -#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ -#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ +#define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ +#define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ +#define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ +#define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ /* ========== Register definition for UDP peripheral ========== */ -#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ -#define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ -#define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ -#define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ -#define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ -#define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ -#define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ -#define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ -#define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ -#define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ -#define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) -#define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ -#define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) -#define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ +#define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ +#define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ +#define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ +#define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ +#define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ +#define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ +#define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ +#define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ +#define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ +#define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ +#define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) +#define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ +#define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) +#define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ /* ========== Register definition for US0 peripheral ========== */ -#define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ -#define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ -#define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ -#define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ -#define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ -#define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ -#define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ -#define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ -#define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ -#define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ -#define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ -#define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ -#define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ -#define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ +#define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ +#define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ +#define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ +#define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ +#define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ +#define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ +#define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ +#define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ +#define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ +#define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ +#define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ +#define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ +#define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ +#define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ /* ========== Register definition for AIC peripheral ========== */ -#define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ -#define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) -#define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ -#define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) -#define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ -#define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ -#define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ -#define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ -#define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ -#define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ -#define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ -#define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ -#define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ -#define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ -#define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ -#define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ -#define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ -#define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ -#define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ -#define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ +#define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ +#define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) +#define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ +#define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) +#define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ +#define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ +#define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ +#define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ +#define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ +#define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ +#define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ +#define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ +#define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ +#define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ +#define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ +#define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ +#define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ +#define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ +#define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ +#define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ /* ========== Register definition for DBGU peripheral ========== */ -#define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ -#define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ -#define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ -#define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ -#define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ -#define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ -#define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ -#define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ -#define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ -#define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ -#define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ -#define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ +#define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ +#define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ +#define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ +#define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ +#define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ +#define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ +#define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ +#define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ +#define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ +#define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ +#define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ +#define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ /* ========== Register definition for PIO peripheral ========== */ -#define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ -#define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ -#define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ -#define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ -#define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ -#define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ -#define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ -#define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ -#define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ -#define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ -#define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ -#define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ -#define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ -#define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ -#define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ -#define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ -#define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ -#define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ -#define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ -#define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ -#define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ -#define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ -#define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ -#define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ -#define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ -#define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ -#define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ -#define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ -#define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ +#define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ +#define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ +#define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ +#define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ +#define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ +#define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ +#define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ +#define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ +#define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ +#define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ +#define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ +#define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ +#define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ +#define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ +#define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ +#define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ +#define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ +#define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ +#define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ +#define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ +#define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ +#define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ +#define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ +#define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ +#define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ +#define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ +#define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ +#define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ +#define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ // ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register +#define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register +#define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register +#define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register +#define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register +#define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register +#define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register +#define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register +#define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register +#define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register +#define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register +#define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register +#define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register +#define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register +#define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register +#define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr +#define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register +#define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register +#define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register +#define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register +#define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register +#define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register +#define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register +#define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register +#define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register +#define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register +#define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register +#define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register +#define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register +#define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register // ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register -#define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register -#define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register -#define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register -#define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register -#define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register -#define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register -#define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register -#define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register -#define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register +#define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register +#define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register +#define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register +#define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register +#define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register +#define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register +#define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register +#define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register +#define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register +#define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register +#define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register +#define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register +#define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register +#define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr +#define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register +#define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register +#define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register +#define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register +#define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register +#define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register +#define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register +#define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register +#define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register +#define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register +#define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register +#define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register +#define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register +#define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register +#define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register /* ========== Register definition for PMC peripheral ========== */ -#define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ -#define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ -#define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ -#define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ -#define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ -#define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ -#define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ -#define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ -#define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ -#define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ -#define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ -#define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ -#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ -#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ -#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ +#define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ +#define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ +#define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ +#define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ +#define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ +#define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ +#define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ +#define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ +#define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ +#define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ +#define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ +#define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ +#define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ +#define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ +#define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ /******************************************************************************/ /* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ /******************************************************************************/ -#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ -#define AT91C_ID_SYS 1 /* System Peripheral */ -#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ -#define AT91C_ID_PIOB 3 /* Parallel IO Controller B */ -#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ -#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ -#define AT91C_ID_US0 6 /* USART 0 */ -#define AT91C_ID_US1 7 /* USART 1 */ -#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ -#define AT91C_ID_TWI 9 /* Two-Wire Interface */ -#define AT91C_ID_PWMC 10 /* PWM Controller */ -#define AT91C_ID_UDP 11 /* USB Device Port */ -#define AT91C_ID_TC0 12 /* Timer Counter 0 */ -#define AT91C_ID_TC1 13 /* Timer Counter 1 */ -#define AT91C_ID_TC2 14 /* Timer Counter 2 */ -#define AT91C_ID_15 15 /* Reserved */ -#define AT91C_ID_16 16 /* Reserved */ -#define AT91C_ID_17 17 /* Reserved */ -#define AT91C_ID_18 18 /* Reserved */ -#define AT91C_ID_19 19 /* Reserved */ -#define AT91C_ID_20 20 /* Reserved */ -#define AT91C_ID_21 21 /* Reserved */ -#define AT91C_ID_22 22 /* Reserved */ -#define AT91C_ID_23 23 /* Reserved */ -#define AT91C_ID_24 24 /* Reserved */ -#define AT91C_ID_25 25 /* Reserved */ -#define AT91C_ID_26 26 /* Reserved */ -#define AT91C_ID_27 27 /* Reserved */ -#define AT91C_ID_28 28 /* Reserved */ -#define AT91C_ID_29 29 /* Reserved */ -#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ -#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ -#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ +#define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ +#define AT91C_ID_SYS 1 /* System Peripheral */ +#define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ +#define AT91C_ID_PIOB 3 /* Parallel IO Controller B */ +#define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ +#define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ +#define AT91C_ID_US0 6 /* USART 0 */ +#define AT91C_ID_US1 7 /* USART 1 */ +#define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ +#define AT91C_ID_TWI 9 /* Two-Wire Interface */ +#define AT91C_ID_PWMC 10 /* PWM Controller */ +#define AT91C_ID_UDP 11 /* USB Device Port */ +#define AT91C_ID_TC0 12 /* Timer Counter 0 */ +#define AT91C_ID_TC1 13 /* Timer Counter 1 */ +#define AT91C_ID_TC2 14 /* Timer Counter 2 */ +#define AT91C_ID_15 15 /* Reserved */ +#define AT91C_ID_16 16 /* Reserved */ +#define AT91C_ID_17 17 /* Reserved */ +#define AT91C_ID_18 18 /* Reserved */ +#define AT91C_ID_19 19 /* Reserved */ +#define AT91C_ID_20 20 /* Reserved */ +#define AT91C_ID_21 21 /* Reserved */ +#define AT91C_ID_22 22 /* Reserved */ +#define AT91C_ID_23 23 /* Reserved */ +#define AT91C_ID_24 24 /* Reserved */ +#define AT91C_ID_25 25 /* Reserved */ +#define AT91C_ID_26 26 /* Reserved */ +#define AT91C_ID_27 27 /* Reserved */ +#define AT91C_ID_28 28 /* Reserved */ +#define AT91C_ID_29 29 /* Reserved */ +#define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ +#define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ +#define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 #ifdef __cplusplus } diff --git a/libcpu/arm/AT91SAM7S/cpu.c b/libcpu/arm/AT91SAM7S/cpu.c index b24ab5644b..18d8d6208a 100644 --- a/libcpu/arm/AT91SAM7S/cpu.c +++ b/libcpu/arm/AT91SAM7S/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/interrupt.c b/libcpu/arm/AT91SAM7S/interrupt.c index db9d31fe28..e4aa8643f1 100644 --- a/libcpu/arm/AT91SAM7S/interrupt.c +++ b/libcpu/arm/AT91SAM7S/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,7 +11,7 @@ #include <rtthread.h> #include "AT91SAM7S.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 extern rt_uint32_t rt_interrupt_nest; @@ -25,7 +25,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -33,18 +33,18 @@ void rt_hw_interrupt_handler(int vector) */ void rt_hw_interrupt_init() { - rt_base_t index; + rt_base_t index; - for (index = 0; index < MAX_HANDLERS; index ++) - { - AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler; - } + for (index = 0; index < MAX_HANDLERS; index ++) + { + AT91C_AIC_SVR(index) = (rt_uint32_t)rt_hw_interrupt_handler; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -53,11 +53,11 @@ void rt_hw_interrupt_init() */ void rt_hw_interrupt_mask(int vector) { - /* disable interrupt */ - AT91C_AIC_IDCR = 1 << vector; + /* disable interrupt */ + AT91C_AIC_IDCR = 1 << vector; - /* clear interrupt */ - AT91C_AIC_ICCR = 1 << vector; + /* clear interrupt */ + AT91C_AIC_ICCR = 1 << vector; } /** @@ -66,7 +66,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - AT91C_AIC_IECR = 1 << vector; + AT91C_AIC_IECR = 1 << vector; } /** @@ -77,11 +77,11 @@ void rt_hw_interrupt_umask(int vector) */ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) { - if(vector >= 0 && vector < MAX_HANDLERS) - { - if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)AT91C_AIC_SVR(vector); - if (new_handler != RT_NULL) AT91C_AIC_SVR(vector) = (rt_uint32_t)new_handler; - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)AT91C_AIC_SVR(vector); + if (new_handler != RT_NULL) AT91C_AIC_SVR(vector) = (rt_uint32_t)new_handler; + } } /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/serial.c b/libcpu/arm/AT91SAM7S/serial.c index adbe8609d6..583443f4cb 100644 --- a/libcpu/arm/AT91SAM7S/serial.c +++ b/libcpu/arm/AT91SAM7S/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,46 +22,46 @@ typedef volatile rt_uint32_t REG32; struct rt_at91serial_hw { - REG32 US_CR; // Control Register - REG32 US_MR; // Mode Register - REG32 US_IER; // Interrupt Enable Register - REG32 US_IDR; // Interrupt Disable Register - REG32 US_IMR; // Interrupt Mask Register - REG32 US_CSR; // Channel Status Register - REG32 US_RHR; // Receiver Holding Register - REG32 US_THR; // Transmitter Holding Register - REG32 US_BRGR; // Baud Rate Generator Register - REG32 US_RTOR; // Receiver Time-out Register - REG32 US_TTGR; // Transmitter Time-guard Register - REG32 Reserved0[5]; // - REG32 US_FIDI; // FI_DI_Ratio Register - REG32 US_NER; // Nb Errors Register - REG32 Reserved1[1]; // - REG32 US_IF; // IRDA_FILTER Register - REG32 Reserved2[44]; // - REG32 US_RPR; // Receive Pointer Register - REG32 US_RCR; // Receive Counter Register - REG32 US_TPR; // Transmit Pointer Register - REG32 US_TCR; // Transmit Counter Register - REG32 US_RNPR; // Receive Next Pointer Register - REG32 US_RNCR; // Receive Next Counter Register - REG32 US_TNPR; // Transmit Next Pointer Register - REG32 US_TNCR; // Transmit Next Counter Register - REG32 US_PTCR; // PDC Transfer Control Register - REG32 US_PTSR; // PDC Transfer Status Register + REG32 US_CR; // Control Register + REG32 US_MR; // Mode Register + REG32 US_IER; // Interrupt Enable Register + REG32 US_IDR; // Interrupt Disable Register + REG32 US_IMR; // Interrupt Mask Register + REG32 US_CSR; // Channel Status Register + REG32 US_RHR; // Receiver Holding Register + REG32 US_THR; // Transmitter Holding Register + REG32 US_BRGR; // Baud Rate Generator Register + REG32 US_RTOR; // Receiver Time-out Register + REG32 US_TTGR; // Transmitter Time-guard Register + REG32 Reserved0[5]; // + REG32 US_FIDI; // FI_DI_Ratio Register + REG32 US_NER; // Nb Errors Register + REG32 Reserved1[1]; // + REG32 US_IF; // IRDA_FILTER Register + REG32 Reserved2[44]; // + REG32 US_RPR; // Receive Pointer Register + REG32 US_RCR; // Receive Counter Register + REG32 US_TPR; // Transmit Pointer Register + REG32 US_TCR; // Transmit Counter Register + REG32 US_RNPR; // Receive Next Pointer Register + REG32 US_RNCR; // Receive Next Counter Register + REG32 US_TNPR; // Transmit Next Pointer Register + REG32 US_TNCR; // Transmit Next Counter Register + REG32 US_PTCR; // PDC Transfer Control Register + REG32 US_PTSR; // PDC Transfer Status Register }; struct rt_at91serial { - struct rt_device parent; + struct rt_device parent; - struct rt_at91serial_hw* hw_base; - rt_uint16_t peripheral_id; - rt_uint32_t baudrate; + struct rt_at91serial_hw* hw_base; + rt_uint16_t peripheral_id; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 struct rt_at91serial serial1; @@ -72,312 +72,312 @@ struct rt_at91serial serial2; static void rt_hw_serial_isr(int irqno) { - rt_base_t level; - struct rt_device* device; - struct rt_at91serial* serial = RT_NULL; + rt_base_t level; + struct rt_device* device; + struct rt_at91serial* serial = RT_NULL; - if (irqno == AT91C_ID_US0) - { + if (irqno == AT91C_ID_US0) + { #ifdef RT_USING_UART1 - /* serial 1 */ - serial = &serial1; + /* serial 1 */ + serial = &serial1; #endif - } - else if (irqno == AT91C_ID_US1) - { + } + else if (irqno == AT91C_ID_US1) + { #ifdef RT_USING_UART2 - /* serial 2 */ - serial = &serial2; + /* serial 2 */ + serial = &serial2; #endif - } - RT_ASSERT(serial != RT_NULL); + } + RT_ASSERT(serial != RT_NULL); - /* get generic device object */ - device = (rt_device_t)serial; + /* get generic device object */ + device = (rt_device_t)serial; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* get received character */ - serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; + /* get received character */ + serial->rx_buffer[serial->save_index] = serial->hw_base->US_RHR; - /* move to next position */ - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; + /* move to next position */ + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - /* indicate to upper layer application */ - if (device->rx_indicate != RT_NULL) - device->rx_indicate(device, 1); + /* indicate to upper layer application */ + if (device->rx_indicate != RT_NULL) + device->rx_indicate(device, 1); - /* ack interrupt */ - AT91C_AIC_EOICR = 1; + /* ack interrupt */ + AT91C_AIC_EOICR = 1; } static rt_err_t rt_serial_init (rt_device_t dev) { - rt_uint32_t bd; - struct rt_at91serial* serial = (struct rt_at91serial*) dev; + rt_uint32_t bd; + struct rt_at91serial* serial = (struct rt_at91serial*) dev; - RT_ASSERT(serial != RT_NULL); - /* must be US0 or US1 */ - RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) || - (serial->peripheral_id == AT91C_ID_US1))); + RT_ASSERT(serial != RT_NULL); + /* must be US0 or US1 */ + RT_ASSERT(((serial->peripheral_id == AT91C_ID_US0) || + (serial->peripheral_id == AT91C_ID_US1))); - /* Enable Clock for USART */ - AT91C_PMC_PCER = 1 << serial->peripheral_id; + /* Enable Clock for USART */ + AT91C_PMC_PCER = 1 << serial->peripheral_id; - /* Enable RxD0 and TxDO Pin */ - if (serial->peripheral_id == AT91C_ID_US0) - { - /* set pinmux */ - AT91C_PIO_PDR = (1 << 5) | (1 << 6); - } - else if (serial->peripheral_id == AT91C_ID_US1) - { - /* set pinmux */ - AT91C_PIO_PDR = (1 << 21) | (1 << 22); - } + /* Enable RxD0 and TxDO Pin */ + if (serial->peripheral_id == AT91C_ID_US0) + { + /* set pinmux */ + AT91C_PIO_PDR = (1 << 5) | (1 << 6); + } + else if (serial->peripheral_id == AT91C_ID_US1) + { + /* set pinmux */ + AT91C_PIO_PDR = (1 << 21) | (1 << 22); + } - serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ - AT91C_US_RSTTX | /* Reset Transmitter */ - AT91C_US_RXDIS | /* Receiver Disable */ - AT91C_US_TXDIS; /* Transmitter Disable */ + serial->hw_base->US_CR = AT91C_US_RSTRX | /* Reset Receiver */ + AT91C_US_RSTTX | /* Reset Transmitter */ + AT91C_US_RXDIS | /* Receiver Disable */ + AT91C_US_TXDIS; /* Transmitter Disable */ - serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ - AT91C_US_CLKS_CLOCK | /* Clock = MCK */ - AT91C_US_CHRL_8_BITS | /* 8-bit Data */ - AT91C_US_PAR_NONE | /* No Parity */ - AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ + serial->hw_base->US_MR = AT91C_US_USMODE_NORMAL | /* Normal Mode */ + AT91C_US_CLKS_CLOCK | /* Clock = MCK */ + AT91C_US_CHRL_8_BITS | /* 8-bit Data */ + AT91C_US_PAR_NONE | /* No Parity */ + AT91C_US_NBSTOP_1_BIT; /* 1 Stop Bit */ - /* set baud rate divisor */ - bd = ((MCK*10)/(serial->baudrate * 16)); - if ((bd % 10) >= 5) bd = (bd / 10) + 1; - else bd /= 10; + /* set baud rate divisor */ + bd = ((MCK*10)/(serial->baudrate * 16)); + if ((bd % 10) >= 5) bd = (bd / 10) + 1; + else bd /= 10; - serial->hw_base->US_BRGR = bd; - serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ - AT91C_US_TXEN; /* Transmitter Enable */ + serial->hw_base->US_BRGR = bd; + serial->hw_base->US_CR = AT91C_US_RXEN | /* Receiver Enable */ + AT91C_US_TXEN; /* Transmitter Enable */ - /* reset rx index */ - serial->save_index = 0; - serial->read_index = 0; + /* reset rx index */ + serial->save_index = 0; + serial->read_index = 0; - /* reset rx buffer */ - rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); + /* reset rx buffer */ + rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable UART rx interrupt */ - serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ - serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable UART rx interrupt */ + serial->hw_base->US_IER = 1 << 0; /* RxReady interrupt */ + serial->hw_base->US_IMR |= 1 << 0; /* umask RxReady interrupt */ - /* install UART handler */ - rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL); - AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); - rt_hw_interrupt_umask(serial->peripheral_id); - } + /* install UART handler */ + rt_hw_interrupt_install(serial->peripheral_id, rt_hw_serial_isr, RT_NULL); + AT91C_AIC_SMR(serial->peripheral_id) = 5 | (0x01 << 5); + rt_hw_interrupt_umask(serial->peripheral_id); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ - serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + serial->hw_base->US_IDR = 1 << 0; /* RxReady interrupt */ + serial->hw_base->US_IMR &= ~(1 << 0); /* mask RxReady interrupt */ + } - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - ptr ++; size --; - } + ptr ++; size --; + } - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - else - { - /* poll mode */ - while (size) - { - /* Wait for Full Rx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + else + { + /* poll mode */ + while (size) + { + /* Wait for Full Rx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_RXRDY)); - /* Read Character */ - *ptr = serial->hw_base->US_RHR; - ptr ++; - size --; - } + /* Read Character */ + *ptr = serial->hw_base->US_RHR; + ptr ++; + size --; + } - return (rt_size_t)ptr - (rt_size_t)buffer; - } + return (rt_size_t)ptr - (rt_size_t)buffer; + } - return 0; + return 0; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_at91serial *serial = (struct rt_at91serial*)dev; - RT_ASSERT(serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_at91serial *serial = (struct rt_at91serial*)dev; + RT_ASSERT(serial != RT_NULL); - ptr = (rt_uint8_t*) buffer; - if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) - { - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* it's a stream mode device */ - while (size) - { - /* stream mode */ - if (*ptr == '\n') - { - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - serial->hw_base->US_THR = '\r'; - } + ptr = (rt_uint8_t*) buffer; + if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) + { + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* it's a stream mode device */ + while (size) + { + /* stream mode */ + if (*ptr == '\n') + { + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + serial->hw_base->US_THR = '\r'; + } - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; size --; - } - } - else - { - while (size) - { - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); + /* Transmit Character */ + serial->hw_base->US_THR = *ptr; + ptr ++; size --; + } + } + else + { + while (size) + { + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->US_CSR & AT91C_US_TXRDY)); - /* Transmit Character */ - serial->hw_base->US_THR = *ptr; - ptr ++; size --; - } - } - } + /* Transmit Character */ + serial->hw_base->US_THR = *ptr; + ptr ++; size --; + } + } + } - return (rt_size_t)ptr - (rt_size_t)buffer; + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } rt_err_t rt_hw_serial_init() { - rt_device_t device; + rt_device_t device; #ifdef RT_USING_UART1 - device = (rt_device_t) &serial1; + device = (rt_device_t) &serial1; - /* init serial device private data */ - serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; - serial1.peripheral_id = AT91C_ID_US0; - serial1.baudrate = 115200; + /* init serial device private data */ + serial1.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US0; + serial1.peripheral_id = AT91C_ID_US0; + serial1.baudrate = 115200; - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; - /* register uart1 on device subsystem */ - rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + /* register uart1 on device subsystem */ + rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif #ifdef RT_USING_UART2 - device = (rt_device_t) &serial2; + device = (rt_device_t) &serial2; - serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; - serial2.peripheral_id = AT91C_ID_US1; - serial2.baudrate = 115200; + serial2.hw_base = (struct rt_at91serial_hw*)AT91C_BASE_US1; + serial2.peripheral_id = AT91C_ID_US1; + serial2.baudrate = 115200; - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; - /* register uart2 on device subsystem */ - rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + /* register uart2 on device subsystem */ + rt_device_register(device, "uart2", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif - return RT_EOK; + return RT_EOK; } /*@}*/ diff --git a/libcpu/arm/AT91SAM7S/serial.h b/libcpu/arm/AT91SAM7S/serial.h index 0937e92f6c..7766053a7f 100644 --- a/libcpu/arm/AT91SAM7S/serial.h +++ b/libcpu/arm/AT91SAM7S/serial.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,48 +17,48 @@ #define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address #endif -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* US Reset Transmitter */ -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* US Receiver Enable */ -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* US Receiver Disable */ -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* US Transmitter Enable */ -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* US Transmitter Disable */ -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) /* US Reset Status Bits */ +#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) /* US RXRDY Interrupt */ +#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) /* US TXRDY Interrupt */ +#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) /* US Reset Receiver */ +#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) /* US Reset Transmitter */ +#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) /* US Receiver Enable */ +#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) /* US Receiver Disable */ +#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) /* US Transmitter Enable */ +#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) /* US Transmitter Disable */ +#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) /* US Reset Status Bits */ -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) /* USAR) Normal */ -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) /* USAR) RS485 */ -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) /* USAR) Hardware Handshaking */ -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) /* USAR) Modem */ -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) /* USAR) ISO7816 protocol: T = 0 */ -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) /* USAR) ISO7816 protocol: T = 1 */ -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) /* USAR) IrDA */ -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) /* USAR) Software Handshaking */ +#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) /* USAR) Normal */ +#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) /* USAR) RS485 */ +#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) /* USAR) Hardware Handshaking */ +#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) /* USAR) Modem */ +#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) /* USAR) ISO7816 protocol: T = 0 */ +#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) /* USAR) ISO7816 protocol: T = 1 */ +#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) /* USAR) IrDA */ +#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) /* USAR) Software Handshaking */ -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* USAR) Clock */ -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) /* USAR) fdiv1 */ -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) /* USAR) slow_clock (ARM) */ -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) /* USAR) External (SCK) */ +#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) /* USAR) Clock */ +#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) /* USAR) fdiv1 */ +#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) /* USAR) slow_clock (ARM) */ +#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) /* USAR) External (SCK) */ -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) /* USAR) Character Length: 5 bits */ -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) /* USAR) Character Length: 6 bits */ -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) /* USAR) Character Length: 7 bits */ -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* USAR) Character Length: 8 bits */ +#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) /* USAR) Character Length: 5 bits */ +#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) /* USAR) Character Length: 6 bits */ +#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) /* USAR) Character Length: 7 bits */ +#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) /* USAR) Character Length: 8 bits */ -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) /* DBGU Even Parity */ -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) /* DBGU Odd Parity */ -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) /* DBGU Parity forced to 0 (Space) */ -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) /* DBGU Parity forced to 1 (Mark) */ -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* DBGU No Parity */ -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) /* DBGU Multi-drop mode */ +#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) /* DBGU Even Parity */ +#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) /* DBGU Odd Parity */ +#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) /* DBGU Parity forced to 0 (Space) */ +#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) /* DBGU Parity forced to 1 (Mark) */ +#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) /* DBGU No Parity */ +#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) /* DBGU Multi-drop mode */ -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* USART 1 stop bit */ -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) /* USART 2 stop bits */ +#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) /* USART 1 stop bit */ +#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) /* USART Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits */ +#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) /* USART 2 stop bits */ -#define MCK 48054857 -#define BR 115200 /* Baud Rate */ -#define BRD (MCK/16/BR) /* Baud Rate Divisor */ +#define MCK 48054857 +#define BR 115200 /* Baud Rate */ +#define BRD (MCK/16/BR) /* Baud Rate Divisor */ #endif diff --git a/libcpu/arm/AT91SAM7S/stack.c b/libcpu/arm/AT91SAM7S/stack.c index 6f8bd13bf9..23fce8e6e2 100644 --- a/libcpu/arm/AT91SAM7S/stack.c +++ b/libcpu/arm/AT91SAM7S/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/AT91SAM7S/trap.c b/libcpu/arm/AT91SAM7S/trap.c index 208e568950..aa9df7c74b 100644 --- a/libcpu/arm/AT91SAM7S/trap.c +++ b/libcpu/arm/AT91SAM7S/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,12 +20,12 @@ void rt_hw_trap_irq() { - rt_isr_handler_t hander = (rt_isr_handler_t)AT91C_AIC_IVR; + rt_isr_handler_t hander = (rt_isr_handler_t)AT91C_AIC_IVR; - hander(AT91C_AIC_ISR); + hander(AT91C_AIC_ISR); - /* end of interrupt */ - AT91C_AIC_EOICR = 0; + /* end of interrupt */ + AT91C_AIC_EOICR = 0; } void rt_hw_trap_fiq() diff --git a/libcpu/arm/AT91SAM7X/cpu.c b/libcpu/arm/AT91SAM7X/cpu.c index 046f7e8ced..ffa4092900 100644 --- a/libcpu/arm/AT91SAM7X/cpu.c +++ b/libcpu/arm/AT91SAM7X/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/AT91SAM7X/interrupt.c b/libcpu/arm/AT91SAM7X/interrupt.c index 0c37f63ada..3a28f507ca 100644 --- a/libcpu/arm/AT91SAM7X/interrupt.c +++ b/libcpu/arm/AT91SAM7X/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,10 +13,10 @@ #include <rthw.h> #include "AT91SAM7X256.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 /* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; +struct rt_irq_desc irq_desc[MAX_HANDLERS]; extern rt_uint32_t rt_interrupt_nest; @@ -30,7 +30,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -38,7 +38,7 @@ static void rt_hw_interrupt_handler(int vector, void *param) */ void rt_hw_interrupt_init(void) { - rt_base_t index; + rt_base_t index; /* init exceptions table */ for(index=0; index < MAX_HANDLERS; index++) @@ -47,16 +47,16 @@ void rt_hw_interrupt_init(void) irq_desc[index].param = RT_NULL; } - for (index = 0; index < MAX_HANDLERS; index ++) - { - AT91C_BASE_AIC->AIC_SVR[index] = (rt_uint32_t)rt_hw_interrupt_handler; - } + for (index = 0; index < MAX_HANDLERS; index ++) + { + AT91C_BASE_AIC->AIC_SVR[index] = (rt_uint32_t)rt_hw_interrupt_handler; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -65,11 +65,11 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - /* disable interrupt */ - AT91C_BASE_AIC->AIC_IDCR = 1 << vector; + /* disable interrupt */ + AT91C_BASE_AIC->AIC_IDCR = 1 << vector; - /* clear interrupt */ - AT91C_BASE_AIC->AIC_ICCR = 1 << vector; + /* clear interrupt */ + AT91C_BASE_AIC->AIC_ICCR = 1 << vector; } /** @@ -78,7 +78,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - AT91C_BASE_AIC->AIC_IECR = 1 << vector; + AT91C_BASE_AIC->AIC_IECR = 1 << vector; } /** @@ -90,21 +90,21 @@ void rt_hw_interrupt_umask(int vector) * * @return the old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = (rt_isr_handler_t)handler; - irq_desc[vector].param = param; - } - } + rt_isr_handler_t old_handler = RT_NULL; + if(vector >= 0 && vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = (rt_isr_handler_t)handler; + irq_desc[vector].param = param; + } + } - return old_handler; + return old_handler; } /*@}*/ diff --git a/libcpu/arm/AT91SAM7X/stack.c b/libcpu/arm/AT91SAM7X/stack.c index ef60b1a760..caa4826014 100644 --- a/libcpu/arm/AT91SAM7X/stack.c +++ b/libcpu/arm/AT91SAM7X/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/AT91SAM7X/trap.c b/libcpu/arm/AT91SAM7X/trap.c index 1c1c351ff8..3c012dd85e 100644 --- a/libcpu/arm/AT91SAM7X/trap.c +++ b/libcpu/arm/AT91SAM7X/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,17 +20,17 @@ void rt_hw_trap_irq(void) { - int irqno; - extern struct rt_irq_desc irq_desc[]; + int irqno; + extern struct rt_irq_desc irq_desc[]; - /* get interrupt number */ - irqno = AT91C_BASE_AIC->AIC_ISR; + /* get interrupt number */ + irqno = AT91C_BASE_AIC->AIC_ISR; - /* invoke isr with parameters */ - irq_desc[irqno].handler(irqno, irq_desc[irqno].param); + /* invoke isr with parameters */ + irq_desc[irqno].handler(irqno, irq_desc[irqno].param); - /* end of interrupt */ - AT91C_BASE_AIC->AIC_EOICR = 0; + /* end of interrupt */ + AT91C_BASE_AIC->AIC_EOICR = 0; } void rt_hw_trap_fiq(void) @@ -41,9 +41,9 @@ void rt_hw_trap_fiq(void) extern struct rt_thread* rt_current_thread; void rt_hw_trap_abort(void) { - rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name); - rt_thread_suspend(rt_current_thread); - rt_schedule(); + rt_kprintf("Abort occured!!! Thread [%s] suspended.\n",rt_current_thread->name); + rt_thread_suspend(rt_current_thread); + rt_schedule(); } /*@}*/ diff --git a/libcpu/arm/SConscript b/libcpu/arm/SConscript index f6ea13fb91..3d0147658f 100644 --- a/libcpu/arm/SConscript +++ b/libcpu/arm/SConscript @@ -6,11 +6,13 @@ from building import * Import('rtconfig') cwd = GetCurrentDir() +list = os.listdir(cwd) # add common code files group = SConscript(os.path.join('common', 'SConscript')) # cpu porting code files -group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) +if rtconfig.CPU in list: + group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript')) Return('group') diff --git a/libcpu/arm/am335x/am33xx.h b/libcpu/arm/am335x/am33xx.h index 99a65ac915..3112a8ac15 100644 --- a/libcpu/arm/am335x/am33xx.h +++ b/libcpu/arm/am335x/am33xx.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -9,8 +9,8 @@ #ifndef __AM33XX_H__ #define __AM33XX_H__ -#define REG32(x) (*((volatile unsigned int *)(x))) -#define REG16(x) (*((volatile unsigned short *)(x))) +#define REG32(x) (*((volatile unsigned int *)(x))) +#define REG16(x) (*((volatile unsigned short *)(x))) /** Cache Line size in ARM Cortex-A8. */ #define AM33XX_CACHELINE_SIZE (64) @@ -198,22 +198,22 @@ #define CM_DPLL_CLKSEL_TIMER2_CLK(base) REG32(CM_DPLL(base) + 0x8) /* timer registers */ -#define DMTIMER_TIDR(base) REG32(base + 0x0) -#define DMTIMER_TIOCP_CFG(base) REG32(base + 0x10) -#define DMTIMER_IRQ_EOI(base) REG32(base + 0x20) -#define DMTIMER_IRQSTATUS_RAW(base) REG32(base + 0x24) -#define DMTIMER_IRQSTATUS(base) REG32(base + 0x28) -#define DMTIMER_IRQENABLE_SET(base) REG32(base + 0x2C) -#define DMTIMER_IRQENABLE_CLR(base) REG32(base + 0x30) -#define DMTIMER_IRQWAKEEN(base) REG32(base + 0x34) -#define DMTIMER_TCLR(base) REG32(base + 0x38) -#define DMTIMER_TCRR(base) REG32(base + 0x3C) -#define DMTIMER_TLDR(base) REG32(base + 0x40) -#define DMTIMER_TTGR(base) REG32(base + 0x44) -#define DMTIMER_TWPS(base) REG32(base + 0x48) -#define DMTIMER_TMAR(base) REG32(base + 0x4C) -#define DMTIMER_TCAR(base, n) REG32(base + 0x50 + (((n) - 1) * 8)) -#define DMTIMER_TSICR(base) REG32(base + 0x54) +#define DMTIMER_TIDR(base) REG32(base + 0x0) +#define DMTIMER_TIOCP_CFG(base) REG32(base + 0x10) +#define DMTIMER_IRQ_EOI(base) REG32(base + 0x20) +#define DMTIMER_IRQSTATUS_RAW(base) REG32(base + 0x24) +#define DMTIMER_IRQSTATUS(base) REG32(base + 0x28) +#define DMTIMER_IRQENABLE_SET(base) REG32(base + 0x2C) +#define DMTIMER_IRQENABLE_CLR(base) REG32(base + 0x30) +#define DMTIMER_IRQWAKEEN(base) REG32(base + 0x34) +#define DMTIMER_TCLR(base) REG32(base + 0x38) +#define DMTIMER_TCRR(base) REG32(base + 0x3C) +#define DMTIMER_TLDR(base) REG32(base + 0x40) +#define DMTIMER_TTGR(base) REG32(base + 0x44) +#define DMTIMER_TWPS(base) REG32(base + 0x48) +#define DMTIMER_TMAR(base) REG32(base + 0x4C) +#define DMTIMER_TCAR(base, n) REG32(base + 0x50 + (((n) - 1) * 8)) +#define DMTIMER_TSICR(base) REG32(base + 0x54) #define EMU_INT 0 #define COMMTX_INT 1 @@ -317,33 +317,33 @@ struct rt_hw_register { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; }; -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 #endif diff --git a/libcpu/arm/am335x/context_iar.S b/libcpu/arm/am335x/context_iar.S index c53e15a23a..1266d8cf74 100644 --- a/libcpu/arm/am335x/context_iar.S +++ b/libcpu/arm/am335x/context_iar.S @@ -1,21 +1,7 @@ ;/* -; * File : context_iar.S -; * This file is part of RT-Thread RTOS -; * COPYRIGHT (C) 2006, RT-Thread Development Team +; * Copyright (c) 2006-2021, RT-Thread Development Team ; * -; * This program is free software; you can redistribute it and/or modify -; * it under the terms of the GNU General Public License as published by -; * the Free Software Foundation; either version 2 of the License, or -; * (at your option) any later version. -; * -; * This program is distributed in the hope that it will be useful, -; * but WITHOUT ANY WARRANTY; without even the implied warranty of -; * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -; * GNU General Public License for more details. -; * -; * You should have received a copy of the GNU General Public License along -; * with this program; if not, write to the Free Software Foundation, Inc., -; * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. +; * SPDX-License-Identifier: Apache-2.0 ; * ; * Change Logs: ; * Date Author Notes diff --git a/libcpu/arm/am335x/cpu.c b/libcpu/arm/am335x/cpu.c index 469276466b..19161a1817 100644 --- a/libcpu/arm/am335x/cpu.c +++ b/libcpu/arm/am335x/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,74 +17,74 @@ */ /*@{*/ -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) #if defined(__CC_ARM) rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #elif defined(__GNUC__) rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif @@ -96,7 +96,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -105,7 +105,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -114,7 +114,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -123,7 +123,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -132,7 +132,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -141,7 +141,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } #endif @@ -151,14 +151,14 @@ rt_base_t rt_hw_cpu_dcache_status() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/arm/am335x/interrupt.c b/libcpu/arm/am335x/interrupt.c index 3acd868496..c4c5e8d7eb 100644 --- a/libcpu/arm/am335x/interrupt.c +++ b/libcpu/arm/am335x/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ #define AINTC_BASE AM33XX_AINTC_REGS -#define MAX_HANDLERS 128 +#define MAX_HANDLERS 128 extern volatile rt_uint8_t rt_interrupt_nest; @@ -59,13 +59,13 @@ extern int system_vectors; static void rt_hw_vector_init(void) { unsigned int *dest = (unsigned int *)AM335X_VECTOR_BASE; - + #ifdef __ICCARM__ unsigned int *src = (unsigned int *)&__vector; #else unsigned int *src = (unsigned int *)&system_vectors; #endif - + rt_memcpy(dest, src, 16 * 4); rt_cpu_vector_set_base(AM335X_VECTOR_BASE); } diff --git a/libcpu/arm/am335x/interrupt.h b/libcpu/arm/am335x/interrupt.h index 7461f94da0..90f392f407 100644 --- a/libcpu/arm/am335x/interrupt.h +++ b/libcpu/arm/am335x/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,28 +14,28 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) -#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) -#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) -#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) -#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) -#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) -#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) -#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) -#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) -#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) -#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) -#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) -#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) -#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) -#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) -#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) -#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) -#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) -#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) +#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) +#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) +#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) +#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) +#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) +#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) +#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) +#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) +#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) +#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) +#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) +#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) +#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) +#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) +#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) +#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) +#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) +#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) +#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) #define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) #define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) -#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) +#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) void rt_hw_interrupt_control(int vector, int priority, int route); int rt_hw_interrupt_get_active(int fiq_irq); diff --git a/libcpu/arm/am335x/mmu.c b/libcpu/arm/am335x/mmu.c index babe825298..fbd886d0e6 100644 --- a/libcpu/arm/am335x/mmu.c +++ b/libcpu/arm/am335x/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,122 +22,122 @@ extern void rt_cpu_tlb_set(register rt_uint32_t i); void mmu_disable_dcache() { - rt_cpu_dcache_disable(); + rt_cpu_dcache_disable(); } void mmu_enable_dcache() { - rt_hw_cpu_dcache_enable(); + rt_hw_cpu_dcache_enable(); } void mmu_disable_icache() { - rt_cpu_icache_disable(); + rt_cpu_icache_disable(); } void mmu_enable_icache() { - rt_hw_cpu_icache_enable(); + rt_hw_cpu_icache_enable(); } void mmu_disable() { - rt_cpu_mmu_disable(); + rt_cpu_mmu_disable(); } void mmu_enable() { - rt_cpu_mmu_enable(); + rt_cpu_mmu_enable(); } void mmu_setttbase(register rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, * in that case access controlled by permission value * set by page table entry */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - - rt_cpu_tlb_set(i); + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + + rt_cpu_tlb_set(i); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~0x1f; + ptr = buffer & ~0x1f; - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += 32; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += 32; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~0x1f; + ptr = buffer & ~0x1f; - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += 32; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += 32; + } } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } /* level1 page table */ @@ -150,8 +150,8 @@ void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrS nSec=(vaddrEnd>>20)-(vaddrStart>>20); for(i=0;i<=nSec;i++) { - *pTT = attr |(((paddrStart>>20)+i)<<20); - pTT++; + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; } } @@ -161,21 +161,21 @@ RT_WEAK void mmu_setmtts(void) mmu_setmtt(0x00000000, 0xFFFFFFFF, 0x00000000, RW_NCNB); /* None cached for 4G memory */ mmu_setmtt(0x80200000, 0x80800000 - 1, 0x80200000, RW_CB); /* 126M cached DDR memory */ mmu_setmtt(0x80000000, 0x80200000 - 1, 0x80000000, RW_NCNB); /* 2M none-cached DDR memory */ - mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB); /* 63K OnChip memory */ + mmu_setmtt(0x402F0000, 0x40300000 - 1, 0x402F0000, RW_CB); /* 63K OnChip memory */ } void rt_hw_mmu_init(void) { - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); mmu_setmtts(); - /* set MMU table address */ - mmu_setttbase((rt_uint32_t)_page_table); + /* set MMU table address */ + mmu_setttbase((rt_uint32_t)_page_table); /* enables MMU */ mmu_enable(); diff --git a/libcpu/arm/am335x/mmu.h b/libcpu/arm/am335x/mmu.h index 73635d3a0e..706d669844 100644 --- a/libcpu/arm/am335x/mmu.h +++ b/libcpu/arm/am335x/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,27 +13,27 @@ #include <rtthread.h> -#define DESC_SEC (0x2) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO +#define DESC_SEC (0x2) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ void rt_hw_mmu_init(void); diff --git a/libcpu/arm/am335x/stack.c b/libcpu/arm/am335x/stack.c index 1dad930818..db3cb37e73 100644 --- a/libcpu/arm/am335x/stack.c +++ b/libcpu/arm/am335x/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/am335x/trap.c b/libcpu/arm/am335x/trap.c index b77543da64..7c73ce93d3 100644 --- a/libcpu/arm/am335x/trap.c +++ b/libcpu/arm/am335x/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -36,13 +36,13 @@ extern long list_thread(void); void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -62,15 +62,15 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) return; #endif - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -84,10 +84,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -100,15 +100,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -124,29 +124,29 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) #ifdef RT_USING_GDB if (gdb_mem_fault_handler) { - regs->pc = (unsigned long)gdb_mem_fault_handler; + regs->pc = (unsigned long)gdb_mem_fault_handler; return; } #endif - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); + rt_kprintf("data abort\n"); + rt_kprintf("thread %.*s stack:\n", RT_NAME_MAX, rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } void rt_hw_trap_irq() { void *param; - unsigned long ir; + unsigned long ir; rt_isr_handler_t isr_func; extern struct rt_irq_desc isr_table[]; - ir = rt_hw_interrupt_get_active(INT_IRQ); + ir = rt_hw_interrupt_get_active(INT_IRQ); if (ir == 127) { /* new IRQ generation */ @@ -169,18 +169,18 @@ void rt_hw_trap_irq() if (isr_func != RT_NULL) isr_func(ir, param); - /* new IRQ generation */ + /* new IRQ generation */ rt_hw_interrupt_ack(INT_IRQ); } void rt_hw_trap_fiq() { void *param; - unsigned long ir; + unsigned long ir; rt_isr_handler_t isr_func; extern struct rt_irq_desc isr_table[]; - ir = rt_hw_interrupt_get_active(INT_FIQ); + ir = rt_hw_interrupt_get_active(INT_FIQ); /* get interrupt service routine */ isr_func = isr_table[ir].handler; @@ -189,7 +189,7 @@ void rt_hw_trap_fiq() /* turn to interrupt service routine */ isr_func(ir, param); - /* new FIQ generation */ + /* new FIQ generation */ rt_hw_interrupt_ack(INT_FIQ); } diff --git a/libcpu/arm/arm926/cpuport.c b/libcpu/arm/arm926/cpuport.c index dc93f42ed6..9148afa401 100644 --- a/libcpu/arm/arm926/cpuport.c +++ b/libcpu/arm/arm926/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/machine.c b/libcpu/arm/arm926/machine.c index aa26d10ec6..19baa4d9fe 100644 --- a/libcpu/arm/arm926/machine.c +++ b/libcpu/arm/arm926/machine.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/mmu.c b/libcpu/arm/arm926/mmu.c index 19d70b9b0b..50ada17f22 100644 --- a/libcpu/arm/arm926/mmu.c +++ b/libcpu/arm/arm926/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/mmu.h b/libcpu/arm/arm926/mmu.h index 36fdbeacd8..ecd39d4edf 100644 --- a/libcpu/arm/arm926/mmu.h +++ b/libcpu/arm/arm926/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/stack.c b/libcpu/arm/arm926/stack.c index f90bfa8c22..caf16c41bc 100644 --- a/libcpu/arm/arm926/stack.c +++ b/libcpu/arm/arm926/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/arm926/trap.c b/libcpu/arm/arm926/trap.c index 9e7ba48037..c364b2addd 100644 --- a/libcpu/arm/arm926/trap.c +++ b/libcpu/arm/arm926/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/armv6/armv6.h b/libcpu/arm/armv6/armv6.h index 659ce90721..522c35845f 100644 --- a/libcpu/arm/armv6/armv6.h +++ b/libcpu/arm/armv6/armv6.h @@ -1,12 +1,12 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ - + #ifndef __ARMV6_H__ #define __ARMV6_H__ @@ -26,7 +26,7 @@ #ifndef __ASSEMBLY__ struct rt_hw_register { - rt_uint32_t cpsr; + rt_uint32_t cpsr; rt_uint32_t r0; rt_uint32_t r1; rt_uint32_t r2; @@ -46,24 +46,24 @@ struct rt_hw_register }; #if(0) struct rt_hw_register{ - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; #endif #endif diff --git a/libcpu/arm/armv6/cpuport.c b/libcpu/arm/armv6/cpuport.c index f886e7e164..6e82539c6e 100644 --- a/libcpu/arm/armv6/cpuport.c +++ b/libcpu/arm/armv6/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,8 +11,8 @@ #include <rthw.h> #include <rtthread.h> -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) extern void machine_reset(void); extern void machine_shutdown(void); @@ -20,32 +20,32 @@ extern void machine_shutdown(void); #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } @@ -54,38 +54,38 @@ rt_inline void cache_disable(rt_uint32_t bit) #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -95,7 +95,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -104,7 +104,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -113,7 +113,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -122,7 +122,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -131,7 +131,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -140,7 +140,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -149,13 +149,13 @@ rt_base_t rt_hw_cpu_dcache_status() */ RT_WEAK void rt_hw_cpu_reset() { - - rt_kprintf("Restarting system...\n"); - machine_reset(); - while(1); /* loop forever and wait for reset to happen */ + rt_kprintf("Restarting system...\n"); + machine_reset(); - /* NEVER REACHED */ + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ } /** @@ -164,67 +164,67 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - machine_shutdown(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + machine_shutdown(); + while (level) + { + RT_ASSERT(0); + } } #ifdef RT_USING_CPU_FFS /** - * This function finds the first bit set (beginning with the least significant bit) + * This function finds the first bit set (beginning with the least significant bit) * in value and return the index of that bit. * - * Bits are numbered starting at 1 (the least significant bit). A return value of + * Bits are numbered starting at 1 (the least significant bit). A return value of * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function + * + * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ #if defined(__CC_ARM) int __rt_ffs(int value) { - register rt_uint32_t x; + register rt_uint32_t x; + + if (value == 0) + return value; - if (value == 0) - return value; - - __asm - { - rsb x, value, #0 - and x, x, value - clz x, x - rsb x, x, #32 - } + __asm + { + rsb x, value, #0 + and x, x, value + clz x, x + rsb x, x, #32 + } - return x; + return x; } #elif defined(__IAR_SYSTEMS_ICC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - __ASM("RSB r4, r0, #0"); - __ASM("AND r4, r4, r0"); - __ASM("CLZ r4, r4"); - __ASM("RSB r0, r4, #32"); + __ASM("RSB r4, r0, #0"); + __ASM("AND r4, r4, r0"); + __ASM("CLZ r4, r4"); + __ASM("RSB r0, r4, #32"); } #elif defined(__GNUC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - value &= (-value); - asm ("clz %0, %1": "=r"(value) :"r"(value)); + value &= (-value); + asm ("clz %0, %1": "=r"(value) :"r"(value)); - return (32 - value); + return (32 - value); } #endif diff --git a/libcpu/arm/armv6/mmu.c b/libcpu/arm/armv6/mmu.c index ae3cf73559..deb2f8365f 100644 --- a/libcpu/arm/armv6/mmu.c +++ b/libcpu/arm/armv6/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,411 +12,411 @@ #ifdef __CC_ARM void mmu_setttbase(rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - __asm volatile - { - mcr p15, 0, value, c8, c7, 0 - } + /* Invalidates all TLBs.Domain access is selected as + * client by configuring domain access register, + * in that case access controlled by permission value + * set by page table entry + */ + value = 0; + __asm volatile + { + mcr p15, 0, value, c8, c7, 0 + } - value = 0x55555555; - __asm volatile - { - mcr p15, 0, value, c3, c0, 0 - mcr p15, 0, i, c2, c0, 0 - } + value = 0x55555555; + __asm volatile + { + mcr p15, 0, value, c3, c0, 0 + mcr p15, 0, i, c2, c0, 0 + } } void mmu_set_domain(rt_uint32_t i) { - __asm volatile - { - mcr p15,0, i, c3, c0, 0 - } + __asm volatile + { + mcr p15,0, i, c3, c0, 0 + } } void mmu_enable() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x01 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x01 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_enable_icache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_enable_dcache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable_icache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x1000 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x1000 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable_dcache() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x04 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x04 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_enable_alignfault() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_disable_alignfault() { - register rt_uint32_t value; + register rt_uint32_t value; - __asm volatile - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, #0x02 - mcr p15, 0, value, c1, c0, 0 - } + __asm volatile + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, #0x02 + mcr p15, 0, value, c1, c0, 0 + } } void mmu_clean_invalidated_cache_index(int index) { - __asm volatile - { - mcr p15, 0, index, c7, c14, 2 - } + __asm volatile + { + mcr p15, 0, index, c7, c14, 2 + } } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while(ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c14, 1 - } - ptr += CACHE_LINE_SIZE; - } + while(ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c14, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c10, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c10, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c6, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c6, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() { - register rt_uint32_t value; + register rt_uint32_t value; - value = 0; - __asm volatile - { - mcr p15, 0, value, c8, c7, 0 - } + value = 0; + __asm volatile + { + mcr p15, 0, value, c8, c7, 0 + } } void mmu_invalidate_icache() { - register rt_uint32_t value; + register rt_uint32_t value; - value = 0; + value = 0; - __asm volatile - { - mcr p15, 0, value, c7, c5, 0 - } + __asm volatile + { + mcr p15, 0, value, c7, c5, 0 + } } void mmu_invalidate_dcache_all() { - register rt_uint32_t value; + register rt_uint32_t value; - value = 0; + value = 0; - __asm volatile - { - mcr p15, 0, value, c7, c6, 0 - } + __asm volatile + { + mcr p15, 0, value, c7, c6, 0 + } } #elif defined(__GNUC__) void mmu_setttbase(register rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; - /* Invalidates all TLBs.Domain access is selected as - * client by configuring domain access register, - * in that case access controlled by permission value - * set by page table entry - */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + /* Invalidates all TLBs.Domain access is selected as + * client by configuring domain access register, + * in that case access controlled by permission value + * set by page table entry + */ + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= 0x1; - /* Enables the extended page tables to be configured for - the hardware page translation mechanism, Subpage AP bits disabled */ - i |= (1 << 23); /* support for ARMv6 MMU features */ - i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ + i |= 0x1; + /* Enables the extended page tables to be configured for + the hardware page translation mechanism, Subpage AP bits disabled */ + i |= (1 << 23); /* support for ARMv6 MMU features */ + i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1; + i &= ~0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 12); + i |= (1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 2); + i |= (1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 12); + i &= ~(1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 2); + i &= ~(1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while(ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while(ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } void mmu_invalidate_dcache_all() { - asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c6, 0": :"r" (0)); } #endif @@ -426,123 +426,123 @@ static volatile unsigned int _pgd_table[4*1024] ALIGN(16*1024); * level2 page table * RT_MMU_PTE_SIZE must be 1024*n */ -#define RT_MMU_PTE_SIZE 4096 +#define RT_MMU_PTE_SIZE 4096 static volatile unsigned int _pte_table[RT_MMU_PTE_SIZE] ALIGN(1*1024); void mmu_create_pgd(struct mem_desc *mdesc) { - volatile rt_uint32_t *pTT; - volatile int i, nSec; - pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20); - nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20); - for(i = 0; i <= nSec; i++) - { - *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20); - pTT++; - } + volatile rt_uint32_t *pTT; + volatile int i, nSec; + pTT = (rt_uint32_t *)_pgd_table + (mdesc->vaddr_start >> 20); + nSec = (mdesc->vaddr_end >> 20) - (mdesc->vaddr_start >> 20); + for(i = 0; i <= nSec; i++) + { + *pTT = mdesc->sect_attr | (((mdesc->paddr_start >> 20) + i) << 20); + pTT++; + } } void mmu_create_pte(struct mem_desc *mdesc) { - volatile rt_uint32_t *pTT; - volatile rt_uint32_t *p_pteentry; - int i; - rt_uint32_t vaddr; - rt_uint32_t total_page = 0; - rt_uint32_t pte_offset = 0; - rt_uint32_t sect_attr = 0; + volatile rt_uint32_t *pTT; + volatile rt_uint32_t *p_pteentry; + int i; + rt_uint32_t vaddr; + rt_uint32_t total_page = 0; + rt_uint32_t pte_offset = 0; + rt_uint32_t sect_attr = 0; - total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1; - pte_offset = mdesc->sect_attr & 0xfffffc00; - sect_attr = mdesc->sect_attr & 0x3ff; - vaddr = mdesc->vaddr_start; + total_page = (mdesc->vaddr_end >> 12) - (mdesc->vaddr_start >> 12) + 1; + pte_offset = mdesc->sect_attr & 0xfffffc00; + sect_attr = mdesc->sect_attr & 0x3ff; + vaddr = mdesc->vaddr_start; - for(i = 0; i < total_page; i++) - { - pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20); - if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ - { - *pTT = pte_offset | sect_attr; - p_pteentry = (rt_uint32_t *)pte_offset + - ((vaddr & 0x000ff000) >> 12); - pte_offset += 1024; - } - else /* using old Level 1 page table item */ - { - p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + - ((vaddr & 0x000ff000) >> 12); - } + for(i = 0; i < total_page; i++) + { + pTT = (rt_uint32_t *)_pgd_table + (vaddr >> 20); + if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ + { + *pTT = pte_offset | sect_attr; + p_pteentry = (rt_uint32_t *)pte_offset + + ((vaddr & 0x000ff000) >> 12); + pte_offset += 1024; + } + else /* using old Level 1 page table item */ + { + p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + + ((vaddr & 0x000ff000) >> 12); + } - *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12); - vaddr += 0x1000; - } + *p_pteentry = mdesc->page_attr | (((mdesc->paddr_start >> 12) + i) << 12); + vaddr += 0x1000; + } } static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size) { - rt_uint32_t pte_offset = 0; - rt_uint32_t nsec = 0; - /* set page table */ - for (; size > 0; size--) - { - if (mdesc->mapped_mode == PAGE_MAPPED) - { - nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20; - mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset; - pte_offset += nsec << 10; - } - if (pte_offset >= RT_MMU_PTE_SIZE) - { - rt_kprintf("PTE table size too little\n"); - RT_ASSERT(0); - } + rt_uint32_t pte_offset = 0; + rt_uint32_t nsec = 0; + /* set page table */ + for (; size > 0; size--) + { + if (mdesc->mapped_mode == PAGE_MAPPED) + { + nsec = (RT_ALIGN(mdesc->vaddr_end, 0x100000) - RT_ALIGN_DOWN(mdesc->vaddr_start, 0x100000)) >> 20; + mdesc->sect_attr |= (((rt_uint32_t)_pte_table)& 0xfffffc00) + pte_offset; + pte_offset += nsec << 10; + } + if (pte_offset >= RT_MMU_PTE_SIZE) + { + rt_kprintf("PTE table size too little\n"); + RT_ASSERT(0); + } - mdesc++; - } + mdesc++; + } } void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) { - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); - /* clear pgd and pte table */ - rt_memset((void *)_pgd_table, 0, 16*1024); - rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); - build_pte_mem_desc(mdesc, size); - /* set page table */ - for (; size > 0; size--) - { - if (mdesc->mapped_mode == SECT_MAPPED) - { - mmu_create_pgd(mdesc); - } - else - { - mmu_create_pte(mdesc); - } + /* clear pgd and pte table */ + rt_memset((void *)_pgd_table, 0, 16*1024); + rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); + build_pte_mem_desc(mdesc, size); + /* set page table */ + for (; size > 0; size--) + { + if (mdesc->mapped_mode == SECT_MAPPED) + { + mmu_create_pgd(mdesc); + } + else + { + mmu_create_pte(mdesc); + } - mdesc++; - } + mdesc++; + } - /* set MMU table address */ - mmu_setttbase((rt_uint32_t)_pgd_table); + /* set MMU table address */ + mmu_setttbase((rt_uint32_t)_pgd_table); - /* enables MMU */ - mmu_enable(); + /* enables MMU */ + mmu_enable(); - /* enable Instruction Cache */ - mmu_enable_icache(); + /* enable Instruction Cache */ + mmu_enable_icache(); - /* enable Data Cache */ - mmu_enable_dcache(); + /* enable Data Cache */ + mmu_enable_dcache(); - mmu_invalidate_icache(); - mmu_invalidate_dcache_all(); + mmu_invalidate_icache(); + mmu_invalidate_dcache_all(); } diff --git a/libcpu/arm/armv6/mmu.h b/libcpu/arm/armv6/mmu.h index 4df61ac21d..18355378bd 100644 --- a/libcpu/arm/armv6/mmu.h +++ b/libcpu/arm/armv6/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ #include <rtthread.h> -#define CACHE_LINE_SIZE 32 +#define CACHE_LINE_SIZE 32 /* * Hardware page table definitions. @@ -30,7 +30,7 @@ /* * - section */ -#define PGD_SECT_BUFFERABLE (1 << 2) +#define PGD_SECT_BUFFERABLE (1 << 2) #define PGD_SECT_CACHEABLE (1 << 3) #define PGD_SECT_XN (1 << 4) /* ARMv6 */ #define PGD_SECT_AP0 (1 << 10) @@ -155,35 +155,35 @@ #define PAGE_RONX_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL|PTE_EXT_XN) /* Read Only without cache and write buffer */ -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) /* Read/Write, cache, write back */ +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) /* Read/Write, cache, write through */ +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) /* Read/Write without cache and write buffer */ struct mem_desc { - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t sect_attr; /* when page mapped */ - rt_uint32_t page_attr; /* only sector mapped valid */ - rt_uint32_t mapped_mode; + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t sect_attr; /* when page mapped */ + rt_uint32_t page_attr; /* only sector mapped valid */ + rt_uint32_t mapped_mode; #define SECT_MAPPED 0 #define PAGE_MAPPED 1 }; diff --git a/libcpu/arm/armv6/stack.c b/libcpu/arm/armv6/stack.c index 52de999fc2..33a8d96d48 100644 --- a/libcpu/arm/armv6/stack.c +++ b/libcpu/arm/armv6/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/armv6/vfp.c b/libcpu/arm/armv6/vfp.c index 9aa8d34fcc..fc07f5a309 100644 --- a/libcpu/arm/armv6/vfp.c +++ b/libcpu/arm/armv6/vfp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/armv6/vfp.h b/libcpu/arm/armv6/vfp.h index c347dbe0a6..fd084f3aef 100644 --- a/libcpu/arm/armv6/vfp.h +++ b/libcpu/arm/armv6/vfp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -87,7 +87,7 @@ }) #define vmsr(vfp, var) \ - asm("vmsr "#vfp", %0" \ + asm("vmsr "#vfp", %0" \ : : "r" (var) : "cc") diff --git a/libcpu/arm/common/backtrace.c b/libcpu/arm/common/backtrace.c index 4fc87b20d1..388a409d88 100644 --- a/libcpu/arm/common/backtrace.c +++ b/libcpu/arm/common/backtrace.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/common/div0.c b/libcpu/arm/common/div0.c index 0cb3e09b54..113778b43f 100644 --- a/libcpu/arm/common/div0.c +++ b/libcpu/arm/common/div0.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -8,5 +8,5 @@ */ void __div0 (void) { - while (1) ; + while (1) ; } diff --git a/libcpu/arm/common/showmem.c b/libcpu/arm/common/showmem.c index b770e4ce17..1a94ff1d9f 100644 --- a/libcpu/arm/common/showmem.c +++ b/libcpu/arm/common/showmem.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,27 +12,27 @@ void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) { - int i = 0, j =0; + int i = 0, j =0; - RT_ASSERT(addr); + RT_ASSERT(addr); - addr = addr & ~0xF; - size = 4*((size + 3)/4); + addr = addr & ~0xF; + size = 4*((size + 3)/4); - while(i < size) - { - rt_kprintf("0x%08x: ", addr ); + while(i < size) + { + rt_kprintf("0x%08x: ", addr ); - for(j=0; j<4; j++) - { - rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); + for(j=0; j<4; j++) + { + rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); - addr += 4; - i++; - } + addr += 4; + i++; + } - rt_kprintf("\n"); - } + rt_kprintf("\n"); + } - return; + return; } diff --git a/libcpu/arm/cortex-a/armv7.h b/libcpu/arm/cortex-a/armv7.h index d22f72fa68..f284bb5255 100644 --- a/libcpu/arm/cortex-a/armv7.h +++ b/libcpu/arm/cortex-a/armv7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,43 +12,43 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; struct rt_hw_stack { - unsigned long cpsr; - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long lr; - unsigned long pc; + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; }; #define USERMODE 0x10 diff --git a/libcpu/arm/cortex-a/cache.c b/libcpu/arm/cortex-a/cache.c index 30af86baa1..0a7e702dbb 100644 --- a/libcpu/arm/cortex-a/cache.c +++ b/libcpu/arm/cortex-a/cache.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2019-03-29 quanzhao the first version + * 2019-03-29 quanzhao the first version */ #include <rthw.h> #include <rtdef.h> diff --git a/libcpu/arm/cortex-a/cp15.h b/libcpu/arm/cortex-a/cp15.h index 97c5b93ad2..687199e573 100644 --- a/libcpu/arm/cortex-a/cp15.h +++ b/libcpu/arm/cortex-a/cp15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/cpu.c b/libcpu/arm/cortex-a/cpu.c index 6775b781bc..9555e01e9c 100644 --- a/libcpu/arm/cortex-a/cpu.c +++ b/libcpu/arm/cortex-a/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/gic.c b/libcpu/arm/cortex-a/gic.c index 2e94b88277..faad418b2d 100644 --- a/libcpu/arm/cortex-a/gic.c +++ b/libcpu/arm/cortex-a/gic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/gic.h b/libcpu/arm/cortex-a/gic.h index a16d0467fb..e48f9f854d 100644 --- a/libcpu/arm/cortex-a/gic.h +++ b/libcpu/arm/cortex-a/gic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/interrupt.c b/libcpu/arm/cortex-a/interrupt.c index b7a70719a9..0d440d1d0e 100644 --- a/libcpu/arm/cortex-a/interrupt.c +++ b/libcpu/arm/cortex-a/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/interrupt.h b/libcpu/arm/cortex-a/interrupt.h index 442187edee..a8a9afb95c 100644 --- a/libcpu/arm/cortex-a/interrupt.h +++ b/libcpu/arm/cortex-a/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/mmu.c b/libcpu/arm/cortex-a/mmu.c index 1260f41fe5..243fe19a0a 100644 --- a/libcpu/arm/cortex-a/mmu.c +++ b/libcpu/arm/cortex-a/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/mmu.h b/libcpu/arm/cortex-a/mmu.h index fbce6df935..5cc60a774d 100644 --- a/libcpu/arm/cortex-a/mmu.h +++ b/libcpu/arm/cortex-a/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/pmu.c b/libcpu/arm/cortex-a/pmu.c index 8ffc1dede6..2b9165cc8b 100644 --- a/libcpu/arm/cortex-a/pmu.c +++ b/libcpu/arm/cortex-a/pmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/pmu.h b/libcpu/arm/cortex-a/pmu.h index fb8390133d..64a74b5d39 100644 --- a/libcpu/arm/cortex-a/pmu.h +++ b/libcpu/arm/cortex-a/pmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/stack.c b/libcpu/arm/cortex-a/stack.c index 07d795ab5b..e68b324867 100644 --- a/libcpu/arm/cortex-a/stack.c +++ b/libcpu/arm/cortex-a/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-a/trap.c b/libcpu/arm/cortex-a/trap.c index dc232a46ee..a213e776c7 100644 --- a/libcpu/arm/cortex-a/trap.c +++ b/libcpu/arm/cortex-a/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m0/cpuport.c b/libcpu/arm/cortex-m0/cpuport.c index 19aec42230..49e15bf339 100644 --- a/libcpu/arm/cortex-m0/cpuport.c +++ b/libcpu/arm/cortex-m0/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m23/cpuport.c b/libcpu/arm/cortex-m23/cpuport.c index 842802c866..d8f9b12c2c 100644 --- a/libcpu/arm/cortex-m23/cpuport.c +++ b/libcpu/arm/cortex-m23/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c index b6c4c9743c..19c33bd7c9 100644 --- a/libcpu/arm/cortex-m3/cpuport.c +++ b/libcpu/arm/cortex-m3/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-m33/cpuport.c b/libcpu/arm/cortex-m33/cpuport.c index 42b5798507..928689d9c8 100644 --- a/libcpu/arm/cortex-m33/cpuport.c +++ b/libcpu/arm/cortex-m33/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -457,7 +457,7 @@ RT_WEAK void rt_hw_cpu_reset(void) * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ -#if defined(__CC_ARM) +#if defined(__CC_ARM) __asm int __rt_ffs(int value) { CMP r0, #0x00 @@ -473,17 +473,13 @@ exit #elif defined(__CLANG_ARM) int __rt_ffs(int value) { - __asm volatile( - "CMP r0, #0x00 \n" - "BEQ 1f \n" + if (value == 0) return value; + __asm volatile( "RBIT r0, r0 \n" "CLZ r0, r0 \n" "ADDS r0, r0, #0x01 \n" - "1: \n" - "BX lr \n" - : "=r"(value) : "r"(value) ); diff --git a/libcpu/arm/cortex-m33/trustzone.c b/libcpu/arm/cortex-m33/trustzone.c index 86654a7199..f49f0c24f8 100644 --- a/libcpu/arm/cortex-m33/trustzone.c +++ b/libcpu/arm/cortex-m33/trustzone.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,11 +10,19 @@ #include <rtthread.h> +#ifdef ARM_CM33_ENABLE_TRUSTZONE extern void TZ_InitContextSystem_S(void); extern rt_uint32_t TZ_AllocModuleContext_S (rt_uint32_t module); extern rt_uint32_t TZ_FreeModuleContext_S(rt_uint32_t id); extern rt_uint32_t TZ_LoadContext_S(rt_uint32_t id); extern rt_uint32_t TZ_StoreContext_S(rt_uint32_t id); +#else +void TZ_InitContextSystem_S(void){} +rt_uint32_t TZ_AllocModuleContext_S (rt_uint32_t module){return 0;} +rt_uint32_t TZ_FreeModuleContext_S(rt_uint32_t id) {return 0;} +rt_uint32_t TZ_LoadContext_S(rt_uint32_t id){return 0;}; +rt_uint32_t TZ_StoreContext_S(rt_uint32_t id){return 0;}; +#endif extern int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); #define TZ_INIT_CONTEXT_ID (0x1001) @@ -23,7 +31,7 @@ extern int tzcall(int id, rt_ubase_t arg0, rt_ubase_t arg1, rt_ubase_t arg2); rt_ubase_t rt_trustzone_current_context; -#if defined(__CC_ARM) +#if defined(__CC_ARM) static __inline rt_uint32_t __get_IPSR(void) { register rt_uint32_t result __asm("ipsr"); @@ -70,7 +78,7 @@ rt_err_t rt_trustzone_enter(rt_ubase_t module) rt_trustzone_init(); if (tzcall(TZ_ALLOC_CONTEXT_ID, module, 0, 0)) { - return RT_EOK; + return RT_EOK; } return -RT_ERROR; } diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c index 2e47832259..dbc42d21cf 100644 --- a/libcpu/arm/cortex-m4/cpuport.c +++ b/libcpu/arm/cortex-m4/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -454,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void) * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ -#if defined(__CC_ARM) +#if defined(__CC_ARM) __asm int __rt_ffs(int value) { CMP r0, #0x00 diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c index 350b819c00..417558e285 100644 --- a/libcpu/arm/cortex-m7/cpu_cache.c +++ b/libcpu/arm/cortex-m7/cpu_cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #include <rtdef.h> #include <board.h> -/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ +/* The L1-caches on all Cortex®-M7s are divided into lines of 32 bytes. */ #define L1CACHE_LINESIZE_BYTE (32) void rt_hw_cpu_icache_enable(void) diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c index aeb9f14ac5..dbc42d21cf 100644 --- a/libcpu/arm/cortex-m7/cpuport.c +++ b/libcpu/arm/cortex-m7/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-r4/armv7.h b/libcpu/arm/cortex-r4/armv7.h index 3adcb92c5d..d29b41a213 100644 --- a/libcpu/arm/cortex-r4/armv7.h +++ b/libcpu/arm/cortex-r4/armv7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -16,23 +16,23 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; #define USERMODE 0x10 diff --git a/libcpu/arm/cortex-r4/cpu.c b/libcpu/arm/cortex-r4/cpu.c index 23c16e383c..dd82ef1cf4 100644 --- a/libcpu/arm/cortex-r4/cpu.c +++ b/libcpu/arm/cortex-r4/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,22 +30,22 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } #ifdef __TI_COMPILER_VERSION__ #ifdef RT_USING_CPU_FFS int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - __asm(" rsb r1, r0, #0"); - __asm(" and r1, r1, r0"); - __asm(" clz r1, r1"); - __asm(" rsb r0, r1, #32"); + __asm(" rsb r1, r0, #0"); + __asm(" and r1, r1, r0"); + __asm(" clz r1, r1"); + __asm(" rsb r0, r1, #32"); } #endif diff --git a/libcpu/arm/cortex-r4/interrupt.c b/libcpu/arm/cortex-r4/interrupt.c index 30e14f5a2d..14a9023921 100644 --- a/libcpu/arm/cortex-r4/interrupt.c +++ b/libcpu/arm/cortex-r4/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,7 +17,7 @@ #include "armv7.h" -#define MAX_HANDLERS 96 +#define MAX_HANDLERS 96 /* exception and interrupt handler table */ struct rt_irq_desc irq_desc[MAX_HANDLERS]; @@ -36,16 +36,16 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_int_not_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } #define vimRAM (0xFFF82000U) void rt_hw_interrupt_init(void) { - register int i; + register int i; - rt_uint32_t *vect_addr; + rt_uint32_t *vect_addr; /* the initialization is done in sys_startup.c */ @@ -55,15 +55,15 @@ void rt_hw_interrupt_init(void) { irq_desc[i].handler = rt_hw_int_not_handle; - vect_addr = (rt_uint32_t *)(vimRAM + i*4); - *vect_addr = (rt_uint32_t)&irq_desc[i]; + vect_addr = (rt_uint32_t *)(vimRAM + i*4); + *vect_addr = (rt_uint32_t)&irq_desc[i]; } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } void rt_hw_interrupt_mask(int vector) @@ -86,21 +86,21 @@ void rt_hw_interrupt_umask(int vector) * @return the old handler */ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; + rt_isr_handler_t old_handler = RT_NULL; - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = handler; + irq_desc[vector].param = param; + } + } - return old_handler; + return old_handler; } /*@}*/ diff --git a/libcpu/arm/cortex-r4/stack.c b/libcpu/arm/cortex-r4/stack.c index 612cde3bfb..539b47d3d2 100644 --- a/libcpu/arm/cortex-r4/stack.c +++ b/libcpu/arm/cortex-r4/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/cortex-r4/trap.c b/libcpu/arm/cortex-r4/trap.c index d50ad06538..e6c62390c1 100644 --- a/libcpu/arm/cortex-r4/trap.c +++ b/libcpu/arm/cortex-r4/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -28,13 +28,13 @@ */ void rt_hw_show_register (struct rt_hw_exp_stack *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -49,8 +49,8 @@ void rt_hw_trap_udef(struct rt_hw_exp_stack *regs) { rt_kprintf("undefined instruction\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -68,7 +68,7 @@ void rt_hw_trap_svc(struct rt_hw_exp_stack *regs) rt_kprintf("software interrupt\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -86,7 +86,7 @@ void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) rt_kprintf("prefetch abort\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -104,7 +104,7 @@ void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) rt_kprintf("Data Abort "); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -121,7 +121,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) rt_kprintf("Reserved trap\n"); rt_hw_show_register(regs); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif rt_hw_cpu_shutdown(); } @@ -129,15 +129,15 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq(void) { - int irqno; - struct rt_irq_desc* irq; - extern struct rt_irq_desc irq_desc[]; + int irqno; + struct rt_irq_desc* irq; + extern struct rt_irq_desc irq_desc[]; - irq = (struct rt_irq_desc*) vimREG->IRQVECREG; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); + irq = (struct rt_irq_desc*) vimREG->IRQVECREG; + irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - /* invoke isr */ - irq->handler(irqno, irq->param); + /* invoke isr */ + irq->handler(irqno, irq->param); } void rt_hw_trap_fiq(void) diff --git a/libcpu/arm/dm36x/cpuport.c b/libcpu/arm/dm36x/cpuport.c index 99edb96260..435ca2f15f 100644 --- a/libcpu/arm/dm36x/cpuport.c +++ b/libcpu/arm/dm36x/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,8 +11,8 @@ #include <rthw.h> #include <rtthread.h> -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) extern void machine_reset(void); extern void machine_shutdown(void); @@ -20,70 +20,70 @@ extern void machine_shutdown(void); #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -93,7 +93,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -102,7 +102,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -111,7 +111,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -120,7 +120,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -129,7 +129,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -138,7 +138,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -147,13 +147,13 @@ rt_base_t rt_hw_cpu_dcache_status() */ RT_WEAK void rt_hw_cpu_reset() { - - rt_kprintf("Restarting system...\n"); - machine_reset(); - while(1); /* loop forever and wait for reset to happen */ + rt_kprintf("Restarting system...\n"); + machine_reset(); - /* NEVER REACHED */ + while(1); /* loop forever and wait for reset to happen */ + + /* NEVER REACHED */ } /** @@ -162,67 +162,67 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - machine_shutdown(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + machine_shutdown(); + while (level) + { + RT_ASSERT(0); + } } #ifdef RT_USING_CPU_FFS /** - * This function finds the first bit set (beginning with the least significant bit) + * This function finds the first bit set (beginning with the least significant bit) * in value and return the index of that bit. * - * Bits are numbered starting at 1 (the least significant bit). A return value of + * Bits are numbered starting at 1 (the least significant bit). A return value of * zero from any of these functions means that the argument was zero. - * - * @return return the index of the first bit set. If value is 0, then this function + * + * @return return the index of the first bit set. If value is 0, then this function * shall return 0. */ #if defined(__CC_ARM) int __rt_ffs(int value) { - register rt_uint32_t x; + register rt_uint32_t x; + + if (value == 0) + return value; - if (value == 0) - return value; - - __asm - { - rsb x, value, #0 - and x, x, value - clz x, x - rsb x, x, #32 - } + __asm + { + rsb x, value, #0 + and x, x, value + clz x, x + rsb x, x, #32 + } - return x; + return x; } #elif defined(__IAR_SYSTEMS_ICC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - __ASM("RSB r4, r0, #0"); - __ASM("AND r4, r4, r0"); - __ASM("CLZ r4, r4"); - __ASM("RSB r0, r4, #32"); + __ASM("RSB r4, r0, #0"); + __ASM("AND r4, r4, r0"); + __ASM("CLZ r4, r4"); + __ASM("RSB r0, r4, #32"); } #elif defined(__GNUC__) int __rt_ffs(int value) { - if (value == 0) - return value; + if (value == 0) + return value; - value &= (-value); - asm ("clz %0, %1": "=r"(value) :"r"(value)); + value &= (-value); + asm ("clz %0, %1": "=r"(value) :"r"(value)); - return (32 - value); + return (32 - value); } #endif diff --git a/libcpu/arm/dm36x/mmu.c b/libcpu/arm/dm36x/mmu.c index abb2c1cd9e..bec2e6a71c 100644 --- a/libcpu/arm/dm36x/mmu.c +++ b/libcpu/arm/dm36x/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,22 +12,22 @@ #ifdef __CC_ARM void mmu_setttbase(rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, * in that case access controlled by permission value * set by page table entry */ - value = 0; + value = 0; __asm volatile { mcr p15, 0, value, c8, c7, 0 - } + } - value = 0x55555555; - __asm volatile - { + value = 0x55555555; + __asm volatile + { mcr p15, 0, value, c3, c0, 0 mcr p15, 0, i, c2, c0, 0 } @@ -153,44 +153,44 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) while(ptr < buffer + size) { - __asm volatile - { - MCR p15, 0, ptr, c7, c14, 1 - } + __asm volatile + { + MCR p15, 0, ptr, c7, c14, 1 + } ptr += CACHE_LINE_SIZE; } } void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c10, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c10, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - __asm volatile - { - MCR p15, 0, ptr, c7, c6, 1 - } - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + __asm volatile + { + MCR p15, 0, ptr, c7, c6, 1 + } + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() @@ -231,137 +231,137 @@ void mmu_invalidate_dcache_all() #elif defined(__GNUC__) void mmu_setttbase(register rt_uint32_t i) { - register rt_uint32_t value; + register rt_uint32_t value; /* Invalidates all TLBs.Domain access is selected as * client by configuring domain access register, * in that case access controlled by permission value * set by page table entry */ - value = 0; - asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); + value = 0; + asm volatile ("mcr p15, 0, %0, c8, c7, 0"::"r"(value)); - value = 0x55555555; - asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); - asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); + value = 0x55555555; + asm volatile ("mcr p15, 0, %0, c3, c0, 0"::"r"(value)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0"::"r"(i)); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= 0x1; - i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ - /* S R bit=1 0 for system protection */ - i |= (1 << 8); - i &= ~(1 << 9); + i |= 0x1; + i |= (1 << 13); /* High exception vectors selected, address range = 0xFFFF0000-0xFFFF001C */ + /* S R bit=1 0 for system protection */ + i |= (1 << 8); + i &= ~(1 << 9); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1; + i &= ~0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 12); + i |= (1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 2); + i |= (1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 12); + i &= ~(1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 2); + i &= ~(1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) @@ -372,7 +372,7 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) while(ptr < buffer + size) { - asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); + asm volatile ("mcr p15, 0, %0, c7, c14, 1": :"r" (ptr)); ptr += CACHE_LINE_SIZE; } } @@ -380,38 +380,38 @@ void mmu_clean_invalidated_dcache(rt_uint32_t buffer, rt_uint32_t size) void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c10, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size) { - unsigned int ptr; + unsigned int ptr; - ptr = buffer & ~(CACHE_LINE_SIZE - 1); + ptr = buffer & ~(CACHE_LINE_SIZE - 1); - while (ptr < buffer + size) - { - asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); - ptr += CACHE_LINE_SIZE; - } + while (ptr < buffer + size) + { + asm volatile ("mcr p15, 0, %0, c7, c6, 1": :"r" (ptr)); + ptr += CACHE_LINE_SIZE; + } } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } void mmu_invalidate_dcache_all() @@ -462,13 +462,13 @@ void mmu_create_pte(struct mem_desc *mdesc) if (*pTT == 0) /* Level 1 page table item not used, now update pgd item */ { *pTT = pte_offset | sect_attr; - p_pteentry = (rt_uint32_t *)pte_offset + + p_pteentry = (rt_uint32_t *)pte_offset + ((vaddr & 0x000ff000) >> 12); pte_offset += 1024; } else /* using old Level 1 page table item */ { - p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + + p_pteentry = (rt_uint32_t *)(*pTT & 0xfffffc00) + ((vaddr & 0x000ff000) >> 12); } @@ -503,13 +503,13 @@ static void build_pte_mem_desc(struct mem_desc *mdesc, rt_uint32_t size) void rt_hw_mmu_init(struct mem_desc *mdesc, rt_uint32_t size) { - /* disable I/D cache */ - mmu_disable_dcache(); - mmu_disable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + /* disable I/D cache */ + mmu_disable_dcache(); + mmu_disable_icache(); + mmu_disable(); + mmu_invalidate_tlb(); - /* clear pgd and pte table */ + /* clear pgd and pte table */ rt_memset((void *)_pgd_table, 0, 16*1024); rt_memset((void *)_pte_table, 0, RT_MMU_PTE_SIZE); build_pte_mem_desc(mdesc, size); diff --git a/libcpu/arm/dm36x/mmu.h b/libcpu/arm/dm36x/mmu.h index 3410b881ac..60a4e3c6e9 100644 --- a/libcpu/arm/dm36x/mmu.h +++ b/libcpu/arm/dm36x/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,7 +12,7 @@ #include <rtthread.h> -#define CACHE_LINE_SIZE 32 +#define CACHE_LINE_SIZE 32 /* * Hardware page table definitions. @@ -30,7 +30,7 @@ /* * - section */ -#define PGD_SECT_BUFFERABLE (1 << 2) +#define PGD_SECT_BUFFERABLE (1 << 2) #define PGD_SECT_CACHEABLE (1 << 3) #define PGD_SECT_XN (1 << 4) /* ARMv6 */ #define PGD_SECT_AP0 (1 << 10) @@ -133,14 +133,14 @@ #define PAGE_RO_FAULT (PAGE_AP_RO|PTE_TYPE_SMALL) /* Read Only without cache and write buffer */ struct mem_desc { - rt_uint32_t vaddr_start; - rt_uint32_t vaddr_end; - rt_uint32_t paddr_start; - rt_uint32_t sect_attr; /* when page mapped */ - rt_uint32_t page_attr; /* only sector mapped valid */ - rt_uint32_t mapped_mode; - #define SECT_MAPPED 0 - #define PAGE_MAPPED 1 + rt_uint32_t vaddr_start; + rt_uint32_t vaddr_end; + rt_uint32_t paddr_start; + rt_uint32_t sect_attr; /* when page mapped */ + rt_uint32_t page_attr; /* only sector mapped valid */ + rt_uint32_t mapped_mode; + #define SECT_MAPPED 0 + #define PAGE_MAPPED 1 }; diff --git a/libcpu/arm/dm36x/stack.c b/libcpu/arm/dm36x/stack.c index 9d7385b9c8..e725d060c1 100644 --- a/libcpu/arm/dm36x/stack.c +++ b/libcpu/arm/dm36x/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/lpc214x/cpuport.c b/libcpu/arm/lpc214x/cpuport.c index 54e7e9b0c8..a1f594dcb9 100644 --- a/libcpu/arm/lpc214x/cpuport.c +++ b/libcpu/arm/lpc214x/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,13 +13,13 @@ #include <rthw.h> #include "lpc214x.h" -#define MAX_HANDLERS 32 -#define SVCMODE 0x13 +#define MAX_HANDLERS 32 +#define SVCMODE 0x13 extern rt_uint32_t rt_interrupt_nest; /* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; +struct rt_irq_desc irq_desc[MAX_HANDLERS]; /** * @addtogroup LPC214x @@ -37,35 +37,35 @@ struct rt_irq_desc irq_desc[MAX_HANDLERS]; * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - *(stk) = (unsigned long)tentry; /* entry point */ - *(--stk) = (unsigned long)texit; /* lr */ - *(--stk) = 0; /* r12 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r8 */ - *(--stk) = 0; /* r7 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r1 */ - *(--stk) = (unsigned long)parameter; /* r0 : argument */ + stk = (unsigned long *)stack_addr; + *(stk) = (unsigned long)tentry; /* entry point */ + *(--stk) = (unsigned long)texit; /* lr */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (unsigned long)parameter; /* r0 : argument */ - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ + /* cpsr */ + if ((rt_uint32_t)tentry & 0x01) + *(--stk) = SVCMODE | 0x20; /* thumb mode */ + else + *(--stk) = SVCMODE; /* arm mode */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /* exception and interrupt handler table */ @@ -74,7 +74,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -82,32 +82,32 @@ void rt_hw_interrupt_handler(int vector, void *param) */ void rt_hw_interrupt_init(void) { - rt_base_t index; - rt_uint32_t *vect_addr, *vect_ctl; + rt_base_t index; + rt_uint32_t *vect_addr, *vect_ctl; - /* initialize VIC*/ - VICIntEnClr = 0xffffffff; - VICVectAddr = 0; - /* set all to IRQ */ - VICIntSelect = 0; + /* initialize VIC*/ + VICIntEnClr = 0xffffffff; + VICVectAddr = 0; + /* set all to IRQ */ + VICIntSelect = 0; rt_memset(irq_desc, 0x00, sizeof(irq_desc)); - for (index = 0; index < MAX_HANDLERS; index ++) - { + for (index = 0; index < MAX_HANDLERS; index ++) + { irq_desc[index].handler = rt_hw_interrupt_handler; - vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2)); - vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2)); + vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + (index << 2)); + vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (index << 2)); - *vect_addr = (rt_uint32_t)&irq_desc[index]; - *vect_ctl = 0xF; - } + *vect_addr = (rt_uint32_t)&irq_desc[index]; + *vect_ctl = 0xF; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -116,7 +116,7 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - VICIntEnClr = (1 << vector); + VICIntEnClr = (1 << vector); } /** @@ -125,7 +125,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - VICIntEnable = (1 << vector); + VICIntEnable = (1 << vector); } /** @@ -143,17 +143,17 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if(vector >= 0 && vector < MAX_HANDLERS) { - rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2)); + rt_uint32_t* vect_ctl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + (vector << 2)); /* assign IRQ slot and enable this slot */ *vect_ctl = 0x20 | (vector & 0x1F); old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } + if (handler != RT_NULL) + { + irq_desc[vector].handler = handler; + irq_desc[vector].param = param; + } } return old_handler; @@ -173,22 +173,22 @@ RT_WEAK void rt_hw_cpu_reset(void) */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } void rt_hw_trap_irq(void) { int irqno; - struct rt_irq_desc* irq; + struct rt_irq_desc* irq; extern struct rt_irq_desc irq_desc[]; - irq = (struct rt_irq_desc*) VICVectAddr; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); + irq = (struct rt_irq_desc*) VICVectAddr; + irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - /* invoke isr */ - irq->handler(irqno, irq->param); + /* invoke isr */ + irq->handler(irqno, irq->param); /* acknowledge Interrupt */ // VICVectAddr = 0; diff --git a/libcpu/arm/lpc214x/lpc214x.h b/libcpu/arm/lpc214x/lpc214x.h index 1805bc6c03..21691f85ad 100644 --- a/libcpu/arm/lpc214x/lpc214x.h +++ b/libcpu/arm/lpc214x/lpc214x.h @@ -361,33 +361,33 @@ #define USBSysErrIntClr (*((volatile unsigned long *) 0xE00900BC)) #define USBSysErrIntSet (*((volatile unsigned long *) 0xE00900C0)) -#define VIC_BASE_ADDR 0xFFFFF000 +#define VIC_BASE_ADDR 0xFFFFF000 enum LPC214x_INT { - WDT_INT = 0, - SW_INT_reserved, - DbgCommRx_INT, - DbgCommTx_INT, - TIMER0_INT, - TIMER1_INT, - UART0_INT, - UART1_INT, - PWM0_INT, - I2C0_INT, - SP0_INT, - SP1_INT, - PLL_INT, - RTC_INT, - EINT0_INT, - EINT1_INT, - EINT2_INT, - EINT3_INT, - ADC0_INT, - I2C1_INT, - BOD_INT, - ADC1_INT, - USB_INT + WDT_INT = 0, + SW_INT_reserved, + DbgCommRx_INT, + DbgCommTx_INT, + TIMER0_INT, + TIMER1_INT, + UART0_INT, + UART1_INT, + PWM0_INT, + I2C0_INT, + SP0_INT, + SP1_INT, + PLL_INT, + RTC_INT, + EINT0_INT, + EINT1_INT, + EINT2_INT, + EINT3_INT, + ADC0_INT, + I2C1_INT, + BOD_INT, + ADC1_INT, + USB_INT }; #endif // __LPC214x_H diff --git a/libcpu/arm/lpc24xx/LPC24xx.h b/libcpu/arm/lpc24xx/LPC24xx.h index 5cb9730854..827310ca67 100644 --- a/libcpu/arm/lpc24xx/LPC24xx.h +++ b/libcpu/arm/lpc24xx/LPC24xx.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,20 +14,20 @@ #ifdef __cplusplus extern "C" { #endif - -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#define MCLK (72000000) - + +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 + +#define MCLK (72000000) + /* Vectored Interrupt Controller (VIC) */ -#define VIC_BASE_ADDR 0xFFFFF000 +#define VIC_BASE_ADDR 0xFFFFF000 #define VICIRQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x000)) #define VICFIQStatus (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x004)) #define VICRawIntr (*(volatile unsigned long *)(VIC_BASE_ADDR + 0x008)) @@ -111,7 +111,7 @@ these registers are known as "VICVectPriority(x)". */ /* Pin Connect Block */ -#define PINSEL_BASE_ADDR 0xE002C000 +#define PINSEL_BASE_ADDR 0xE002C000 #define PINSEL0 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x00)) #define PINSEL1 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x04)) #define PINSEL2 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x08)) @@ -137,7 +137,7 @@ these registers are known as "VICVectPriority(x)". */ #define PINMODE9 (*(volatile unsigned long *)(PINSEL_BASE_ADDR + 0x64)) /* General Purpose Input/Output (GPIO) */ -#define GPIO_BASE_ADDR 0xE0028000 +#define GPIO_BASE_ADDR 0xE0028000 #define IOPIN0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x00)) #define IOSET0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x04)) #define IODIR0 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x08)) @@ -148,13 +148,13 @@ these registers are known as "VICVectPriority(x)". */ #define IOCLR1 (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x1C)) /* GPIO Interrupt Registers */ -#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) +#define IO0_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x90)) #define IO0_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x94)) #define IO0_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x84)) #define IO0_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x88)) #define IO0_INT_CLR (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x8C)) -#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) +#define IO2_INT_EN_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB0)) #define IO2_INT_EN_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xB4)) #define IO2_INT_STAT_R (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA4)) #define IO2_INT_STAT_F (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0xA8)) @@ -162,227 +162,227 @@ these registers are known as "VICVectPriority(x)". */ #define IO_INT_STAT (*(volatile unsigned long *)(GPIO_BASE_ADDR + 0x80)) -#define PARTCFG_BASE_ADDR 0x3FFF8000 -#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) +#define PARTCFG_BASE_ADDR 0x3FFF8000 +#define PARTCFG (*(volatile unsigned long *)(PARTCFG_BASE_ADDR + 0x00)) /* Fast I/O setup */ -#define FIO_BASE_ADDR 0x3FFFC000 -#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) +#define FIO_BASE_ADDR 0x3FFFC000 +#define FIO0DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x00)) #define FIO0MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x10)) #define FIO0PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x14)) #define FIO0SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x18)) #define FIO0CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) +#define FIO1DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x20)) #define FIO1MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x30)) #define FIO1PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x34)) #define FIO1SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x38)) #define FIO1CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) +#define FIO2DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x40)) #define FIO2MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x50)) #define FIO2PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x54)) #define FIO2SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x58)) #define FIO2CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) +#define FIO3DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x60)) #define FIO3MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x70)) #define FIO3PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x74)) #define FIO3SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x78)) #define FIO3CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) +#define FIO4DIR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x80)) #define FIO4MASK (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x90)) #define FIO4PIN (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x94)) #define FIO4SET (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x98)) #define FIO4CLR (*(volatile unsigned long *)(FIO_BASE_ADDR + 0x9C)) /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ -#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) +#define FIO0DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x80)) -#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) -#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) -#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) -#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) +#define FIO0DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x01)) +#define FIO1DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x41)) +#define FIO3DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x61)) +#define FIO4DIR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x81)) -#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) +#define FIO0DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x82)) -#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) -#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) -#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) -#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) -#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) +#define FIO0DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x03)) +#define FIO1DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x23)) +#define FIO2DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x43)) +#define FIO3DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x63)) +#define FIO4DIR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x83)) -#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) -#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) -#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) -#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) -#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) +#define FIO0DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x00)) +#define FIO1DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x20)) +#define FIO2DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x40)) +#define FIO3DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x60)) +#define FIO4DIRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x80)) -#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) -#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) -#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) -#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) -#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) +#define FIO0DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x02)) +#define FIO1DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x22)) +#define FIO2DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x42)) +#define FIO3DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x62)) +#define FIO4DIRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x82)) -#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) +#define FIO0MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASK0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x90)) -#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) -#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) -#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) -#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) -#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) +#define FIO0MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x11)) +#define FIO1MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x21)) +#define FIO2MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x51)) +#define FIO3MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x71)) +#define FIO4MASK1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x91)) -#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) +#define FIO0MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASK2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x92)) -#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) -#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) -#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) -#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) -#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) +#define FIO0MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x13)) +#define FIO1MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x33)) +#define FIO2MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x53)) +#define FIO3MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x73)) +#define FIO4MASK3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x93)) -#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) -#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) -#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) -#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) -#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) +#define FIO0MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x10)) +#define FIO1MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x30)) +#define FIO2MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x50)) +#define FIO3MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x70)) +#define FIO4MASKL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x90)) -#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) -#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) -#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) -#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) -#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) +#define FIO0MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x12)) +#define FIO1MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x32)) +#define FIO2MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x52)) +#define FIO3MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x72)) +#define FIO4MASKU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x92)) -#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) +#define FIO0PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PIN0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x94)) -#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) -#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) -#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) -#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) -#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) +#define FIO0PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x15)) +#define FIO1PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x35)) +#define FIO2PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x55)) +#define FIO3PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x75)) +#define FIO4PIN1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x95)) -#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) +#define FIO0PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PIN2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x96)) -#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) -#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) -#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) -#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) -#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) +#define FIO0PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x17)) +#define FIO1PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x37)) +#define FIO2PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x57)) +#define FIO3PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x77)) +#define FIO4PIN3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x97)) -#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) -#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) -#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) -#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) -#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) +#define FIO0PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x14)) +#define FIO1PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x34)) +#define FIO2PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x54)) +#define FIO3PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x74)) +#define FIO4PINL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x94)) -#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) -#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) -#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) -#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) -#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) +#define FIO0PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x16)) +#define FIO1PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x36)) +#define FIO2PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x56)) +#define FIO3PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x76)) +#define FIO4PINU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x96)) -#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) +#define FIO0SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SET0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x98)) -#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) -#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) -#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) -#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) -#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) +#define FIO0SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x19)) +#define FIO1SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x29)) +#define FIO2SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x59)) +#define FIO3SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x79)) +#define FIO4SET1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x99)) -#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) +#define FIO0SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SET2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9A)) -#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) -#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) -#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) -#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) -#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) +#define FIO0SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1B)) +#define FIO1SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3B)) +#define FIO2SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5B)) +#define FIO3SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7B)) +#define FIO4SET3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9B)) -#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) -#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) -#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) -#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) -#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) +#define FIO0SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x18)) +#define FIO1SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x38)) +#define FIO2SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x58)) +#define FIO3SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x78)) +#define FIO4SETL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x98)) -#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) -#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) -#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) -#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) -#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) +#define FIO0SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1A)) +#define FIO1SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3A)) +#define FIO2SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5A)) +#define FIO3SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7A)) +#define FIO4SETU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9A)) -#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) +#define FIO0CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLR0 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9C)) -#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) -#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) -#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) -#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) -#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) +#define FIO0CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1D)) +#define FIO1CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x2D)) +#define FIO2CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5D)) +#define FIO3CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7D)) +#define FIO4CLR1 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9D)) -#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) +#define FIO0CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLR2 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9E)) -#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) -#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) -#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) -#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) -#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) +#define FIO0CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x1F)) +#define FIO1CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x3F)) +#define FIO2CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x5F)) +#define FIO3CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x7F)) +#define FIO4CLR3 (*(volatile unsigned char *)(FIO_BASE_ADDR + 0x9F)) -#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) -#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) -#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) -#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) -#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) +#define FIO0CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1C)) +#define FIO1CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3C)) +#define FIO2CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5C)) +#define FIO3CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7C)) +#define FIO4CLRL (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9C)) -#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) -#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) -#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) -#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) -#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) +#define FIO0CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x1E)) +#define FIO1CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x3E)) +#define FIO2CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x5E)) +#define FIO3CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x7E)) +#define FIO4CLRU (*(volatile unsigned short *)(FIO_BASE_ADDR + 0x9E)) /* System Control Block(SCB) modules include Memory Accelerator Module, -Phase Locked Loop, VPB divider, Power Control, External Interrupt, +Phase Locked Loop, VPB divider, Power Control, External Interrupt, Reset, and Code Security/Debugging */ -#define SCB_BASE_ADDR 0xE01FC000 +#define SCB_BASE_ADDR 0xE01FC000 /* Memory Accelerator Module (MAM) */ #define MAMCR (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x000)) @@ -405,7 +405,7 @@ Reset, and Code Security/Debugging */ #define CLKSRCSEL (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x10C)) #define PCLKSEL0 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A8)) #define PCLKSEL1 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1AC)) - + /* External Interrupts */ #define EXTINT (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x140)) #define INTWAKE (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x144)) @@ -423,22 +423,22 @@ Reset, and Code Security/Debugging */ #define AHBCFG2 (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x18C)) /* System Controls and Status */ -#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) +#define SCS (*(volatile unsigned long *)(SCB_BASE_ADDR + 0x1A0)) -/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers +/* MPMC(EMC) registers, note: all the external memory controller(EMC) registers are for LPC24xx only. */ -#define STATIC_MEM0_BASE 0x80000000 -#define STATIC_MEM1_BASE 0x81000000 -#define STATIC_MEM2_BASE 0x82000000 -#define STATIC_MEM3_BASE 0x83000000 +#define STATIC_MEM0_BASE 0x80000000 +#define STATIC_MEM1_BASE 0x81000000 +#define STATIC_MEM2_BASE 0x82000000 +#define STATIC_MEM3_BASE 0x83000000 -#define DYNAMIC_MEM0_BASE 0xA0000000 -#define DYNAMIC_MEM1_BASE 0xB0000000 -#define DYNAMIC_MEM2_BASE 0xC0000000 -#define DYNAMIC_MEM3_BASE 0xD0000000 +#define DYNAMIC_MEM0_BASE 0xA0000000 +#define DYNAMIC_MEM1_BASE 0xB0000000 +#define DYNAMIC_MEM2_BASE 0xC0000000 +#define DYNAMIC_MEM3_BASE 0xD0000000 /* External Memory Controller (EMC) */ -#define EMC_BASE_ADDR 0xFFE08000 +#define EMC_BASE_ADDR 0xFFE08000 #define EMC_CTRL (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x000)) #define EMC_STAT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x004)) #define EMC_CONFIG (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x008)) @@ -503,9 +503,9 @@ are for LPC24xx only. */ #define EMC_STA_EXT_WAIT (*(volatile unsigned long *)(EMC_BASE_ADDR + 0x880)) - + /* Timer 0 */ -#define TMR0_BASE_ADDR 0xE0004000 +#define TMR0_BASE_ADDR 0xE0004000 #define T0IR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x00)) #define T0TCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x04)) #define T0TC (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x08)) @@ -525,7 +525,7 @@ are for LPC24xx only. */ #define T0CTCR (*(volatile unsigned long *)(TMR0_BASE_ADDR + 0x70)) /* Timer 1 */ -#define TMR1_BASE_ADDR 0xE0008000 +#define TMR1_BASE_ADDR 0xE0008000 #define T1IR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x00)) #define T1TCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x04)) #define T1TC (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x08)) @@ -545,7 +545,7 @@ are for LPC24xx only. */ #define T1CTCR (*(volatile unsigned long *)(TMR1_BASE_ADDR + 0x70)) /* Timer 2 */ -#define TMR2_BASE_ADDR 0xE0070000 +#define TMR2_BASE_ADDR 0xE0070000 #define T2IR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x00)) #define T2TCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x04)) #define T2TC (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x08)) @@ -565,7 +565,7 @@ are for LPC24xx only. */ #define T2CTCR (*(volatile unsigned long *)(TMR2_BASE_ADDR + 0x70)) /* Timer 3 */ -#define TMR3_BASE_ADDR 0xE0074000 +#define TMR3_BASE_ADDR 0xE0074000 #define T3IR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x00)) #define T3TCR (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x04)) #define T3TC (*(volatile unsigned long *)(TMR3_BASE_ADDR + 0x08)) @@ -586,7 +586,7 @@ are for LPC24xx only. */ /* Pulse Width Modulator (PWM) */ -#define PWM0_BASE_ADDR 0xE0014000 +#define PWM0_BASE_ADDR 0xE0014000 #define PWM0IR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x00)) #define PWM0TCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x04)) #define PWM0TC (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x08)) @@ -610,7 +610,7 @@ are for LPC24xx only. */ #define PWM0LER (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x50)) #define PWM0CTCR (*(volatile unsigned long *)(PWM0_BASE_ADDR + 0x70)) -#define PWM1_BASE_ADDR 0xE0018000 +#define PWM1_BASE_ADDR 0xE0018000 #define PWM1IR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x00)) #define PWM1TCR (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x04)) #define PWM1TC (*(volatile unsigned long *)(PWM1_BASE_ADDR + 0x08)) @@ -636,7 +636,7 @@ are for LPC24xx only. */ /* Universal Asynchronous Receiver Transmitter 0 (UART0) */ -#define UART0_BASE_ADDR 0xE000C000 +#define UART0_BASE_ADDR 0xE000C000 #define U0RBR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U0THR (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) #define U0DLL (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x00)) @@ -653,7 +653,7 @@ are for LPC24xx only. */ #define U0TER (*(volatile unsigned long *)(UART0_BASE_ADDR + 0x30)) /* Universal Asynchronous Receiver Transmitter 1 (UART1) */ -#define UART1_BASE_ADDR 0xE0010000 +#define UART1_BASE_ADDR 0xE0010000 #define U1RBR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) #define U1THR (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) #define U1DLL (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x00)) @@ -671,7 +671,7 @@ are for LPC24xx only. */ #define U1TER (*(volatile unsigned long *)(UART1_BASE_ADDR + 0x30)) /* Universal Asynchronous Receiver Transmitter 2 (UART2) */ -#define UART2_BASE_ADDR 0xE0078000 +#define UART2_BASE_ADDR 0xE0078000 #define U2RBR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) #define U2THR (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) #define U2DLL (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x00)) @@ -688,7 +688,7 @@ are for LPC24xx only. */ #define U2TER (*(volatile unsigned long *)(UART2_BASE_ADDR + 0x30)) /* Universal Asynchronous Receiver Transmitter 3 (UART3) */ -#define UART3_BASE_ADDR 0xE007C000 +#define UART3_BASE_ADDR 0xE007C000 #define U3RBR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) #define U3THR (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) #define U3DLL (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x00)) @@ -705,7 +705,7 @@ are for LPC24xx only. */ #define U3TER (*(volatile unsigned long *)(UART3_BASE_ADDR + 0x30)) /* I2C Interface 0 */ -#define I2C0_BASE_ADDR 0xE001C000 +#define I2C0_BASE_ADDR 0xE001C000 #define I20CONSET (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x00)) #define I20STAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x04)) #define I20DAT (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x08)) @@ -715,7 +715,7 @@ are for LPC24xx only. */ #define I20CONCLR (*(volatile unsigned long *)(I2C0_BASE_ADDR + 0x18)) /* I2C Interface 1 */ -#define I2C1_BASE_ADDR 0xE005C000 +#define I2C1_BASE_ADDR 0xE005C000 #define I21CONSET (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x00)) #define I21STAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x04)) #define I21DAT (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x08)) @@ -725,7 +725,7 @@ are for LPC24xx only. */ #define I21CONCLR (*(volatile unsigned long *)(I2C1_BASE_ADDR + 0x18)) /* I2C Interface 2 */ -#define I2C2_BASE_ADDR 0xE0080000 +#define I2C2_BASE_ADDR 0xE0080000 #define I22CONSET (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x00)) #define I22STAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x04)) #define I22DAT (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x08)) @@ -735,7 +735,7 @@ are for LPC24xx only. */ #define I22CONCLR (*(volatile unsigned long *)(I2C2_BASE_ADDR + 0x18)) /* SPI0 (Serial Peripheral Interface 0) */ -#define SPI0_BASE_ADDR 0xE0020000 +#define SPI0_BASE_ADDR 0xE0020000 #define S0SPCR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x00)) #define S0SPSR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x04)) #define S0SPDR (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x08)) @@ -743,7 +743,7 @@ are for LPC24xx only. */ #define S0SPINT (*(volatile unsigned long *)(SPI0_BASE_ADDR + 0x1C)) /* SSP0 Controller */ -#define SSP0_BASE_ADDR 0xE0068000 +#define SSP0_BASE_ADDR 0xE0068000 #define SSP0CR0 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x00)) #define SSP0CR1 (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x04)) #define SSP0DR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x08)) @@ -756,7 +756,7 @@ are for LPC24xx only. */ #define SSP0DMACR (*(volatile unsigned long *)(SSP0_BASE_ADDR + 0x24)) /* SSP1 Controller */ -#define SSP1_BASE_ADDR 0xE0030000 +#define SSP1_BASE_ADDR 0xE0030000 #define SSP1CR0 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x00)) #define SSP1CR1 (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x04)) #define SSP1DR (*(volatile unsigned long *)(SSP1_BASE_ADDR + 0x08)) @@ -770,7 +770,7 @@ are for LPC24xx only. */ /* Real Time Clock */ -#define RTC_BASE_ADDR 0xE0024000 +#define RTC_BASE_ADDR 0xE0024000 #define RTC_ILR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x00)) #define RTC_CTC (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x04)) #define RTC_CCR (*(volatile unsigned long *)(RTC_BASE_ADDR + 0x08)) @@ -801,7 +801,7 @@ are for LPC24xx only. */ /* A/D Converter 0 (AD0) */ -#define AD0_BASE_ADDR 0xE0034000 +#define AD0_BASE_ADDR 0xE0034000 #define AD0CR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x00)) #define AD0GDR (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x04)) #define AD0INTEN (*(volatile unsigned long *)(AD0_BASE_ADDR + 0x0C)) @@ -817,12 +817,12 @@ are for LPC24xx only. */ /* D/A Converter */ -#define DAC_BASE_ADDR 0xE006C000 +#define DAC_BASE_ADDR 0xE006C000 #define DACR (*(volatile unsigned long *)(DAC_BASE_ADDR + 0x00)) /* Watchdog */ -#define WDG_BASE_ADDR 0xE0000000 +#define WDG_BASE_ADDR 0xE0000000 #define WDMOD (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x00)) #define WDTC (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x04)) #define WDFEED (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x08)) @@ -830,78 +830,78 @@ are for LPC24xx only. */ #define WDCLKSEL (*(volatile unsigned long *)(WDG_BASE_ADDR + 0x10)) /* CAN CONTROLLERS AND ACCEPTANCE FILTER */ -#define CAN_ACCEPT_BASE_ADDR 0xE003C000 -#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) -#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) -#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) -#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) -#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) -#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) -#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) -#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) +#define CAN_ACCEPT_BASE_ADDR 0xE003C000 +#define CAN_AFMR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x00)) +#define CAN_SFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x04)) +#define CAN_SFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x08)) +#define CAN_EFF_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) +#define CAN_EFF_GRP_SA (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x10)) +#define CAN_EOT (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x14)) +#define CAN_LUT_ERR_ADR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x18)) +#define CAN_LUT_ERR (*(volatile unsigned long *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) + +#define CAN_CENTRAL_BASE_ADDR 0xE0040000 +#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) +#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) +#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) + +#define CAN1_BASE_ADDR 0xE0044000 +#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) +#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) +#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) +#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) +#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) +#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) +#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) +#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) +#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) +#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) +#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) +#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) -#define CAN_CENTRAL_BASE_ADDR 0xE0040000 -#define CAN_TX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x00)) -#define CAN_RX_SR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x04)) -#define CAN_MSR (*(volatile unsigned long *)(CAN_CENTRAL_BASE_ADDR + 0x08)) +#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) +#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) +#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) +#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) +#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) +#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) +#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) +#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) +#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) +#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) +#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) +#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) -#define CAN1_BASE_ADDR 0xE0044000 -#define CAN1MOD (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x00)) -#define CAN1CMR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x04)) -#define CAN1GSR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x08)) -#define CAN1ICR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x0C)) -#define CAN1IER (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x10)) -#define CAN1BTR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x14)) -#define CAN1EWL (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x18)) -#define CAN1SR (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x1C)) -#define CAN1RFS (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x20)) -#define CAN1RID (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x24)) -#define CAN1RDA (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x28)) -#define CAN1RDB (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x2C)) - -#define CAN1TFI1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x30)) -#define CAN1TID1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x34)) -#define CAN1TDA1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x38)) -#define CAN1TDB1 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x3C)) -#define CAN1TFI2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x40)) -#define CAN1TID2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x44)) -#define CAN1TDA2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x48)) -#define CAN1TDB2 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x4C)) -#define CAN1TFI3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x50)) -#define CAN1TID3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x54)) -#define CAN1TDA3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x58)) -#define CAN1TDB3 (*(volatile unsigned long *)(CAN1_BASE_ADDR + 0x5C)) +#define CAN2_BASE_ADDR 0xE0048000 +#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) +#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) +#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) +#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) +#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) +#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) +#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) +#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) +#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) +#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) +#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) +#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) -#define CAN2_BASE_ADDR 0xE0048000 -#define CAN2MOD (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x00)) -#define CAN2CMR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x04)) -#define CAN2GSR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x08)) -#define CAN2ICR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x0C)) -#define CAN2IER (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x10)) -#define CAN2BTR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x14)) -#define CAN2EWL (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x18)) -#define CAN2SR (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x1C)) -#define CAN2RFS (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x20)) -#define CAN2RID (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x24)) -#define CAN2RDA (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x28)) -#define CAN2RDB (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x2C)) - -#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) -#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) -#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) -#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) -#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) -#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) -#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) -#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) -#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) -#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) -#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) -#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) +#define CAN2TFI1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x30)) +#define CAN2TID1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x34)) +#define CAN2TDA1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x38)) +#define CAN2TDB1 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x3C)) +#define CAN2TFI2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x40)) +#define CAN2TID2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x44)) +#define CAN2TDA2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x48)) +#define CAN2TDB2 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x4C)) +#define CAN2TFI3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x50)) +#define CAN2TID3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x54)) +#define CAN2TDA3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x58)) +#define CAN2TDB3 (*(volatile unsigned long *)(CAN2_BASE_ADDR + 0x5C)) /* MultiMedia Card Interface(MCI) Controller */ -#define MCI_BASE_ADDR 0xE008C000 +#define MCI_BASE_ADDR 0xE008C000 #define MCI_POWER (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x00)) #define MCI_CLOCK (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x04)) #define MCI_ARGUMENT (*(volatile unsigned long *)(MCI_BASE_ADDR + 0x08)) @@ -924,7 +924,7 @@ are for LPC24xx only. */ /* I2S Interface Controller (I2S) */ -#define I2S_BASE_ADDR 0xE0088000 +#define I2S_BASE_ADDR 0xE0088000 #define I2S_DAO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x00)) #define I2S_DAI (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x04)) #define I2S_TX_FIFO (*(volatile unsigned long *)(I2S_BASE_ADDR + 0x08)) @@ -938,7 +938,7 @@ are for LPC24xx only. */ /* General-purpose DMA Controller */ -#define DMA_BASE_ADDR 0xFFE04000 +#define DMA_BASE_ADDR 0xFFE04000 #define GPDMA_INT_STAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x000)) #define GPDMA_INT_TCSTAT (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x004)) #define GPDMA_INT_TCCLR (*(volatile unsigned long *)(DMA_BASE_ADDR + 0x008)) @@ -970,8 +970,8 @@ are for LPC24xx only. */ /* USB Controller */ -#define USB_INT_BASE_ADDR 0xE01FC1C0 -#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ +#define USB_INT_BASE_ADDR 0xE01FC1C0 +#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ #define USB_INT_STAT (*(volatile unsigned long *)(USB_INT_BASE_ADDR + 0x00)) @@ -1027,7 +1027,7 @@ are for LPC24xx only. */ /* USB Host and OTG registers are for LPC24xx only */ /* USB Host Controller */ -#define USBHC_BASE_ADDR 0xFFE0C000 +#define USBHC_BASE_ADDR 0xFFE0C000 #define HC_REVISION (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x00)) #define HC_CONTROL (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x04)) #define HC_CMD_STAT (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x08)) @@ -1053,16 +1053,16 @@ are for LPC24xx only. */ #define HC_RH_PORT_STAT2 (*(volatile unsigned long *)(USBHC_BASE_ADDR + 0x58)) /* USB OTG Controller */ -#define USBOTG_BASE_ADDR 0xFFE0C100 +#define USBOTG_BASE_ADDR 0xFFE0C100 #define OTG_INT_STAT (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x00)) #define OTG_INT_EN (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x04)) #define OTG_INT_SET (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x08)) #define OTG_INT_CLR (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x0C)) -/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ +/* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ #define OTG_STAT_CTRL (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) #define OTG_TIMER (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x14)) -#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 +#define USBOTG_I2C_BASE_ADDR 0xFFE0C300 #define OTG_I2C_RX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) #define OTG_I2C_TX (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x00)) #define OTG_I2C_STS (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x04)) @@ -1070,20 +1070,20 @@ are for LPC24xx only. */ #define OTG_I2C_CLKHI (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x0C)) #define OTG_I2C_CLKLO (*(volatile unsigned long *)(USBOTG_I2C_BASE_ADDR + 0x10)) -/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are +/* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ -#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 +#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 #define OTG_CLK_CTRL (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) #define OTG_CLK_STAT (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) /* Note: below three register name convention is for LPC23xx USB device only, match -with the spec. update in USB Device Section. */ +with the spec. update in USB Device Section. */ #define USBPortSel (*(volatile unsigned long *)(USBOTG_BASE_ADDR + 0x10)) #define USBClkCtrl (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x04)) #define USBClkSt (*(volatile unsigned long *)(USBOTG_CLK_BASE_ADDR + 0x08)) /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ -#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ +#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ #define MAC_MAC1 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ #define MAC_MAC2 (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ #define MAC_IPGT (*(volatile unsigned long *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ @@ -1139,7 +1139,7 @@ with the spec. update in USB Device Section. */ #define MAC_MODULEID (*(volatile unsigned long *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ /* LCD Controller registers */ -#define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */ +#define LCD_BASE_ADDR 0xFFE10000 /* AHB Peripheral # 4 */ #define LCD_CFG (*(volatile unsigned long *)(0xE01FC1B8)) #define LCD_TIMH (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x000)) #define LCD_TIMV (*(volatile unsigned long *)(LCD_BASE_ADDR + 0x004)) @@ -1169,24 +1169,24 @@ with the spec. update in USB Device Section. */ struct rt_hw_register { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; }; #ifdef __cplusplus diff --git a/libcpu/arm/lpc24xx/cpu.c b/libcpu/arm/lpc24xx/cpu.c index 0453722d1d..d9c74020bb 100644 --- a/libcpu/arm/lpc24xx/cpu.c +++ b/libcpu/arm/lpc24xx/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,9 +30,9 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/lpc24xx/interrupt.c b/libcpu/arm/lpc24xx/interrupt.c index a855de1e11..87bb86b879 100644 --- a/libcpu/arm/lpc24xx/interrupt.c +++ b/libcpu/arm/lpc24xx/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,10 +13,10 @@ #include <rthw.h> #include "LPC24xx.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 /* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; +struct rt_irq_desc irq_desc[MAX_HANDLERS]; extern rt_uint32_t rt_interrupt_nest; @@ -30,19 +30,19 @@ rt_uint32_t rt_thread_switch_interrupt_flag; /*@{*/ void rt_hw_interrupt_handler(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } void rt_hw_interrupt_init(void) { - register int i; + register int i; - rt_uint32_t *vect_addr, *vect_cntl; - - /* initialize VIC*/ - VICIntEnClr = 0xffffffff; - VICVectAddr = 0; - VICIntSelect = 0; + rt_uint32_t *vect_addr, *vect_cntl; + + /* initialize VIC*/ + VICIntEnClr = 0xffffffff; + VICVectAddr = 0; + VICIntSelect = 0; /* init exceptions table */ rt_memset(irq_desc, 0x00, sizeof(irq_desc)); @@ -50,27 +50,27 @@ void rt_hw_interrupt_init(void) { irq_desc[i].handler = rt_hw_interrupt_handler; - vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + i*4); - vect_cntl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + i*4); - *vect_addr = (rt_uint32_t)&irq_desc[i]; - *vect_cntl = 0xF; + vect_addr = (rt_uint32_t *)(VIC_BASE_ADDR + 0x100 + i*4); + vect_cntl = (rt_uint32_t *)(VIC_BASE_ADDR + 0x200 + i*4); + *vect_addr = (rt_uint32_t)&irq_desc[i]; + *vect_cntl = 0xF; } - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } void rt_hw_interrupt_mask(int vector) { - VICIntEnClr = (1 << vector); + VICIntEnClr = (1 << vector); } void rt_hw_interrupt_umask(int vector) { - VICIntEnable = (1 << vector); + VICIntEnable = (1 << vector); } /** @@ -82,22 +82,22 @@ void rt_hw_interrupt_umask(int vector) * * @return the old handler */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, + void *param, const char *name) { - rt_isr_handler_t old_handler = RT_NULL; + rt_isr_handler_t old_handler = RT_NULL; - if(vector >= 0 && vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = handler; - irq_desc[vector].param = param; - } - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + old_handler = irq_desc[vector].handler; + if (handler != RT_NULL) + { + irq_desc[vector].handler = handler; + irq_desc[vector].param = param; + } + } - return old_handler; + return old_handler; } /*@}*/ diff --git a/libcpu/arm/lpc24xx/stack.c b/libcpu/arm/lpc24xx/stack.c index 0378a5f658..a7bce755b3 100644 --- a/libcpu/arm/lpc24xx/stack.c +++ b/libcpu/arm/lpc24xx/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/lpc24xx/trap.c b/libcpu/arm/lpc24xx/trap.c index d296bfdbfe..7ad7328a93 100644 --- a/libcpu/arm/lpc24xx/trap.c +++ b/libcpu/arm/lpc24xx/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,13 +27,13 @@ */ void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -48,8 +48,8 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) { rt_kprintf("undefined instruction\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -66,8 +66,8 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) { rt_kprintf("software interrupt\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -83,8 +83,8 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) { rt_kprintf("prefetch abort\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -97,11 +97,11 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) * @note never invoke this function in application */ void rt_hw_trap_dabt(struct rt_hw_register *regs) -{ +{ rt_kprintf("Data Abort "); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } @@ -116,27 +116,27 @@ void rt_hw_trap_resv(struct rt_hw_register *regs) { rt_kprintf("not used\n"); rt_hw_show_register(regs); - if (rt_thread_self() != RT_NULL) - rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); + if (rt_thread_self() != RT_NULL) + rt_kprintf("Current Thread: %s\n", rt_thread_self()->name); rt_hw_cpu_shutdown(); } extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq(void) { - int irqno; - struct rt_irq_desc* irq; - extern struct rt_irq_desc irq_desc[]; + int irqno; + struct rt_irq_desc* irq; + extern struct rt_irq_desc irq_desc[]; - irq = (struct rt_irq_desc*) VICVectAddr; - irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); + irq = (struct rt_irq_desc*) VICVectAddr; + irqno = ((rt_uint32_t) irq - (rt_uint32_t) &irq_desc[0])/sizeof(struct rt_irq_desc); - /* invoke isr */ - irq->handler(irqno, irq->param); + /* invoke isr */ + irq->handler(irqno, irq->param); } void rt_hw_trap_fiq(void) -{ +{ rt_kprintf("fast interrupt request\n"); } diff --git a/libcpu/arm/realview-a8-vmm/armv7.h b/libcpu/arm/realview-a8-vmm/armv7.h index d22f72fa68..f284bb5255 100644 --- a/libcpu/arm/realview-a8-vmm/armv7.h +++ b/libcpu/arm/realview-a8-vmm/armv7.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,43 +12,43 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; struct rt_hw_stack { - unsigned long cpsr; - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long lr; - unsigned long pc; + unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long lr; + unsigned long pc; }; #define USERMODE 0x10 diff --git a/libcpu/arm/realview-a8-vmm/cp15.h b/libcpu/arm/realview-a8-vmm/cp15.h index 486f38200d..b18331af92 100644 --- a/libcpu/arm/realview-a8-vmm/cp15.h +++ b/libcpu/arm/realview-a8-vmm/cp15.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/cpu.c b/libcpu/arm/realview-a8-vmm/cpu.c index dbdb4ac515..8c5a6d16dd 100644 --- a/libcpu/arm/realview-a8-vmm/cpu.c +++ b/libcpu/arm/realview-a8-vmm/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,14 @@ /** shutdown CPU */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/arm/realview-a8-vmm/gic.c b/libcpu/arm/realview-a8-vmm/gic.c index 82f87b7e8f..962317821a 100644 --- a/libcpu/arm/realview-a8-vmm/gic.c +++ b/libcpu/arm/realview-a8-vmm/gic.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/gic.h b/libcpu/arm/realview-a8-vmm/gic.h index 8fcdf05f6f..7c781ad4d9 100644 --- a/libcpu/arm/realview-a8-vmm/gic.h +++ b/libcpu/arm/realview-a8-vmm/gic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/interrupt.c b/libcpu/arm/realview-a8-vmm/interrupt.c index 5ef0bdc460..23ff062a8b 100644 --- a/libcpu/arm/realview-a8-vmm/interrupt.c +++ b/libcpu/arm/realview-a8-vmm/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -26,9 +26,9 @@ extern volatile rt_uint8_t rt_interrupt_nest; struct rt_irq_desc isr_table[MAX_HANDLERS]; /* Those varibles will be accessed in ISR, so we need to share them. */ -rt_uint32_t rt_interrupt_from_thread SECTION(".bss.share.int"); -rt_uint32_t rt_interrupt_to_thread SECTION(".bss.share.int"); -rt_uint32_t rt_thread_switch_interrupt_flag SECTION(".bss.share.int"); +rt_uint32_t rt_interrupt_from_thread RT_SECTION(".bss.share.int"); +rt_uint32_t rt_interrupt_to_thread RT_SECTION(".bss.share.int"); +rt_uint32_t rt_thread_switch_interrupt_flag RT_SECTION(".bss.share.int"); const unsigned int VECTOR_BASE = 0x00; extern void rt_cpu_vector_set_base(unsigned int addr); diff --git a/libcpu/arm/realview-a8-vmm/interrupt.h b/libcpu/arm/realview-a8-vmm/interrupt.h index 7461f94da0..90f392f407 100644 --- a/libcpu/arm/realview-a8-vmm/interrupt.h +++ b/libcpu/arm/realview-a8-vmm/interrupt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -14,28 +14,28 @@ #define INT_IRQ 0x00 #define INT_FIQ 0x01 -#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) -#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) -#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) -#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) -#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) -#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) -#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) -#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) -#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) -#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) -#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) -#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) -#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) -#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) -#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) -#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) -#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) -#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) -#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) +#define INTC_REVISION(hw_base) REG32((hw_base) + 0x0) +#define INTC_SYSCONFIG(hw_base) REG32((hw_base) + 0x10) +#define INTC_SYSSTATUS(hw_base) REG32((hw_base) + 0x14) +#define INTC_SIR_IRQ(hw_base) REG32((hw_base) + 0x40) +#define INTC_SIR_FIQ(hw_base) REG32((hw_base) + 0x44) +#define INTC_CONTROL(hw_base) REG32((hw_base) + 0x48) +#define INTC_PROTECTION(hw_base) REG32((hw_base) + 0x4c) +#define INTC_IDLE(hw_base) REG32((hw_base) + 0x50) +#define INTC_IRQ_PRIORITY(hw_base) REG32((hw_base) + 0x60) +#define INTC_FIQ_PRIORITY(hw_base) REG32((hw_base) + 0x64) +#define INTC_THRESHOLD(hw_base) REG32((hw_base) + 0x68) +#define INTC_SICR(hw_base) REG32((hw_base) + 0x6c) +#define INTC_SCR(hw_base, n) REG32((hw_base) + 0x70 + ((n) * 0x04)) +#define INTC_ITR(hw_base, n) REG32((hw_base) + 0x80 + ((n) * 0x20)) +#define INTC_MIR(hw_base, n) REG32((hw_base) + 0x84 + ((n) * 0x20)) +#define INTC_MIR_CLEAR(hw_base, n) REG32((hw_base) + 0x88 + ((n) * 0x20)) +#define INTC_MIR_SET(hw_base, n) REG32((hw_base) + 0x8c + ((n) * 0x20)) +#define INTC_ISR_SET(hw_base, n) REG32((hw_base) + 0x90 + ((n) * 0x20)) +#define INTC_ISR_CLEAR(hw_base, n) REG32((hw_base) + 0x94 + ((n) * 0x20)) #define INTC_PENDING_IRQ(hw_base, n) REG32((hw_base) + 0x98 + ((n) * 0x20)) #define INTC_PENDING_FIQ(hw_base, n) REG32((hw_base) + 0x9c + ((n) * 0x20)) -#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) +#define INTC_ILR(hw_base, n) REG32((hw_base) + 0x100 + ((n) * 0x04)) void rt_hw_interrupt_control(int vector, int priority, int route); int rt_hw_interrupt_get_active(int fiq_irq); diff --git a/libcpu/arm/realview-a8-vmm/mmu.c b/libcpu/arm/realview-a8-vmm/mmu.c index 58acdd8145..f4d6068099 100644 --- a/libcpu/arm/realview-a8-vmm/mmu.c +++ b/libcpu/arm/realview-a8-vmm/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/pmu.c b/libcpu/arm/realview-a8-vmm/pmu.c index 8ffc1dede6..2b9165cc8b 100644 --- a/libcpu/arm/realview-a8-vmm/pmu.c +++ b/libcpu/arm/realview-a8-vmm/pmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/pmu.h b/libcpu/arm/realview-a8-vmm/pmu.h index fb8390133d..64a74b5d39 100644 --- a/libcpu/arm/realview-a8-vmm/pmu.h +++ b/libcpu/arm/realview-a8-vmm/pmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/stack.c b/libcpu/arm/realview-a8-vmm/stack.c index 619a16c446..8cf73ac05c 100644 --- a/libcpu/arm/realview-a8-vmm/stack.c +++ b/libcpu/arm/realview-a8-vmm/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/realview-a8-vmm/trap.c b/libcpu/arm/realview-a8-vmm/trap.c index 4a522f5126..c6ca45aee7 100644 --- a/libcpu/arm/realview-a8-vmm/trap.c +++ b/libcpu/arm/realview-a8-vmm/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -131,7 +131,7 @@ void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) rt_hw_cpu_shutdown(); } -#define GIC_ACK_INTID_MASK 0x000003ff +#define GIC_ACK_INTID_MASK 0x000003ff void rt_hw_trap_irq(void) { diff --git a/libcpu/arm/s3c24x0/cpu.c b/libcpu/arm/s3c24x0/cpu.c index 2adf526a5c..3a72782ae4 100644 --- a/libcpu/arm/s3c24x0/cpu.c +++ b/libcpu/arm/s3c24x0/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -17,76 +17,76 @@ */ /*@{*/ -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -96,7 +96,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -105,7 +105,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -114,7 +114,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -123,7 +123,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -132,7 +132,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -141,7 +141,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -150,21 +150,21 @@ rt_base_t rt_hw_cpu_dcache_status() */ RT_WEAK void rt_hw_cpu_reset() { - /* Disable all interrupt except the WDT */ - INTMSK = (~((rt_uint32_t)1 << INTWDT)); + /* Disable all interrupt except the WDT */ + INTMSK = (~((rt_uint32_t)1 << INTWDT)); - /* Disable watchdog */ - WTCON = 0x0000; + /* Disable watchdog */ + WTCON = 0x0000; - /* Initialize watchdog timer count register */ - WTCNT = 0x0001; + /* Initialize watchdog timer count register */ + WTCNT = 0x0001; - /* Enable watchdog timer; assert reset at timer timeout */ - WTCON = 0x0021; + /* Enable watchdog timer; assert reset at timer timeout */ + WTCON = 0x0021; - while(1); /* loop forever and wait for reset to happen */ + while(1); /* loop forever and wait for reset to happen */ - /* NEVER REACHED */ + /* NEVER REACHED */ } /** @@ -173,14 +173,14 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/arm/s3c24x0/interrupt.c b/libcpu/arm/s3c24x0/interrupt.c index 8c7aebeb25..c985fc7c86 100644 --- a/libcpu/arm/s3c24x0/interrupt.c +++ b/libcpu/arm/s3c24x0/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #include <rthw.h> #include "s3c24x0.h" -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 extern rt_uint32_t rt_interrupt_nest; @@ -29,7 +29,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -77,7 +77,7 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - INTMSK |= 1 << vector; + INTMSK |= 1 << vector; } /** @@ -86,15 +86,15 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - if (vector == INTNOTUSED6) - { - rt_kprintf("Interrupt vec %d is not used!\n", vector); - // while(1); - } - else if (vector == INTGLOBAL) - INTMSK = 0x0; - else - INTMSK &= ~(1 << vector); + if (vector == INTNOTUSED6) + { + rt_kprintf("Interrupt vec %d is not used!\n", vector); + // while(1); + } + else if (vector == INTGLOBAL) + INTMSK = 0x0; + else + INTMSK &= ~(1 << vector); } /** @@ -115,9 +115,9 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if (handler != RT_NULL) { #ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); #endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; + isr_table[vector].handler = handler; isr_table[vector].param = param; } } diff --git a/libcpu/arm/s3c24x0/mmu.c b/libcpu/arm/s3c24x0/mmu.c index dc993ec9a3..4e5ef8d3c6 100644 --- a/libcpu/arm/s3c24x0/mmu.c +++ b/libcpu/arm/s3c24x0/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,158 +12,158 @@ #include <rtthread.h> #include "s3c24x0.h" -#define _MMUTT_STARTADDRESS 0x33FF0000 +#define _MMUTT_STARTADDRESS 0x33FF0000 -#define DESC_SEC (0x2|(1<<4)) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO +#define DESC_SEC (0x2|(1<<4)) +#define CB (3<<2) //cache_on, write_back +#define CNB (2<<2) //cache_on, write_through +#define NCB (1<<2) //cache_off,WR_BUF on +#define NCNB (0<<2) //cache_off,WR_BUF off +#define AP_RW (3<<10) //supervisor=RW, user=RW +#define AP_RO (2<<10) //supervisor=RW, user=RO -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) +#define DOMAIN_FAULT (0x0) +#define DOMAIN_CHK (0x1) +#define DOMAIN_NOTCHK (0x3) +#define DOMAIN0 (0x0<<5) +#define DOMAIN1 (0x1<<5) -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) +#define DOMAIN0_ATTR (DOMAIN_CHK<<0) +#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) +#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) +#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) +#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) +#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) #ifdef __GNUC__ void mmu_setttbase(register rt_uint32_t i) { - asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); + asm volatile ("mcr p15, 0, %0, c2, c0, 0": :"r" (i)); } void mmu_set_domain(register rt_uint32_t i) { - asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); + asm volatile ("mcr p15,0, %0, c3, c0, 0": :"r" (i)); } void mmu_enable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= 0x1; + i |= 0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~0x1; + i &= ~0x1; - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 12); + i |= (1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 2); + i |= (1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_icache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 12); + i &= ~(1 << 12); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_dcache() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 2); + i &= ~(1 << 2); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_enable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i |= (1 << 1); + i |= (1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_disable_alignfault() { - register rt_uint32_t i; + register rt_uint32_t i; - /* read control register */ - asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + /* read control register */ + asm volatile ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - i &= ~(1 << 1); + i &= ~(1 << 1); - /* write back to control register */ - asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); + /* write back to control register */ + asm volatile ("mcr p15, 0, %0, c1, c0, 0": :"r" (i)); } void mmu_clean_invalidated_cache_index(int index) { - asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); + asm volatile ("mcr p15, 0, %0, c7, c14, 2": :"r" (index)); } void mmu_invalidate_tlb() { - asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c8, c7, 0": :"r" (0)); } void mmu_invalidate_icache() { - asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); + asm volatile ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); } #endif @@ -320,71 +320,71 @@ void mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr) nSec=(vaddrEnd>>20)-(vaddrStart>>20); for(i=0;i<=nSec;i++) { - *pTT = attr |(((paddrStart>>20)+i)<<20); - pTT++; + *pTT = attr |(((paddrStart>>20)+i)<<20); + pTT++; } } void rt_hw_mmu_init(void) { - int i,j; - //========================== IMPORTANT NOTE ========================= - //The current stack and code area can't be re-mapped in this routine. - //If you want memory map mapped freely, your own sophiscated mmu - //initialization code is needed. - //=================================================================== + int i,j; + //========================== IMPORTANT NOTE ========================= + //The current stack and code area can't be re-mapped in this routine. + //If you want memory map mapped freely, your own sophiscated mmu + //initialization code is needed. + //=================================================================== - mmu_disable_dcache(); - mmu_disable_icache(); + mmu_disable_dcache(); + mmu_disable_icache(); - //If write-back is used,the DCache should be cleared. - for(i=0;i<64;i++) - for(j=0;j<8;j++) - mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); + //If write-back is used,the DCache should be cleared. + for(i=0;i<64;i++) + for(j=0;j<8;j++) + mmu_clean_invalidated_cache_index((i<<26)|(j<<5)); - mmu_invalidate_icache(); + mmu_invalidate_icache(); - //To complete mmu_Init() fast, Icache may be turned on here. - mmu_enable_icache(); + //To complete mmu_Init() fast, Icache may be turned on here. + mmu_enable_icache(); - mmu_disable(); - mmu_invalidate_tlb(); + mmu_disable(); + mmu_invalidate_tlb(); - //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); - mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 - mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 - mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 - mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 - mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 - mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 - //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 - mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 - mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 - //30f00000->30100000, 31000000->30200000 - mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 - mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 + //mmu_setmtt(int vaddrStart,int vaddrEnd,int paddrStart,int attr); + mmu_setmtt(0x00000000,0x07f00000,0x00000000,RW_CNB); //bank0 + mmu_setmtt(0x00000000,0x03f00000,(int)0x30000000,RW_CB); //bank0 + mmu_setmtt(0x04000000,0x07f00000,0,RW_NCNB); //bank0 + mmu_setmtt(0x08000000,0x0ff00000,0x08000000,RW_CNB); //bank1 + mmu_setmtt(0x10000000,0x17f00000,0x10000000,RW_NCNB); //bank2 + mmu_setmtt(0x18000000,0x1ff00000,0x18000000,RW_NCNB); //bank3 + //mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_CB); //bank4 + mmu_setmtt(0x20000000,0x27f00000,0x20000000,RW_NCNB); //bank4 for DM9000 + mmu_setmtt(0x28000000,0x2ff00000,0x28000000,RW_NCNB); //bank5 + //30f00000->30100000, 31000000->30200000 + mmu_setmtt(0x30000000,0x30100000,0x30000000,RW_CB); //bank6-1 + mmu_setmtt(0x30200000,0x33e00000,0x30200000,RW_CB); //bank6-2 - mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 - mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 + mmu_setmtt(0x33f00000,0x34000000,0x33f00000,RW_NCNB); //bank6-3 + mmu_setmtt(0x38000000,0x3ff00000,0x38000000,RW_NCNB); //bank7 - mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR - mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR - mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR - mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used - mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR + mmu_setmtt(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR + mmu_setmtt(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR + mmu_setmtt(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR + mmu_setmtt(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used + mmu_setmtt(0x60000000,0x67f00000,0x60000000,RW_NCNB); //SFR - mmu_setttbase(_MMUTT_STARTADDRESS); + mmu_setttbase(_MMUTT_STARTADDRESS); - /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ - mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); + /* DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked) */ + mmu_set_domain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); - mmu_enable_alignfault(); + mmu_enable_alignfault(); - mmu_enable(); + mmu_enable(); - /* ICache enable */ - mmu_enable_icache(); - /* DCache should be turned on after mmu is turned on. */ - mmu_enable_dcache(); + /* ICache enable */ + mmu_enable_icache(); + /* DCache should be turned on after mmu is turned on. */ + mmu_enable_dcache(); } diff --git a/libcpu/arm/s3c24x0/rtc.c b/libcpu/arm/s3c24x0/rtc.c index d0c80bce6b..0f9484405c 100644 --- a/libcpu/arm/s3c24x0/rtc.c +++ b/libcpu/arm/s3c24x0/rtc.c @@ -1,66 +1,66 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2009-04-26 yi.qiu first version - * 2010-03-18 Gary Lee add functions such as GregorianDay - * and rtc_time_to_tm - * 2009-03-20 yi.qiu clean up + * 2009-04-26 yi.qiu first version + * 2010-03-18 Gary Lee add functions such as GregorianDay + * and rtc_time_to_tm + * 2009-03-20 yi.qiu clean up */ #include <rtthread.h> -#include <time.h> +#include <sys/time.h> #include <s3c24x0.h> // #define RTC_DEBUG -#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */ -#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */ -#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) -#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10)) +#define RTC_ENABLE RTCCON |= 0x01; /*RTC read and write enable */ +#define RTC_DISABLE RTCCON &= ~0x01; /* RTC read and write disable */ +#define BCD2BIN(n) (((((n) >> 4) & 0x0F) * 10) + ((n) & 0x0F)) +#define BIN2BCD(n) ((((n) / 10) << 4) | ((n) % 10)) /** * This function get rtc time */ void rt_hw_rtc_get(struct tm *ti) { - rt_uint8_t sec, min, hour, mday, wday, mon, year; + rt_uint8_t sec, min, hour, mday, wday, mon, year; - /* enable access to RTC registers */ - RTCCON |= RTC_ENABLE; + /* enable access to RTC registers */ + RTCCON |= RTC_ENABLE; - /* read RTC registers */ - do - { - sec = BCDSEC; - min = BCDMIN; - hour = BCDHOUR; - mday = BCDDATE; - wday = BCDDAY; - mon = BCDMON; - year = BCDYEAR; + /* read RTC registers */ + do + { + sec = BCDSEC; + min = BCDMIN; + hour = BCDHOUR; + mday = BCDDATE; + wday = BCDDAY; + mon = BCDMON; + year = BCDYEAR; } while (sec != BCDSEC); #ifdef RTC_DEBUG - rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n", - sec, min, hour, mday, wday, mon, year); + rt_kprintf("sec:%x min:%x hour:%x mday:%x wday:%x mon:%x year:%x\n", + sec, min, hour, mday, wday, mon, year); #endif - /* disable access to RTC registers */ - RTC_DISABLE + /* disable access to RTC registers */ + RTC_DISABLE - ti->tm_sec = BCD2BIN(sec & 0x7F); - ti->tm_min = BCD2BIN(min & 0x7F); - ti->tm_hour = BCD2BIN(hour & 0x3F); - ti->tm_mday = BCD2BIN(mday & 0x3F); - ti->tm_mon = BCD2BIN(mon & 0x1F); - ti->tm_year = BCD2BIN(year); - ti->tm_wday = BCD2BIN(wday & 0x07); - ti->tm_yday = 0; - ti->tm_isdst = 0; + ti->tm_sec = BCD2BIN(sec & 0x7F); + ti->tm_min = BCD2BIN(min & 0x7F); + ti->tm_hour = BCD2BIN(hour & 0x3F); + ti->tm_mday = BCD2BIN(mday & 0x3F); + ti->tm_mon = BCD2BIN(mon & 0x1F); + ti->tm_year = BCD2BIN(year); + ti->tm_wday = BCD2BIN(wday & 0x07); + ti->tm_yday = 0; + ti->tm_isdst = 0; } /** @@ -68,32 +68,32 @@ void rt_hw_rtc_get(struct tm *ti) */ void rt_hw_rtc_set(struct tm *ti) { - rt_uint8_t sec, min, hour, mday, wday, mon, year; + rt_uint8_t sec, min, hour, mday, wday, mon, year; - year = BIN2BCD(ti->tm_year); - mon = BIN2BCD(ti->tm_mon); - wday = BIN2BCD(ti->tm_wday); - mday = BIN2BCD(ti->tm_mday); - hour = BIN2BCD(ti->tm_hour); - min = BIN2BCD(ti->tm_min); - sec = BIN2BCD(ti->tm_sec); + year = BIN2BCD(ti->tm_year); + mon = BIN2BCD(ti->tm_mon); + wday = BIN2BCD(ti->tm_wday); + mday = BIN2BCD(ti->tm_mday); + hour = BIN2BCD(ti->tm_hour); + min = BIN2BCD(ti->tm_min); + sec = BIN2BCD(ti->tm_sec); - /* enable access to RTC registers */ - RTC_ENABLE + /* enable access to RTC registers */ + RTC_ENABLE - do{ - /* write RTC registers */ - BCDSEC = sec; - BCDMIN = min; - BCDHOUR = hour; - BCDDATE = mday; - BCDDAY = wday; - BCDMON = mon; - BCDYEAR = year; - }while (sec != BCDSEC); - - /* disable access to RTC registers */ - RTC_DISABLE + do{ + /* write RTC registers */ + BCDSEC = sec; + BCDMIN = min; + BCDHOUR = hour; + BCDDATE = mday; + BCDDAY = wday; + BCDMON = mon; + BCDYEAR = year; + }while (sec != BCDSEC); + + /* disable access to RTC registers */ + RTC_DISABLE } /** @@ -101,85 +101,85 @@ void rt_hw_rtc_set(struct tm *ti) */ void rt_hw_rtc_reset (void) { - RTCCON = (RTCCON & ~0x06) | 0x08; - RTCCON &= ~(0x08|0x01); + RTCCON = (RTCCON & ~0x06) | 0x08; + RTCCON &= ~(0x08|0x01); } static struct rt_device rtc; static rt_err_t rtc_open(rt_device_t dev, rt_uint16_t oflag) { - RTC_ENABLE - return RT_EOK; + RTC_ENABLE + return RT_EOK; } static rt_err_t rtc_close(rt_device_t dev) { - RTC_DISABLE - return RT_EOK; + RTC_DISABLE + return RT_EOK; } static rt_size_t rtc_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - return RT_EOK; + return RT_EOK; } static rt_err_t rtc_control(rt_device_t dev, int cmd, void *args) { - struct tm tm, *tm_ptr; + struct tm tm, *tm_ptr; time_t *time; - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - time = (time_t *)args; - switch (cmd) - { - case RT_DEVICE_CTRL_RTC_GET_TIME: - /* read device */ - rt_hw_rtc_get(&tm); - *((rt_time_t *)args) = mktime(&tm); - break; + time = (time_t *)args; + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + /* read device */ + rt_hw_rtc_get(&tm); + *((rt_time_t *)args) = timegm(&tm); + break; - case RT_DEVICE_CTRL_RTC_SET_TIME: - tm_ptr = localtime(time); - /* write device */ - rt_hw_rtc_set(tm_ptr); - break; - } + case RT_DEVICE_CTRL_RTC_SET_TIME: + /* write device */ + tm_ptr = gmtime(time); + rt_hw_rtc_set(tm_ptr); + break; + } - return RT_EOK; + return RT_EOK; } void rt_hw_rtc_init(void) { - rtc.type = RT_Device_Class_RTC; + rtc.type = RT_Device_Class_RTC; + + /* register rtc device */ + rtc.init = RT_NULL; + rtc.open = rtc_open; + rtc.close = rtc_close; + rtc.read = rtc_read; + rtc.write = RT_NULL; + rtc.control = rtc_control; + + /* no private */ + rtc.user_data = RT_NULL; - /* register rtc device */ - rtc.init = RT_NULL; - rtc.open = rtc_open; - rtc.close = rtc_close; - rtc.read = rtc_read; - rtc.write = RT_NULL; - rtc.control = rtc_control; - - /* no private */ - rtc.user_data = RT_NULL; - - rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); + rt_device_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); } #ifdef RT_USING_FINSH #include <finsh.h> void list_date() { - time_t time; - rt_device_t device; + time_t time; + rt_device_t device; - device = rt_device_find("rtc"); - if (device != RT_NULL) - { - rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); + device = rt_device_find("rtc"); + if (device != RT_NULL) + { + rt_device_control(device, RT_DEVICE_CTRL_RTC_GET_TIME, &time); - rt_kprintf("%d, %s\n", time, ctime(&time)); - } + rt_kprintf("%d, %s\n", time, ctime(&time)); + } } FINSH_FUNCTION_EXPORT(list_date, list date); #endif diff --git a/libcpu/arm/s3c24x0/rtc.h b/libcpu/arm/s3c24x0/rtc.h index aafa714b0e..78219325a5 100644 --- a/libcpu/arm/s3c24x0/rtc.h +++ b/libcpu/arm/s3c24x0/rtc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/s3c24x0/s3c24x0.h b/libcpu/arm/s3c24x0/s3c24x0.h index 03749c5227..75e1eb0119 100644 --- a/libcpu/arm/s3c24x0/s3c24x0.h +++ b/libcpu/arm/s3c24x0/s3c24x0.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,7 +22,7 @@ extern "C" { */ /*@{*/ -// Memory control +// Memory control #define BWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status #define BANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control #define BANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control @@ -101,7 +101,7 @@ extern "C" { #define CLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control #define CLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control #define CLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control -#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control +#define CAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control // LCD CONTROLLER @@ -114,7 +114,7 @@ extern "C" { #define LCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2 #define LCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set #define REDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table -#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table +#define GREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table #define BLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table #define DITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode #define TPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette @@ -223,10 +223,10 @@ extern "C" { #define TCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4 // Added for 2440 -#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only) -#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0 -#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1 -#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register +#define FLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only) +#define DSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0 +#define DSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1 +#define MSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register // USB DEVICE @@ -388,9 +388,9 @@ extern "C" { #define GPHDAT (*(volatile unsigned *)0x56000074) //Port H data #define GPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H -#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control -#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data -#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J +#define GPJCON (*(volatile unsigned *)0x560000d0) //Port J control +#define GPJDAT (*(volatile unsigned *)0x560000d4) //Port J data +#define GPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J #define MISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control #define DCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control @@ -495,7 +495,7 @@ extern "C" { #ifdef __BIG_ENDIAN /* edited for 2440A */ #define SDIDAT (*(volatile unsigned *)0x5a00004c) #else // Little Endian -#define SDIDAT (*(volatile unsigned *)0x5a000040) +#define SDIDAT (*(volatile unsigned *)0x5a000040) #endif //SD Interface // PENDING BIT @@ -562,40 +562,40 @@ extern "C" { #define ClearPending(bit) {SRCPND = bit;INTPND = bit;INTPND;} //Wait until INTPND is changed for the case that the ISR is very short. -#define INTGLOBAL 32 +#define INTGLOBAL 32 /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define ABORTMODE 0x17 -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 +#define USERMODE 0x10 +#define FIQMODE 0x11 +#define IRQMODE 0x12 +#define SVCMODE 0x13 +#define ABORTMODE 0x17 +#define UNDEFMODE 0x1b +#define MODEMASK 0x1f +#define NOINT 0xc0 struct rt_hw_register { - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; #ifdef __cplusplus diff --git a/libcpu/arm/s3c24x0/stack.c b/libcpu/arm/s3c24x0/stack.c index 82607c3590..99938e2317 100644 --- a/libcpu/arm/s3c24x0/stack.c +++ b/libcpu/arm/s3c24x0/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/s3c24x0/system_clock.c b/libcpu/arm/s3c24x0/system_clock.c index 833b193cce..235c5e5e5c 100644 --- a/libcpu/arm/s3c24x0/system_clock.c +++ b/libcpu/arm/s3c24x0/system_clock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,21 +11,21 @@ #include <rtthread.h> #include "s3c24x0.h" -#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz +#define CONFIG_SYS_CLK_FREQ 12000000 // Fin = 12.00MHz #if CONFIG_SYS_CLK_FREQ == 12000000 - /* MPLL=2*12*100/6=400MHz */ - #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */ - #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */ - #define MPL_SDIV 0 /* s=MPL_SDIV=0 */ - /* UPLL=12*64/8=96MHz */ - #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */ - #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */ - #define UPL_SDIV 1 /* s=UPL_SDIV=1 */ - /* System clock divider FCLK:HCLK:PCLK=1:4:8 */ - #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */ - #define HDIVN 0x2 /* HCLK = FCLK / 4 */ - #define PDIVN 0x1 /* PCLK = HCLK / 2 */ + /* MPLL=2*12*100/6=400MHz */ + #define MPL_MIDV 92 /* m=MPL_MDIV+8=100 */ + #define MPL_PDIV 4 /* p=MPL_PDIV+2=6 */ + #define MPL_SDIV 0 /* s=MPL_SDIV=0 */ + /* UPLL=12*64/8=96MHz */ + #define UPL_MDIV 56 /* m=UPL_MDIV+8=64 */ + #define UPL_PDIV 2 /* p=UPL_PDIV+2=4 */ + #define UPL_SDIV 1 /* s=UPL_SDIV=1 */ + /* System clock divider FCLK:HCLK:PCLK=1:4:8 */ + #define DIVN_UPLL 0x1 /* UCLK = UPLL clock / 2 */ + #define HDIVN 0x2 /* HCLK = FCLK / 4 */ + #define PDIVN 0x1 /* PCLK = HCLK / 2 */ #endif rt_uint32_t PCLK; @@ -35,60 +35,60 @@ rt_uint32_t UCLK; void rt_hw_get_clock(void) { - rt_uint32_t val; - rt_uint8_t m, p, s; + rt_uint32_t val; + rt_uint8_t m, p, s; - val = MPLLCON; - m = (val>>12)&0xff; - p = (val>>4)&0x3f; - s = val&3; + val = MPLLCON; + m = (val>>12)&0xff; + p = (val>>4)&0x3f; + s = val&3; - FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100; + FCLK = ((m+8)*(CONFIG_SYS_CLK_FREQ/100)*2)/((p+2)*(1<<s))*100; - val = CLKDIVN; - m = (val>>1)&3; - p = val&1; + val = CLKDIVN; + m = (val>>1)&3; + p = val&1; - switch (m) { - case 0: - HCLK = FCLK; - break; - case 1: - HCLK = FCLK>>1; - break; - case 2: - if(s&2) - HCLK = FCLK>>3; - else - HCLK = FCLK>>2; - break; - case 3: - if(s&1) - HCLK = FCLK/6; - else - HCLK = FCLK/3; - break; + switch (m) { + case 0: + HCLK = FCLK; + break; + case 1: + HCLK = FCLK>>1; + break; + case 2: + if(s&2) + HCLK = FCLK>>3; + else + HCLK = FCLK>>2; + break; + case 3: + if(s&1) + HCLK = FCLK/6; + else + HCLK = FCLK/3; + break; } - if(p) - PCLK = HCLK>>1; - else - PCLK = HCLK; + if(p) + PCLK = HCLK>>1; + else + PCLK = HCLK; } void rt_hw_set_mpll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) { - MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12); + MPLLCON = sdiv | (pdiv<<4) | (mdiv<<12); } void rt_hw_set_upll_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv) { - UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv; + UPLLCON = (mdiv<<12) | (pdiv<<4) | sdiv; } void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn) { - CLKDIVN = (hdivn<<1) | pdivn; + CLKDIVN = (hdivn<<1) | pdivn; } /** @@ -96,9 +96,9 @@ void rt_hw_set_divider(rt_uint8_t hdivn, rt_uint8_t pdivn) */ void rt_hw_clock_init(void) { - LOCKTIME = 0xFFFFFFFF; - rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV); - rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV); - rt_hw_set_divider(HDIVN, PDIVN); + LOCKTIME = 0xFFFFFFFF; + rt_hw_set_mpll_clock(MPL_SDIV, MPL_PDIV, MPL_MIDV); + rt_hw_set_upll_clock(UPL_SDIV, UPL_PDIV, UPL_MDIV); + rt_hw_set_divider(HDIVN, PDIVN); } diff --git a/libcpu/arm/s3c24x0/trap.c b/libcpu/arm/s3c24x0/trap.c index f2f389c6b0..f0e8a7097a 100644 --- a/libcpu/arm/s3c24x0/trap.c +++ b/libcpu/arm/s3c24x0/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -34,13 +34,13 @@ extern long list_thread(void); void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -53,15 +53,15 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -75,10 +75,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -91,15 +91,15 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -112,15 +112,15 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); #ifdef RT_USING_FINSH - list_thread(); + list_thread(); #endif - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -132,9 +132,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc isr_table[]; @@ -161,13 +161,13 @@ void rt_hw_trap_irq(void) ClearPending(1 << irq); #ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; + isr_table[irq].counter++; #endif /* RT_USING_INTERRUPT_INFO */ } void rt_hw_trap_fiq(void) { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/libcpu/arm/s3c44b0/cpu.c b/libcpu/arm/s3c44b0/cpu.c index 9d60b09688..d80ca054e2 100644 --- a/libcpu/arm/s3c44b0/cpu.c +++ b/libcpu/arm/s3c44b0/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,29 +22,29 @@ */ void rt_hw_cpu_icache_enable() { - rt_base_t reg; + rt_base_t reg; - volatile int i; - /* flush cycle */ - for(i = 0x10002000; i < 0x10004800; i+=16) - { - *((int *)i)=0x0; - } + volatile int i; + /* flush cycle */ + for(i = 0x10002000; i < 0x10004800; i+=16) + { + *((int *)i)=0x0; + } - /* - * Init cache - * Non-cacheable area (everything outside RAM) - * 0x0000:0000 - 0x0C00:0000 - */ - NCACHBE0 = 0xC0000000; - NCACHBE1 = 0x00000000; + /* + * Init cache + * Non-cacheable area (everything outside RAM) + * 0x0000:0000 - 0x0C00:0000 + */ + NCACHBE0 = 0xC0000000; + NCACHBE1 = 0x00000000; - /* - Enable chache - */ - reg = SYSCFG; - reg |= 0x00000006; /* 8kB */ - SYSCFG = reg; + /* + Enable chache + */ + reg = SYSCFG; + reg |= 0x00000006; /* 8kB */ + SYSCFG = reg; } /** @@ -53,11 +53,11 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - rt_base_t reg; + rt_base_t reg; - reg = SYSCFG; - reg &= ~0x00000006; /* 8kB */ - SYSCFG = reg; + reg = SYSCFG; + reg &= ~0x00000006; /* 8kB */ + SYSCFG = reg; } /** @@ -66,7 +66,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return 0; + return 0; } /** @@ -75,7 +75,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - rt_hw_cpu_icache_enable(); + rt_hw_cpu_icache_enable(); } /** @@ -84,7 +84,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - rt_hw_cpu_icache_disable(); + rt_hw_cpu_icache_disable(); } /** @@ -93,7 +93,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return rt_hw_cpu_icache_status(); + return rt_hw_cpu_icache_status(); } /** @@ -110,9 +110,9 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } /*@}*/ diff --git a/libcpu/arm/s3c44b0/interrupt.c b/libcpu/arm/s3c44b0/interrupt.c index 6b3eed4a39..5464011dd2 100644 --- a/libcpu/arm/s3c44b0/interrupt.c +++ b/libcpu/arm/s3c44b0/interrupt.c @@ -1,19 +1,19 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2006-09-06 XuXinming first version - * 2006-09-15 Bernard add interrupt bank 0..3 for more effective + * 2006-09-15 Bernard add interrupt bank 0..3 for more effective * in irq trap */ #include <rtthread.h> #include "s3c44b0.h" -#define MAX_HANDLERS 26 +#define MAX_HANDLERS 26 extern rt_uint32_t rt_interrupt_nest; @@ -34,7 +34,7 @@ unsigned char interrupt_bank3[256]; void rt_hw_interrupt_handle(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -42,70 +42,70 @@ void rt_hw_interrupt_handle(int vector) */ void rt_hw_interrupt_init() { - register int i; + register int i; - /* all interrupt disabled include global bit */ - INTMSK = 0x07ffffff; - - /* clear pending register */ - I_ISPC = 0x03ffffff; - - /* non-vector mode IRQ enable */ - INTCON = 0x5; - - /* all IRQ mode */ - INTMOD = 0x0; + /* all interrupt disabled include global bit */ + INTMSK = 0x07ffffff; - /* init exceptions table */ - for(i=0; i<MAX_HANDLERS; i++) - { - isr_table[i] = rt_hw_interrupt_handle; - } + /* clear pending register */ + I_ISPC = 0x03ffffff; - for ( i = 0; i < 256; i++) - { - interrupt_bank0[i] = 0; - interrupt_bank1[i] = 0; - interrupt_bank2[i] = 0; - interrupt_bank3[i] = 0; - } + /* non-vector mode IRQ enable */ + INTCON = 0x5; - /* setup interrupt bank table */ - interrupt_bank0[1] = 0; - interrupt_bank0[2] = 1; - interrupt_bank0[4] = 2; - interrupt_bank0[8] = 3; - interrupt_bank0[16] = 4; - interrupt_bank0[32] = 5; - interrupt_bank0[64] = 6; - interrupt_bank0[128]= 7; + /* all IRQ mode */ + INTMOD = 0x0; - interrupt_bank1[1] = 8; - interrupt_bank1[2] = 9; - interrupt_bank1[4] = 10; - interrupt_bank1[8] = 11; - interrupt_bank1[16] = 12; - interrupt_bank1[32] = 13; - interrupt_bank1[64] = 14; - interrupt_bank1[128]= 15; + /* init exceptions table */ + for(i=0; i<MAX_HANDLERS; i++) + { + isr_table[i] = rt_hw_interrupt_handle; + } - interrupt_bank2[1] = 16; - interrupt_bank2[2] = 17; - interrupt_bank2[4] = 18; - interrupt_bank2[8] = 19; - interrupt_bank2[16] = 20; - interrupt_bank2[32] = 21; - interrupt_bank2[64] = 22; - interrupt_bank2[128]= 23; + for ( i = 0; i < 256; i++) + { + interrupt_bank0[i] = 0; + interrupt_bank1[i] = 0; + interrupt_bank2[i] = 0; + interrupt_bank3[i] = 0; + } - interrupt_bank3[1] = 24; - interrupt_bank3[2] = 25; + /* setup interrupt bank table */ + interrupt_bank0[1] = 0; + interrupt_bank0[2] = 1; + interrupt_bank0[4] = 2; + interrupt_bank0[8] = 3; + interrupt_bank0[16] = 4; + interrupt_bank0[32] = 5; + interrupt_bank0[64] = 6; + interrupt_bank0[128]= 7; - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + interrupt_bank1[1] = 8; + interrupt_bank1[2] = 9; + interrupt_bank1[4] = 10; + interrupt_bank1[8] = 11; + interrupt_bank1[16] = 12; + interrupt_bank1[32] = 13; + interrupt_bank1[64] = 14; + interrupt_bank1[128]= 15; + + interrupt_bank2[1] = 16; + interrupt_bank2[2] = 17; + interrupt_bank2[4] = 18; + interrupt_bank2[8] = 19; + interrupt_bank2[16] = 20; + interrupt_bank2[32] = 21; + interrupt_bank2[64] = 22; + interrupt_bank2[128]= 23; + + interrupt_bank3[1] = 24; + interrupt_bank3[2] = 25; + + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -114,7 +114,7 @@ void rt_hw_interrupt_init() */ void rt_hw_interrupt_mask(int vector) { - INTMSK |= 1 << vector; + INTMSK |= 1 << vector; } /** @@ -123,7 +123,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - INTMSK &= ~(1 << vector); + INTMSK &= ~(1 << vector); } /** @@ -134,11 +134,11 @@ void rt_hw_interrupt_umask(int vector) */ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) { - if(vector < MAX_HANDLERS) - { - if (old_handler != RT_NULL) *old_handler = isr_table[vector]; - if (new_handler != RT_NULL) isr_table[vector] = new_handler; - } + if(vector < MAX_HANDLERS) + { + if (old_handler != RT_NULL) *old_handler = isr_table[vector]; + if (new_handler != RT_NULL) isr_table[vector] = new_handler; + } } /*@}*/ diff --git a/libcpu/arm/s3c44b0/s3c44b0.h b/libcpu/arm/s3c44b0/s3c44b0.h index 7b854b718a..a40946b573 100644 --- a/libcpu/arm/s3c44b0/s3c44b0.h +++ b/libcpu/arm/s3c44b0/s3c44b0.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -22,315 +22,315 @@ extern "C" { /*@{*/ /*------------------------------------------------------------------------ - * ASIC Address Definition + * ASIC Address Definition *----------------------------------------------------------------------*/ -#define S3C_REG *(volatile unsigned int *) -#define S3C_REGW *(volatile unsigned short *) -#define S3C_REGB *(volatile unsigned char *) +#define S3C_REG *(volatile unsigned int *) +#define S3C_REGW *(volatile unsigned short *) +#define S3C_REGB *(volatile unsigned char *) /* System */ -#define SYSCFG (S3C_REG(0x1c00000)) +#define SYSCFG (S3C_REG(0x1c00000)) /* Cache */ -#define NCACHBE0 (S3C_REG(0x1c00004)) -#define NCACHBE1 (S3C_REG(0x1c00008)) +#define NCACHBE0 (S3C_REG(0x1c00004)) +#define NCACHBE1 (S3C_REG(0x1c00008)) /* Bus control */ -#define SBUSCON (S3C_REG(0x1c40000)) +#define SBUSCON (S3C_REG(0x1c40000)) /* Memory control */ -#define BWSCON (S3C_REG(0x1c80000)) -#define BANKCON0 (S3C_REG(0x1c80004)) -#define BANKCON1 (S3C_REG(0x1c80008)) -#define BANKCON2 (S3C_REG(0x1c8000c)) -#define BANKCON3 (S3C_REG(0x1c80010)) -#define BANKCON4 (S3C_REG(0x1c80014)) -#define BANKCON5 (S3C_REG(0x1c80018)) -#define BANKCON6 (S3C_REG(0x1c8001c)) -#define BANKCON7 (S3C_REG(0x1c80020)) -#define REFRESH (S3C_REG(0x1c80024)) -#define BANKSIZE (S3C_REG(0x1c80028)) -#define MRSRB6 (S3C_REG(0x1c8002c)) -#define MRSRB7 (S3C_REG(0x1c80030)) +#define BWSCON (S3C_REG(0x1c80000)) +#define BANKCON0 (S3C_REG(0x1c80004)) +#define BANKCON1 (S3C_REG(0x1c80008)) +#define BANKCON2 (S3C_REG(0x1c8000c)) +#define BANKCON3 (S3C_REG(0x1c80010)) +#define BANKCON4 (S3C_REG(0x1c80014)) +#define BANKCON5 (S3C_REG(0x1c80018)) +#define BANKCON6 (S3C_REG(0x1c8001c)) +#define BANKCON7 (S3C_REG(0x1c80020)) +#define REFRESH (S3C_REG(0x1c80024)) +#define BANKSIZE (S3C_REG(0x1c80028)) +#define MRSRB6 (S3C_REG(0x1c8002c)) +#define MRSRB7 (S3C_REG(0x1c80030)) /* UART */ -#define ULCON0 (S3C_REG(0x1d00000)) -#define ULCON1 (S3C_REG(0x1d04000)) -#define UCON0 (S3C_REG(0x1d00004)) -#define UCON1 (S3C_REG(0x1d04004)) -#define UFCON0 (S3C_REG(0x1d00008)) -#define UFCON1 (S3C_REG(0x1d04008)) -#define UMCON0 (S3C_REG(0x1d0000c)) -#define UMCON1 (S3C_REG(0x1d0400c)) -#define UTRSTAT0 (S3C_REG(0x1d00010)) -#define UTRSTAT1 (S3C_REG(0x1d04010)) -#define UERSTAT0 (S3C_REG(0x1d00014)) -#define UERSTAT1 (S3C_REG(0x1d04014)) -#define UFSTAT0 (S3C_REG(0x1d00018)) -#define UFSTAT1 (S3C_REG(0x1d04018)) -#define UMSTAT0 (S3C_REG(0x1d0001c)) -#define UMSTAT1 (S3C_REG(0x1d0401c)) -#define UBRDIV0 (S3C_REG(0x1d00028)) -#define UBRDIV1 (S3C_REG(0x1d04028)) +#define ULCON0 (S3C_REG(0x1d00000)) +#define ULCON1 (S3C_REG(0x1d04000)) +#define UCON0 (S3C_REG(0x1d00004)) +#define UCON1 (S3C_REG(0x1d04004)) +#define UFCON0 (S3C_REG(0x1d00008)) +#define UFCON1 (S3C_REG(0x1d04008)) +#define UMCON0 (S3C_REG(0x1d0000c)) +#define UMCON1 (S3C_REG(0x1d0400c)) +#define UTRSTAT0 (S3C_REG(0x1d00010)) +#define UTRSTAT1 (S3C_REG(0x1d04010)) +#define UERSTAT0 (S3C_REG(0x1d00014)) +#define UERSTAT1 (S3C_REG(0x1d04014)) +#define UFSTAT0 (S3C_REG(0x1d00018)) +#define UFSTAT1 (S3C_REG(0x1d04018)) +#define UMSTAT0 (S3C_REG(0x1d0001c)) +#define UMSTAT1 (S3C_REG(0x1d0401c)) +#define UBRDIV0 (S3C_REG(0x1d00028)) +#define UBRDIV1 (S3C_REG(0x1d04028)) -#define UTXH0 (S3C_REGB(0x1d00020)) -#define UTXH1 (S3C_REGB(0x1d04020)) -#define URXH0 (S3C_REGB(0x1d00024)) -#define URXH1 (S3C_REGB(0x1d04024)) +#define UTXH0 (S3C_REGB(0x1d00020)) +#define UTXH1 (S3C_REGB(0x1d04020)) +#define URXH0 (S3C_REGB(0x1d00024)) +#define URXH1 (S3C_REGB(0x1d04024)) /* SIO */ -#define SIOCON (S3C_REG(0x1d14000)) -#define SIODAT (S3C_REG(0x1d14004)) -#define SBRDR (S3C_REG(0x1d14008)) -#define IVTCNT (S3C_REG(0x1d1400c)) -#define DCNTZ (S3C_REG(0x1d14010)) +#define SIOCON (S3C_REG(0x1d14000)) +#define SIODAT (S3C_REG(0x1d14004)) +#define SBRDR (S3C_REG(0x1d14008)) +#define IVTCNT (S3C_REG(0x1d1400c)) +#define DCNTZ (S3C_REG(0x1d14010)) /* IIS */ -#define IISCON (S3C_REG(0x1d18000)) -#define IISMOD (S3C_REG(0x1d18004)) -#define IISPSR (S3C_REG(0x1d18008)) -#define IISFCON (S3C_REG(0x1d1800c)) +#define IISCON (S3C_REG(0x1d18000)) +#define IISMOD (S3C_REG(0x1d18004)) +#define IISPSR (S3C_REG(0x1d18008)) +#define IISFCON (S3C_REG(0x1d1800c)) -#define IISFIF (S3C_REQW(0x1d18010)) +#define IISFIF (S3C_REQW(0x1d18010)) /* I/O Port */ -#define PCONA (S3C_REG(0x1d20000)) -#define PDATA (S3C_REG(0x1d20004)) +#define PCONA (S3C_REG(0x1d20000)) +#define PDATA (S3C_REG(0x1d20004)) -#define PCONB (S3C_REG(0x1d20008)) -#define PDATB (S3C_REG(0x1d2000c)) +#define PCONB (S3C_REG(0x1d20008)) +#define PDATB (S3C_REG(0x1d2000c)) -#define PCONC (S3C_REG(0x1d20010)) -#define PDATC (S3C_REG(0x1d20014)) -#define PUPC (S3C_REG(0x1d20018)) +#define PCONC (S3C_REG(0x1d20010)) +#define PDATC (S3C_REG(0x1d20014)) +#define PUPC (S3C_REG(0x1d20018)) -#define PCOND (S3C_REG(0x1d2001c)) -#define PDATD (S3C_REG(0x1d20020)) -#define PUPD (S3C_REG(0x1d20024)) +#define PCOND (S3C_REG(0x1d2001c)) +#define PDATD (S3C_REG(0x1d20020)) +#define PUPD (S3C_REG(0x1d20024)) -#define PCONE (S3C_REG(0x1d20028)) -#define PDATE (S3C_REG(0x1d2002c)) -#define PUPE (S3C_REG(0x1d20030)) +#define PCONE (S3C_REG(0x1d20028)) +#define PDATE (S3C_REG(0x1d2002c)) +#define PUPE (S3C_REG(0x1d20030)) -#define PCONF (S3C_REG(0x1d20034)) -#define PDATF (S3C_REG(0x1d20038)) -#define PUPF (S3C_REG(0x1d2003c)) +#define PCONF (S3C_REG(0x1d20034)) +#define PDATF (S3C_REG(0x1d20038)) +#define PUPF (S3C_REG(0x1d2003c)) -#define PCONG (S3C_REG(0x1d20040)) -#define PDATG (S3C_REG(0x1d20044)) -#define PUPG (S3C_REG(0x1d20048)) +#define PCONG (S3C_REG(0x1d20040)) +#define PDATG (S3C_REG(0x1d20044)) +#define PUPG (S3C_REG(0x1d20048)) -#define SPUCR (S3C_REG(0x1d2004c)) -#define EXTINT (S3C_REG(0x1d20050)) -#define EXTINTPND (S3C_REG(0x1d20054)) +#define SPUCR (S3C_REG(0x1d2004c)) +#define EXTINT (S3C_REG(0x1d20050)) +#define EXTINTPND (S3C_REG(0x1d20054)) /* Watchdog */ -#define WTCON (S3C_REG(0x1d30000)) -#define WTDAT (S3C_REG(0x1d30004)) -#define WTCNT (S3C_REG(0x1d30008)) +#define WTCON (S3C_REG(0x1d30000)) +#define WTDAT (S3C_REG(0x1d30004)) +#define WTCNT (S3C_REG(0x1d30008)) /* ADC */ -#define ADCCON (S3C_REG(0x1d40000)) -#define ADCPSR (S3C_REG(0x1d40004)) -#define ADCDAT (S3C_REG(0x1d40008)) +#define ADCCON (S3C_REG(0x1d40000)) +#define ADCPSR (S3C_REG(0x1d40004)) +#define ADCDAT (S3C_REG(0x1d40008)) /* Timer */ -#define TCFG0 (S3C_REG(0x1d50000)) -#define TCFG1 (S3C_REG(0x1d50004)) -#define TCON (S3C_REG(0x1d50008)) +#define TCFG0 (S3C_REG(0x1d50000)) +#define TCFG1 (S3C_REG(0x1d50004)) +#define TCON (S3C_REG(0x1d50008)) -#define TCNTB0 (S3C_REG(0x1d5000c)) -#define TCMPB0 (S3C_REG(0x1d50010)) -#define TCNTO0 (S3C_REG(0x1d50014)) +#define TCNTB0 (S3C_REG(0x1d5000c)) +#define TCMPB0 (S3C_REG(0x1d50010)) +#define TCNTO0 (S3C_REG(0x1d50014)) -#define TCNTB1 (S3C_REG(0x1d50018)) -#define TCMPB1 (S3C_REG(0x1d5001c)) -#define TCNTO1 (S3C_REG(0x1d50020)) +#define TCNTB1 (S3C_REG(0x1d50018)) +#define TCMPB1 (S3C_REG(0x1d5001c)) +#define TCNTO1 (S3C_REG(0x1d50020)) -#define TCNTB2 (S3C_REG(0x1d50024)) -#define TCMPB2 (S3C_REG(0x1d50028)) -#define TCNTO2 (S3C_REG(0x1d5002c)) +#define TCNTB2 (S3C_REG(0x1d50024)) +#define TCMPB2 (S3C_REG(0x1d50028)) +#define TCNTO2 (S3C_REG(0x1d5002c)) -#define TCNTB3 (S3C_REG(0x1d50030)) -#define TCMPB3 (S3C_REG(0x1d50034)) -#define TCNTO3 (S3C_REG(0x1d50038)) +#define TCNTB3 (S3C_REG(0x1d50030)) +#define TCMPB3 (S3C_REG(0x1d50034)) +#define TCNTO3 (S3C_REG(0x1d50038)) -#define TCNTB4 (S3C_REG(0x1d5003c)) -#define TCMPB4 (S3C_REG(0x1d50040)) -#define TCNTO4 (S3C_REG(0x1d50044)) +#define TCNTB4 (S3C_REG(0x1d5003c)) +#define TCMPB4 (S3C_REG(0x1d50040)) +#define TCNTO4 (S3C_REG(0x1d50044)) -#define TCNTB5 (S3C_REG(0x1d50048)) -#define TCNTO5 (S3C_REG(0x1d5004c)) +#define TCNTB5 (S3C_REG(0x1d50048)) +#define TCNTO5 (S3C_REG(0x1d5004c)) /* IIC */ -#define IICCON (S3C_REG(0x1d60000)) -#define IICSTAT (S3C_REG(0x1d60004)) -#define IICADD (S3C_REG(0x1d60008)) -#define IICDS (S3C_REG(0x1d6000c)) +#define IICCON (S3C_REG(0x1d60000)) +#define IICSTAT (S3C_REG(0x1d60004)) +#define IICADD (S3C_REG(0x1d60008)) +#define IICDS (S3C_REG(0x1d6000c)) /* RTC */ -#define RTCCON (S3C_REGB(0x1d70040) -#define RTCALM (S3C_REGB(0x1d70050) -#define ALMSEC (S3C_REGB(0x1d70054) -#define ALMMIN (S3C_REGB(0x1d70058) -#define ALMHOUR (S3C_REGB(0x1d7005c) -#define ALMDAY (S3C_REGB(0x1d70060) -#define ALMMON (S3C_REGB(0x1d70064) -#define ALMYEAR (S3C_REGB(0x1d70068) -#define RTCRST (S3C_REGB(0x1d7006c) -#define BCDSEC (S3C_REGB(0x1d70070) -#define BCDMIN (S3C_REGB(0x1d70074) -#define BCDHOUR (S3C_REGB(0x1d70078) -#define BCDDAY (S3C_REGB(0x1d7007c) -#define BCDDATE (S3C_REGB(0x1d70080) -#define BCDMON (S3C_REGB(0x1d70084) -#define BCDYEAR (S3C_REGB(0x1d70088) -#define TICINT (S3C_REGB(0x1d7008c) +#define RTCCON (S3C_REGB(0x1d70040) +#define RTCALM (S3C_REGB(0x1d70050) +#define ALMSEC (S3C_REGB(0x1d70054) +#define ALMMIN (S3C_REGB(0x1d70058) +#define ALMHOUR (S3C_REGB(0x1d7005c) +#define ALMDAY (S3C_REGB(0x1d70060) +#define ALMMON (S3C_REGB(0x1d70064) +#define ALMYEAR (S3C_REGB(0x1d70068) +#define RTCRST (S3C_REGB(0x1d7006c) +#define BCDSEC (S3C_REGB(0x1d70070) +#define BCDMIN (S3C_REGB(0x1d70074) +#define BCDHOUR (S3C_REGB(0x1d70078) +#define BCDDAY (S3C_REGB(0x1d7007c) +#define BCDDATE (S3C_REGB(0x1d70080) +#define BCDMON (S3C_REGB(0x1d70084) +#define BCDYEAR (S3C_REGB(0x1d70088) +#define TICINT (S3C_REGB(0x1d7008c) /* Clock & Power management */ -#define PLLCON (S3C_REG(0x1d80000)) -#define CLKCON (S3C_REG(0x1d80004)) -#define CLKSLOW (S3C_REG(0x1d80008)) -#define LOCKTIME (S3C_REG(0x1d8000c)) +#define PLLCON (S3C_REG(0x1d80000)) +#define CLKCON (S3C_REG(0x1d80004)) +#define CLKSLOW (S3C_REG(0x1d80008)) +#define LOCKTIME (S3C_REG(0x1d8000c)) /* Interrupt */ -#define INTCON (S3C_REG(0x1e00000)) -#define INTPND (S3C_REG(0x1e00004)) -#define INTMOD (S3C_REG(0x1e00008)) -#define INTMSK (S3C_REG(0x1e0000c)) +#define INTCON (S3C_REG(0x1e00000)) +#define INTPND (S3C_REG(0x1e00004)) +#define INTMOD (S3C_REG(0x1e00008)) +#define INTMSK (S3C_REG(0x1e0000c)) -#define I_PSLV (S3C_REG(0x1e00010)) -#define I_PMST (S3C_REG(0x1e00014)) -#define I_CSLV (S3C_REG(0x1e00018)) -#define I_CMST (S3C_REG(0x1e0001c)) -#define I_ISPR (S3C_REG(0x1e00020)) -#define I_ISPC (S3C_REG(0x1e00024)) +#define I_PSLV (S3C_REG(0x1e00010)) +#define I_PMST (S3C_REG(0x1e00014)) +#define I_CSLV (S3C_REG(0x1e00018)) +#define I_CMST (S3C_REG(0x1e0001c)) +#define I_ISPR (S3C_REG(0x1e00020)) +#define I_ISPC (S3C_REG(0x1e00024)) -#define F_ISPR (S3C_REG(0x1e00038)) -#define F_ISPC (S3C_REG(0x1e0003c)) +#define F_ISPR (S3C_REG(0x1e00038)) +#define F_ISPC (S3C_REG(0x1e0003c)) /********************************/ /* LCD Controller Registers */ /********************************/ -#define LCDCON1 (S3C_REG(0x300000)) -#define LCDCON2 (S3C_REG(0x300004)) -#define LCDSADDR1 (S3C_REG(0x300008)) -#define LCDSADDR2 (S3C_REG(0x30000c)) -#define LCDSADDR3 (S3C_REG(0x300010)) -#define REDLUT (S3C_REG(0x300014)) -#define GREENLUT (S3C_REG(0x300018)) -#define BLUELUT (S3C_REG(0x30001c)) -#define DP1_2 (S3C_REG(0x300020)) -#define DP4_7 (S3C_REG(0x300024)) -#define DP3_5 (S3C_REG(0x300028)) -#define DP2_3 (S3C_REG(0x30002c)) -#define DP5_7 (S3C_REG(0x300030)) -#define DP3_4 (S3C_REG(0x300034)) -#define DP4_5 (S3C_REG(0x300038)) -#define DP6_7 (S3C_REG(0x30003c)) -#define LCDCON3 (S3C_REG(0x300040)) -#define DITHMODE (S3C_REG(0x300044)) +#define LCDCON1 (S3C_REG(0x300000)) +#define LCDCON2 (S3C_REG(0x300004)) +#define LCDSADDR1 (S3C_REG(0x300008)) +#define LCDSADDR2 (S3C_REG(0x30000c)) +#define LCDSADDR3 (S3C_REG(0x300010)) +#define REDLUT (S3C_REG(0x300014)) +#define GREENLUT (S3C_REG(0x300018)) +#define BLUELUT (S3C_REG(0x30001c)) +#define DP1_2 (S3C_REG(0x300020)) +#define DP4_7 (S3C_REG(0x300024)) +#define DP3_5 (S3C_REG(0x300028)) +#define DP2_3 (S3C_REG(0x30002c)) +#define DP5_7 (S3C_REG(0x300030)) +#define DP3_4 (S3C_REG(0x300034)) +#define DP4_5 (S3C_REG(0x300038)) +#define DP6_7 (S3C_REG(0x30003c)) +#define LCDCON3 (S3C_REG(0x300040)) +#define DITHMODE (S3C_REG(0x300044)) /* ZDMA0 */ -#define ZDCON0 (S3C_REG(0x1e80000)) -#define ZDISRC0 (S3C_REG(0x1e80004)) -#define ZDIDES0 (S3C_REG(0x1e80008)) -#define ZDICNT0 (S3C_REG(0x1e8000c)) -#define ZDCSRC0 (S3C_REG(0x1e80010)) -#define ZDCDES0 (S3C_REG(0x1e80014)) -#define ZDCCNT0 (S3C_REG(0x1e80018)) +#define ZDCON0 (S3C_REG(0x1e80000)) +#define ZDISRC0 (S3C_REG(0x1e80004)) +#define ZDIDES0 (S3C_REG(0x1e80008)) +#define ZDICNT0 (S3C_REG(0x1e8000c)) +#define ZDCSRC0 (S3C_REG(0x1e80010)) +#define ZDCDES0 (S3C_REG(0x1e80014)) +#define ZDCCNT0 (S3C_REG(0x1e80018)) /* ZDMA1 */ -#define ZDCON1 (S3C_REG(0x1e80020)) -#define ZDISRC1 (S3C_REG(0x1e80024)) -#define ZDIDES1 (S3C_REG(0x1e80028)) -#define ZDICNT1 (S3C_REG(0x1e8002c)) -#define ZDCSRC1 (S3C_REG(0x1e80030)) -#define ZDCDES1 (S3C_REG(0x1e80034)) -#define ZDCCNT1 (S3C_REG(0x1e80038)) +#define ZDCON1 (S3C_REG(0x1e80020)) +#define ZDISRC1 (S3C_REG(0x1e80024)) +#define ZDIDES1 (S3C_REG(0x1e80028)) +#define ZDICNT1 (S3C_REG(0x1e8002c)) +#define ZDCSRC1 (S3C_REG(0x1e80030)) +#define ZDCDES1 (S3C_REG(0x1e80034)) +#define ZDCCNT1 (S3C_REG(0x1e80038)) /* BDMA0 */ -#define BDCON0 (S3C_REG(0x1f80000)) -#define BDISRC0 (S3C_REG(0x1f80004)) -#define BDIDES0 (S3C_REG(0x1f80008)) -#define BDICNT0 (S3C_REG(0x1f8000c)) -#define BDCSRC0 (S3C_REG(0x1f80010)) -#define BDCDES0 (S3C_REG(0x1f80014)) -#define BDCCNT0 (S3C_REG(0x1f80018)) +#define BDCON0 (S3C_REG(0x1f80000)) +#define BDISRC0 (S3C_REG(0x1f80004)) +#define BDIDES0 (S3C_REG(0x1f80008)) +#define BDICNT0 (S3C_REG(0x1f8000c)) +#define BDCSRC0 (S3C_REG(0x1f80010)) +#define BDCDES0 (S3C_REG(0x1f80014)) +#define BDCCNT0 (S3C_REG(0x1f80018)) /* BDMA1 */ -#define BDCON1 (S3C_REG(0x1f80020)) -#define BDISRC1 (S3C_REG(0x1f80024)) -#define BDIDES1 (S3C_REG(0x1f80028)) -#define BDICNT1 (S3C_REG(0x1f8002c)) -#define BDCSRC1 (S3C_REG(0x1f80030)) -#define BDCDES1 (S3C_REG(0x1f80034)) -#define BDCCNT1 (S3C_REG(0x1f80038)) +#define BDCON1 (S3C_REG(0x1f80020)) +#define BDISRC1 (S3C_REG(0x1f80024)) +#define BDIDES1 (S3C_REG(0x1f80028)) +#define BDICNT1 (S3C_REG(0x1f8002c)) +#define BDCSRC1 (S3C_REG(0x1f80030)) +#define BDCDES1 (S3C_REG(0x1f80034)) +#define BDCCNT1 (S3C_REG(0x1f80038)) /*****************************/ /* CPU Mode */ /*****************************/ -#define USERMODE 0x10 /* User Mode(USR) */ -#define FIQMODE 0x11 /* Fast Interrupt Mode (FIQ) */ -#define IRQMODE 0x12 /* Interrupt Mode (IRQ) */ -#define SVCMODE 0x13 /* Supervisor Mode (SVC) */ -#define ABORTMODE 0x17 /* Abort Mode(ABT) */ -#define UNDEFMODE 0x1b /* Undefine Mode(UDF) */ -#define MODEMASK 0x1f /* Processor Mode Mask */ -#define NOINT 0xc0 +#define USERMODE 0x10 /* User Mode(USR) */ +#define FIQMODE 0x11 /* Fast Interrupt Mode (FIQ) */ +#define IRQMODE 0x12 /* Interrupt Mode (IRQ) */ +#define SVCMODE 0x13 /* Supervisor Mode (SVC) */ +#define ABORTMODE 0x17 /* Abort Mode(ABT) */ +#define UNDEFMODE 0x1b /* Undefine Mode(UDF) */ +#define MODEMASK 0x1f /* Processor Mode Mask */ +#define NOINT 0xc0 /*****************************/ /* INT Define */ /*****************************/ -#define INT_ADC 0x00 -#define INT_RTC 0x01 -#define INT_UTXD1 0x02 -#define INT_UTXD0 0x03 -#define INT_SIO 0x04 -#define INT_IIC 0x05 -#define INT_URXD1 0x06 -#define INT_URXD0 0x07 -#define INT_TIMER5 0x08 -#define INT_TIMER4 0x09 -#define INT_TIMER3 0x0A -#define INT_TIMER2 0x0B -#define INT_TIMER1 0x0C -#define INT_TIMER0 0x0D -#define INT_UERR01 0x0E -#define INT_WDT 0x1F -#define INT_BDMA1 0x10 -#define INT_BDMA0 0x11 -#define INT_ZDMA1 0x12 -#define INT_ZDMA0 0x13 -#define INT_TICK 0x14 -#define INT_EINT4567 0x15 -#define INT_EINT3 0x16 -#define INT_EINT2 0x17 -#define INT_EINT1 0x18 -#define INT_EINT0 0x19 +#define INT_ADC 0x00 +#define INT_RTC 0x01 +#define INT_UTXD1 0x02 +#define INT_UTXD0 0x03 +#define INT_SIO 0x04 +#define INT_IIC 0x05 +#define INT_URXD1 0x06 +#define INT_URXD0 0x07 +#define INT_TIMER5 0x08 +#define INT_TIMER4 0x09 +#define INT_TIMER3 0x0A +#define INT_TIMER2 0x0B +#define INT_TIMER1 0x0C +#define INT_TIMER0 0x0D +#define INT_UERR01 0x0E +#define INT_WDT 0x1F +#define INT_BDMA1 0x10 +#define INT_BDMA0 0x11 +#define INT_ZDMA1 0x12 +#define INT_ZDMA0 0x13 +#define INT_TICK 0x14 +#define INT_EINT4567 0x15 +#define INT_EINT3 0x16 +#define INT_EINT2 0x17 +#define INT_EINT1 0x18 +#define INT_EINT0 0x19 -#define INT_GLOBAL 26 +#define INT_GLOBAL 26 struct rt_hw_register { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; - unsigned long ORIG_r0; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; + unsigned long ORIG_r0; }; /*@}*/ diff --git a/libcpu/arm/s3c44b0/serial.c b/libcpu/arm/s3c44b0/serial.c index 6af515b027..95f8cb3487 100644 --- a/libcpu/arm/s3c44b0/serial.c +++ b/libcpu/arm/s3c44b0/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,21 +18,21 @@ void rt_serial_init(void); void rt_console_puts(const char* str); void rt_serial_putc(const char c); -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ rt_inline void serial_flush_input(void) { - volatile unsigned int tmp; + volatile unsigned int tmp; - /* keep on reading as long as the receiver is not empty */ - while(UTRSTAT0 & USTAT_RCV_READY) tmp = URXH0; + /* keep on reading as long as the receiver is not empty */ + while(UTRSTAT0 & USTAT_RCV_READY) tmp = URXH0; } rt_inline void serial_flush_output(void) { - /* wait until the transmitter is no longer busy */ - while(!(UTRSTAT0 & USTAT_TXB_EMPTY)) ; + /* wait until the transmitter is no longer busy */ + while(!(UTRSTAT0 & USTAT_TXB_EMPTY)) ; } /** @@ -48,10 +48,10 @@ rt_inline void serial_flush_output(void) */ void rt_console_puts(const char* str) { - while (*str) - { - rt_serial_putc (*str++); - } + while (*str) + { + rt_serial_putc (*str++); + } } /** @@ -59,25 +59,25 @@ void rt_console_puts(const char* str) */ void rt_serial_init() { - rt_uint32_t divisor = 0; + rt_uint32_t divisor = 0; - divisor = 0x20; + divisor = 0x20; - serial_flush_output(); - serial_flush_input(); + serial_flush_output(); + serial_flush_input(); - /* UART interrupt off */ - UCON0 = 0; - /* FIFO disable */ - UFCON0 =0x0; - UMCON0 =0x0; - /* set baudrate */ - UBRDIV0 = divisor; + /* UART interrupt off */ + UCON0 = 0; + /* FIFO disable */ + UFCON0 =0x0; + UMCON0 =0x0; + /* set baudrate */ + UBRDIV0 = divisor; - /* word length=8bit, stop bit = 1, no parity, use external clock */ - ULCON0 = 0x03|0x00|0x00; + /* word length=8bit, stop bit = 1, no parity, use external clock */ + ULCON0 = 0x03|0x00|0x00; - UCON0 = 0x5; + UCON0 = 0x5; } /** @@ -87,9 +87,9 @@ void rt_serial_init() */ char rt_serial_getc() { - while ((UTRSTAT0 & USTAT_RCV_READY) == 0); + while ((UTRSTAT0 & USTAT_RCV_READY) == 0); - return URXH0; + return URXH0; } /** @@ -99,16 +99,16 @@ char rt_serial_getc() */ void rt_serial_putc(const char c) { - /* - to be polite with serial console add a line feed - to the carriage return character - */ - if (c=='\n')rt_serial_putc('\r'); + /* + to be polite with serial console add a line feed + to the carriage return character + */ + if (c=='\n')rt_serial_putc('\r'); - /* wait for room in the transmit FIFO */ - while(!(UTRSTAT0 & USTAT_TXB_EMPTY)); + /* wait for room in the transmit FIFO */ + while(!(UTRSTAT0 & USTAT_TXB_EMPTY)); - UTXH0 = (rt_uint8_t)c; + UTXH0 = (rt_uint8_t)c; } /*@}*/ diff --git a/libcpu/arm/s3c44b0/stack.c b/libcpu/arm/s3c44b0/stack.c index 12da611d5a..4ed4693994 100644 --- a/libcpu/arm/s3c44b0/stack.c +++ b/libcpu/arm/s3c44b0/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/s3c44b0/trap.c b/libcpu/arm/s3c44b0/trap.c index 3b93d5457e..106a990262 100644 --- a/libcpu/arm/s3c44b0/trap.c +++ b/libcpu/arm/s3c44b0/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -33,13 +33,13 @@ extern struct rt_thread *rt_current_thread; */ void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -52,10 +52,10 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("undefined instruction\n"); + rt_hw_cpu_shutdown(); } /** @@ -84,10 +84,10 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("prefetch abort\n"); + rt_hw_cpu_shutdown(); } /** @@ -100,10 +100,10 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("data abort\n"); + rt_hw_cpu_shutdown(); } /** @@ -123,50 +123,50 @@ void rt_hw_trap_resv(struct rt_hw_register *regs) extern rt_isr_handler_t isr_table[]; void rt_hw_trap_irq() { - register unsigned long ispr, intstat; - register rt_isr_handler_t isr_func; + register unsigned long ispr, intstat; + register rt_isr_handler_t isr_func; #ifdef BSP_INT_DEBUG - rt_kprintf("irq coming, "); + rt_kprintf("irq coming, "); #endif - intstat = I_ISPR & 0x7ffffff; + intstat = I_ISPR & 0x7ffffff; #ifdef BSP_INT_DEBUG - rt_kprintf("I_ISPR: %d\n", intstat); + rt_kprintf("I_ISPR: %d\n", intstat); #endif - ispr = intstat; + ispr = intstat; - /* to find interrupt */ - if ( intstat & 0xff ) /* lowest 8bits */ - { - intstat = interrupt_bank0[intstat & 0xff]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff00 ) /* low 8bits */ - { - intstat = interrupt_bank1[(intstat & 0xff00) >> 8]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff0000 ) /* high 8bits */ - { - intstat = interrupt_bank2[(intstat & 0xff0000) >> 16]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else if ( intstat & 0xff000000 ) /* highest 8bits */ - { - intstat = interrupt_bank3[(intstat & 0xff000000) >> 24]; - isr_func = (rt_isr_handler_t)isr_table[ intstat ]; - } - else return; + /* to find interrupt */ + if ( intstat & 0xff ) /* lowest 8bits */ + { + intstat = interrupt_bank0[intstat & 0xff]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else if ( intstat & 0xff00 ) /* low 8bits */ + { + intstat = interrupt_bank1[(intstat & 0xff00) >> 8]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else if ( intstat & 0xff0000 ) /* high 8bits */ + { + intstat = interrupt_bank2[(intstat & 0xff0000) >> 16]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else if ( intstat & 0xff000000 ) /* highest 8bits */ + { + intstat = interrupt_bank3[(intstat & 0xff000000) >> 24]; + isr_func = (rt_isr_handler_t)isr_table[ intstat ]; + } + else return; #ifdef BSP_INT_DEBUG - rt_kprintf("irq: %d happen\n", intstat); + rt_kprintf("irq: %d happen\n", intstat); #endif - /* turn to interrupt service routine */ - isr_func(intstat); + /* turn to interrupt service routine */ + isr_func(intstat); - I_ISPC = ispr; /* clear interrupt */ + I_ISPC = ispr; /* clear interrupt */ } void rt_hw_trap_fiq() diff --git a/libcpu/arm/sep4020/clk.c b/libcpu/arm/sep4020/clk.c index da69e25b6d..031d310fcf 100644 --- a/libcpu/arm/sep4020/clk.c +++ b/libcpu/arm/sep4020/clk.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,46 +11,46 @@ #include <rtthread.h> #include "sep4020.h" -#define CLK_IN 4000000 /* Fin = 4.00MHz */ -#define SYSCLK 72000000 /* system clock we want */ +#define CLK_IN 4000000 /* Fin = 4.00MHz */ +#define SYSCLK 72000000 /* system clock we want */ -#define CLK_ESRAM 0 -#define CLK_LCDC 1 -#define CLK_PWM 2 -#define CLK_DMAC 3 -#define CLK_EMI 4 -#define CLK_MMCSD 5 -#define CLK_SSI 7 -#define CLK_UART0 8 -#define CLK_UART1 9 -#define CLK_UART2 10 -#define CLK_UART3 11 -#define CLK_USB 12 -#define CLK_MAC 13 -#define CLK_SMC 14 -#define CLK_I2C 15 -#define CLK_GPT 16 +#define CLK_ESRAM 0 +#define CLK_LCDC 1 +#define CLK_PWM 2 +#define CLK_DMAC 3 +#define CLK_EMI 4 +#define CLK_MMCSD 5 +#define CLK_SSI 7 +#define CLK_UART0 8 +#define CLK_UART1 9 +#define CLK_UART2 10 +#define CLK_UART3 11 +#define CLK_USB 12 +#define CLK_MAC 13 +#define CLK_SMC 14 +#define CLK_I2C 15 +#define CLK_GPT 16 static void rt_hw_set_system_clock(void) { - rt_uint8_t pv; + rt_uint8_t pv; - /* pv value*/ - pv = SYSCLK/2/CLK_IN; - /* go to normal mode*/ - *(RP)PMU_PMDR = 0x01; - /* set the clock */ - *(RP)PMU_PMCR = 0x4000 | pv; - /* trige configurate*/ - *(RP)PMU_PMCR = 0xc000 | pv; + /* pv value*/ + pv = SYSCLK/2/CLK_IN; + /* go to normal mode*/ + *(RP)PMU_PMDR = 0x01; + /* set the clock */ + *(RP)PMU_PMCR = 0x4000 | pv; + /* trige configurate*/ + *(RP)PMU_PMCR = 0xc000 | pv; } static void rt_hw_set_usb_clock(void) { - /* set the clock */ - *(RP)PMU_PUCR = 0x000c; - /* trige configurate*/ - *(RP)PMU_PMCR = 0x800c; + /* set the clock */ + *(RP)PMU_PUCR = 0x000c; + /* trige configurate*/ + *(RP)PMU_PMCR = 0x800c; } @@ -59,10 +59,10 @@ static void rt_hw_set_usb_clock(void) */ void rt_hw_clock_init(void) { - /* set system clock */ - rt_hw_set_system_clock(); - /* set usb clock */ - rt_hw_set_usb_clock(); + /* set system clock */ + rt_hw_set_system_clock(); + /* set usb clock */ + rt_hw_set_usb_clock(); } /** @@ -70,22 +70,22 @@ void rt_hw_clock_init(void) */ rt_uint32_t rt_hw_get_clock(void) { - rt_uint32_t val; - rt_uint8_t pv, pd, npd; + rt_uint32_t val; + rt_uint8_t pv, pd, npd; - /* get PMCR value */ - val =*(RP) PMU_PMCR; - /* get NPD */ - npd = (val >> 14) & 0x01; - /* get PD */ - pd = (val >> 10) & 0x0f; - /* get PV */ - pv = val & 0x7f; - /* caculate the system clock */ - if(npd) - val = 2 * CLK_IN * pv; - else - val = CLK_IN * pv / (pd + 1); + /* get PMCR value */ + val =*(RP) PMU_PMCR; + /* get NPD */ + npd = (val >> 14) & 0x01; + /* get PD */ + pd = (val >> 10) & 0x0f; + /* get PV */ + pv = val & 0x7f; + /* caculate the system clock */ + if(npd) + val = 2 * CLK_IN * pv; + else + val = CLK_IN * pv / (pd + 1); return(val); } diff --git a/libcpu/arm/sep4020/cpu.c b/libcpu/arm/sep4020/cpu.c index 92ba2cf86a..256ede56e9 100644 --- a/libcpu/arm/sep4020/cpu.c +++ b/libcpu/arm/sep4020/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -21,76 +21,76 @@ extern rt_uint32_t rt_hw_interrupt_disable(void); */ /*@{*/ -#define ICACHE_MASK (rt_uint32_t)(1 << 12) -#define DCACHE_MASK (rt_uint32_t)(1 << 2) +#define ICACHE_MASK (rt_uint32_t)(1 << 12) +#define DCACHE_MASK (rt_uint32_t)(1 << 2) #ifdef __GNUC__ rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); - return i; + asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i)); + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "orr r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "orr r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } rt_inline void cache_disable(rt_uint32_t bit) { - __asm__ __volatile__( \ - "mrc p15,0,r0,c1,c0,0\n\t" \ - "bic r0,r0,%0\n\t" \ - "mcr p15,0,r0,c1,c0,0" \ - : \ - :"r" (bit) \ - :"memory"); + __asm__ __volatile__( \ + "mrc p15,0,r0,c1,c0,0\n\t" \ + "bic r0,r0,%0\n\t" \ + "mcr p15,0,r0,c1,c0,0" \ + : \ + :"r" (bit) \ + :"memory"); } #endif #ifdef __CC_ARM rt_inline rt_uint32_t cp15_rd(void) { - rt_uint32_t i; + rt_uint32_t i; - __asm - { - mrc p15, 0, i, c1, c0, 0 - } + __asm + { + mrc p15, 0, i, c1, c0, 0 + } - return i; + return i; } rt_inline void cache_enable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - orr value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + orr value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } rt_inline void cache_disable(rt_uint32_t bit) { - rt_uint32_t value; + rt_uint32_t value; - __asm - { - mrc p15, 0, value, c1, c0, 0 - bic value, value, bit - mcr p15, 0, value, c1, c0, 0 - } + __asm + { + mrc p15, 0, value, c1, c0, 0 + bic value, value, bit + mcr p15, 0, value, c1, c0, 0 + } } #endif @@ -100,7 +100,7 @@ rt_inline void cache_disable(rt_uint32_t bit) */ void rt_hw_cpu_icache_enable() { - cache_enable(ICACHE_MASK); + cache_enable(ICACHE_MASK); } /** @@ -109,7 +109,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - cache_disable(ICACHE_MASK); + cache_disable(ICACHE_MASK); } /** @@ -118,7 +118,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return (cp15_rd() & ICACHE_MASK); + return (cp15_rd() & ICACHE_MASK); } /** @@ -127,7 +127,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - cache_enable(DCACHE_MASK); + cache_enable(DCACHE_MASK); } /** @@ -136,7 +136,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - cache_disable(DCACHE_MASK); + cache_disable(DCACHE_MASK); } /** @@ -145,7 +145,7 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return (cp15_rd() & DCACHE_MASK); + return (cp15_rd() & DCACHE_MASK); } /** @@ -155,18 +155,18 @@ rt_base_t rt_hw_cpu_dcache_status() RT_WEAK void rt_hw_cpu_reset() { - /* enable watchdog */ - *(RP)(RTC_CTR) = 0x02; + /* enable watchdog */ + *(RP)(RTC_CTR) = 0x02; - /*Enable watchdog reset*/ - *(RP)(RTC_INT_EN) = 0x20; + /*Enable watchdog reset*/ + *(RP)(RTC_INT_EN) = 0x20; - /* Initialize watchdog timer count register */ - *(RP)(RTC_WD_CNT) = 0x0001; + /* Initialize watchdog timer count register */ + *(RP)(RTC_WD_CNT) = 0x0001; - while(1); /* loop forever and wait for reset to happen */ + while(1); /* loop forever and wait for reset to happen */ - /* NEVER REACHED */ + /* NEVER REACHED */ } /** @@ -175,12 +175,12 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t UNUSED level; - rt_kprintf("shutdown...\n"); + rt_uint32_t UNUSED level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); + level = rt_hw_interrupt_disable(); - RT_ASSERT(RT_NULL); + RT_ASSERT(RT_NULL); } /*@}*/ diff --git a/libcpu/arm/sep4020/interrupt.c b/libcpu/arm/sep4020/interrupt.c index ebc9c9625b..24907c139f 100644 --- a/libcpu/arm/sep4020/interrupt.c +++ b/libcpu/arm/sep4020/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,7 +13,7 @@ #include <rthw.h> #include <sep4020.h> -#define MAX_HANDLERS 32 +#define MAX_HANDLERS 32 extern rt_uint32_t rt_interrupt_nest; @@ -29,7 +29,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; static void rt_hw_interrupt_handle(int vector, void *param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -45,7 +45,7 @@ void rt_hw_interrupt_init(void) *(RP)(INTC_IMR) = 0xFFFFFFFF; /*enable all the irq*/ - *(RP)(INTC_IER) = 0XFFFFFFFF; + *(RP)(INTC_IER) = 0XFFFFFFFF; /*Dont use any forced irq*/ *(RP)(INTC_IFR) = 0x0; @@ -82,7 +82,7 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int vector) { - *(RP)(INTC_IMR) |= 1 << vector; + *(RP)(INTC_IMR) |= 1 << vector; } /** @@ -91,12 +91,12 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - if(vector == 16) - { - rt_kprintf("Interrupt vec %d is not used!\n", vector); - } - else - *(RP)(INTC_IMR) &= ~(1 << vector); + if(vector == 16) + { + rt_kprintf("Interrupt vec %d is not used!\n", vector); + } + else + *(RP)(INTC_IMR) &= ~(1 << vector); } @@ -118,7 +118,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if (handler != RT_NULL) { #ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); #endif /* RT_USING_INTERRUPT_INFO */ isr_table[vector].handler = handler; isr_table[vector].param = param; diff --git a/libcpu/arm/sep4020/sep4020.h b/libcpu/arm/sep4020/sep4020.h index 4ae09d0275..bb8effbff0 100644 --- a/libcpu/arm/sep4020/sep4020.h +++ b/libcpu/arm/sep4020/sep4020.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -13,13 +13,13 @@ /*Core definations*/ #define SVCMODE -#define Mode_USR 0x10 -#define Mode_FIQ 0x11 -#define Mode_IRQ 0x12 -#define Mode_SVC 0x13 -#define Mode_ABT 0x17 -#define Mode_UND 0x1B -#define Mode_SYS 0x1F +#define Mode_USR 0x10 +#define Mode_FIQ 0x11 +#define Mode_IRQ 0x12 +#define Mode_SVC 0x13 +#define Mode_ABT 0x17 +#define Mode_UND 0x1B +#define Mode_SYS 0x1F @@ -106,7 +106,7 @@ #define RTC_INT_STS (RTC_BASE+0X014) /* 中断状态寄存器 */ #define RTC_SAMP (RTC_BASE+0X018) /* 采样周期寄存器 */ #define RTC_WD_CNT (RTC_BASE+0X01C) /* Watch-Dog计数值寄存器 */ -#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog服务寄存器 */ +#define RTC_WD_SEV (RTC_BASE+0X020) /* Watch-Dog服务寄存器 */ #define RTC_CONFIG_CHECK (RTC_BASE+0X024) /* 配置时间确认寄存器 (在配置时间之前先写0xaaaaaaaa) */ #define RTC_KEY0 (RTC_BASE+0X02C) /* 密钥寄存器 */ @@ -325,18 +325,18 @@ * SD模块 * 基址: 0x1000B000 */ - -#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIO时钟控制寄存器 */ -#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIO软件复位寄存器 */ -#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIO命令参数寄存器 */ -#define SDC_COMMAND (SD_BASE+0X0C) /* SDIO命令控制寄存器 */ + +#define SDC_CLOCK_CONTROL (SD_BASE+0x00) /* SDIO时钟控制寄存器 */ +#define SDC_SOFTWARE_RESET (SD_BASE+0X04) /* SDIO软件复位寄存器 */ +#define SDC_ARGUMENT (SD_BASE+0X08) /* SDIO命令参数寄存器 */ +#define SDC_COMMAND (SD_BASE+0X0C) /* SDIO命令控制寄存器 */ #define SDC_BLOCK_SIZE (SD_BASE+0X10) /* SDIO数据块长度寄存器 */ -#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIO数据块数目寄存器 */ -#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO传输模式选择寄存器 */ -#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIO响应寄存器0 */ -#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIO响应寄存器1 */ -#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIO响应寄存器2 */ -#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIO响应寄存器3 */ +#define SDC_BLOCK_COUNT (SD_BASE+0X14) /* SDIO数据块数目寄存器 */ +#define SDC_TRANSFER_MODE (SD_BASE+0X18) /* SDIO传输模式选择寄存器 */ +#define SDC_RESPONSE0 (SD_BASE+0X1c) /* SDIO响应寄存器0 */ +#define SDC_RESPONSE1 (SD_BASE+0X20) /* SDIO响应寄存器1 */ +#define SDC_RESPONSE2 (SD_BASE+0X24) /* SDIO响应寄存器2 */ +#define SDC_RESPONSE3 (SD_BASE+0X28) /* SDIO响应寄存器3 */ #define SDC_READ_TIMEOUT_CONTROL (SD_BASE+0X2c) /* SDIO读超时控制寄存器 */ #define SDC_INTERRUPT_STATUS (SD_BASE+0X30) /* SDIO中断状态寄存器 */ #define SDC_INTERRUPT_STATUS_MASK (SD_BASE+0X34) /* SDIO中断状态屏蔽寄存器 */ @@ -650,15 +650,15 @@ #define MAC_HASH0 (MAC_BASE+0X048) /* MAC HASH寄存器 */ #define MAC_HASH1 (MAC_BASE+0X04C) /* MAC HASH寄存器 */ #define MAC_TXPAUSE (MAC_BASE+0X050) /* MAC控制帧寄存器 */ -#define MAC_TX_BD (MAC_BASE+0X400) -#define MAC_RX_BD (MAC_BASE+0X600) +#define MAC_TX_BD (MAC_BASE+0X400) +#define MAC_RX_BD (MAC_BASE+0X600) /* ************************************** * Error Codes: * IF SUCCESS RETURN 0, ELSE RETURN OTHER ERROR CODE, - * parameter error return (-33)/E_PAR, + * parameter error return (-33)/E_PAR, * hardware error reture (-99)/E_HA ************************************** */ @@ -680,7 +680,7 @@ #define E_QOVR (-73) /* Queuing or nesting overflow */ #define E_DLT (-81) /* Object being waited for was deleted */ #define E_TMOUT (-85) /* Polling failure or timeout exceeded */ -#define E_RLWAI (-86) /* WAIT state was forcibly released */ +#define E_RLWAI (-86) /* WAIT state was forcibly released */ #define E_HA (-99) /* HARD WARE ERROR */ @@ -692,7 +692,7 @@ */ #define CLK_SGPT (1 << 16) -#define CLK_SI2S (1 << 15) +#define CLK_SI2S (1 << 15) #define CLK_SSMC (1 << 14) #define CLK_SMAC (1 << 13) #define CLK_SUSB (1 << 12) @@ -713,8 +713,8 @@ /*Interrupt Sources*/ -#define INTSRC_RTC 31 -#define INTSRC_DMAC 30 +#define INTSRC_RTC 31 +#define INTSRC_DMAC 30 #define INTSRC_EMI 29 #define INTSRC_MAC 28 #define INTSRC_TIMER1 27 @@ -732,17 +732,17 @@ #define INTSRC_USB 15 #define INTSRC_SMC0 14 #define INTSRC_SMC1 13 -#define INTSRC_SDIO 12 -#define INTSRC_EXINT10 11 -#define INTSRC_EXINT9 10 -#define INTSRC_EXINT8 9 -#define INTSRC_EXINT7 8 -#define INTSRC_EXINT6 7 -#define INTSRC_EXINT5 6 -#define INTSRC_EXINT4 5 -#define INTSRC_EXINT3 4 -#define INTSRC_EXINT2 3 -#define INTSRC_EXINT1 2 +#define INTSRC_SDIO 12 +#define INTSRC_EXINT10 11 +#define INTSRC_EXINT9 10 +#define INTSRC_EXINT8 9 +#define INTSRC_EXINT7 8 +#define INTSRC_EXINT6 7 +#define INTSRC_EXINT5 6 +#define INTSRC_EXINT4 5 +#define INTSRC_EXINT3 4 +#define INTSRC_EXINT2 3 +#define INTSRC_EXINT1 2 #define INTSRC_EXINT0 1 #define INTSRC_NULL 0 @@ -752,7 +752,7 @@ #define set_int_force(intnum) *(RP)INTC_IFR = (1 << intnum) //置1后，软件强制该位对应的中断源发出中断信号 #define enable_irq(intnum) *(RP)INTC_IER |= (1 << intnum) //置1后，允许中断源的IRQ 中断信号 #define disable_irq( intnum) *(RP)INTC_IER &= ~(1<< intnum) //置0后，不允许中断源的IRQ 中断信号 -#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //置1后，屏蔽对应的IRQ 中断信号 +#define mask_irq(intnum) *(RP)INTC_IMR |= (1 << intnum) //置1后，屏蔽对应的IRQ 中断信号 #define unmask_irq(intnum) *(RP)INTC_IMR &= ~(1 << intnum) //置0后，通过对应的IRQ 中断信号 #define mask_all_irq() *(RP)INTC_IMR = 0xFFFFFFFF //屏蔽对应的IRQ 中断信号 #define unmask_all_irq() *(RP)INTC_IMR = 0x00000000 //通过对应的IRQ 中断信号 @@ -765,7 +765,7 @@ * 所有程序中用到的Typedef ************************************** */ - + typedef char S8; /* signed 8-bit integer */ typedef short S16; /* signed 16-bit integer */ typedef long S32; /* signed 32-bit integer */ @@ -782,8 +782,8 @@ typedef void (*FP)(); /* program start address */ #ifndef _BOOL_TYPE_ #define _BOOL_TYPE_ -typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ -#endif +typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ +#endif typedef int ER; /* Error code. A signed integer. */ @@ -802,71 +802,71 @@ typedef int ER; /* Error code. A signed integer. */ /*Macros for debug*/ #define EOUT(fmt,...) \ - do \ - { \ - rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + do \ + { \ + rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #define RT_DEBUG #ifdef RT_DEBUG - #define DBOUT(fmt,...) \ - do \ - { \ - rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + #define DBOUT(fmt,...) \ + do \ + { \ + rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #else - #define DBOUT(fmt,...) \ - do{}while(0) + #define DBOUT(fmt,...) \ + do{}while(0) #endif -#ifdef RT_DEBUG - #define ASSERT(arg) \ - if((arg) == 0) \ - { \ - while(1) \ - { \ - rt_kprintf("have a assert failure\n"); \ - } \ - } +#ifdef RT_DEBUG + #define ASSERT(arg) \ + if((arg) == 0) \ + { \ + while(1) \ + { \ + rt_kprintf("have a assert failure\n"); \ + } \ + } #else - #define ASSERT(arg) \ - do \ - { \ - }while(0) + #define ASSERT(arg) \ + do \ + { \ + }while(0) #endif #define write_reg(reg,value) \ - do \ - { \ - *(RP)(reg) = value; \ - }while(0) + do \ + { \ + *(RP)(reg) = value; \ + }while(0) #define read_reg(reg) (*(RP)reg) struct rt_hw_register { - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t cpsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t cpsr; + rt_uint32_t ORIG_r0; }; diff --git a/libcpu/arm/sep4020/serial.c b/libcpu/arm/sep4020/serial.c index 713959238a..9bf1546c08 100644 --- a/libcpu/arm/sep4020/serial.c +++ b/libcpu/arm/sep4020/serial.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2006-03-13 Bernard first version * 2009-04-20 yi.qiu modified according bernard's stm32 version - * 2010-10-6 wangmeng added sep4020 surpport + * 2010-10-6 wangmeng added sep4020 surpport */ #include <rtthread.h> #include <rthw.h> @@ -24,204 +24,204 @@ */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct serial_device* uart = (struct serial_device*) dev->user_data; + struct serial_device* uart = (struct serial_device*) dev->user_data; - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } - return RT_EOK; + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; } /* save a char to serial buffer */ static void rt_serial_savechar(struct serial_device* uart, char ch) { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + + /* enable interrupt */ + rt_hw_interrupt_enable(level); } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; - ptr ++; - } - } - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; + ptr ++; + } + } + } - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; +{ + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + + -- size; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; + /* move to next position */ + uart->int_tx->save_index ++; - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = '\r'; - } + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = '\r'; + } - ++ptr; --size; - } - } + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + ++ptr; --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; + + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; + return RT_EOK; } /* @@ -229,49 +229,49 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } - + /* ISR for serial interrupt */ void rt_hw_serial_isr(rt_device_t device) { - struct serial_device* uart = (struct serial_device*) device->user_data; - - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + struct serial_device* uart = (struct serial_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* save on rx buffer */ + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); + } - /* save on rx buffer */ - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); - } + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; - device->rx_indicate(device, rx_length); - } + device->rx_indicate(device, rx_length); + } } /*@}*/ diff --git a/libcpu/arm/sep4020/serial.h b/libcpu/arm/sep4020/serial.h index 69e7df248c..26ec0f6cec 100644 --- a/libcpu/arm/sep4020/serial.h +++ b/libcpu/arm/sep4020/serial.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,7 +7,7 @@ * Date Author Notes * 2006-03-13 Bernard first version * 2009-04-20 yi.qiu modified according bernard's stm32 version - * 2010-10-6 wangmeng added sep4020 surpport + * 2010-10-6 wangmeng added sep4020 surpport */ #ifndef __SERIAL_H__ @@ -15,67 +15,67 @@ #include <sep4020.h> -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 /*For sep4020's uart have several secondary function*/ /*we use union to decribe it*/ union dlbl_fifo { - rt_uint32_t dlbl; - rt_uint32_t rxfifo; - rt_uint32_t txfifo; + rt_uint32_t dlbl; + rt_uint32_t rxfifo; + rt_uint32_t txfifo; }; union dlbh_ier { - rt_uint32_t dlbh; - rt_uint32_t ier; + rt_uint32_t dlbh; + rt_uint32_t ier; }; union iir_fcr { - rt_uint32_t iir; - rt_uint32_t fcr; + rt_uint32_t iir; + rt_uint32_t fcr; }; struct serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct serial_int_tx { - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; }; typedef struct uartport { - union dlbl_fifo dlbl_fifo; - union dlbh_ier dlbh_ier; - union iir_fcr iir_fcr; - rt_uint32_t lcr; - rt_uint32_t mcr; - rt_uint32_t lsr; - rt_uint32_t msr; + union dlbl_fifo dlbl_fifo; + union dlbh_ier dlbh_ier; + union iir_fcr iir_fcr; + rt_uint32_t lcr; + rt_uint32_t mcr; + rt_uint32_t lsr; + rt_uint32_t msr; }uartport; struct serial_device { - uartport* uart_device; - - /* rx structure */ - struct serial_int_rx* int_rx; + uartport* uart_device; - /* tx structure */ - struct serial_int_tx* int_tx; + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; }; rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); diff --git a/libcpu/arm/sep4020/stack.c b/libcpu/arm/sep4020/stack.c index b2205c76d2..3a7b5fd87c 100644 --- a/libcpu/arm/sep4020/stack.c +++ b/libcpu/arm/sep4020/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/sep4020/trap.c b/libcpu/arm/sep4020/trap.c index c551b2246c..441a55bd6d 100644 --- a/libcpu/arm/sep4020/trap.c +++ b/libcpu/arm/sep4020/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -31,13 +31,13 @@ extern struct rt_thread *rt_current_thread; void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); + rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("cpsr:0x%08x\n", regs->cpsr); } /** @@ -50,13 +50,13 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_udef(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("undefined instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("undefined instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -70,10 +70,10 @@ void rt_hw_trap_udef(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -86,13 +86,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -105,13 +105,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -123,9 +123,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc isr_table[]; @@ -155,13 +155,13 @@ void rt_hw_trap_irq(void) isr_func(irq, param); #ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; + isr_table[irq].counter++; #endif /* RT_USING_INTERRUPT_INFO */ } void rt_hw_trap_fiq(void) { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/libcpu/arm/zynq7000/SConscript b/libcpu/arm/zynq7000/SConscript deleted file mode 100644 index 28af7ba651..0000000000 --- a/libcpu/arm/zynq7000/SConscript +++ /dev/null @@ -1,23 +0,0 @@ -# RT-Thread building script for component - -from building import * - -Import('rtconfig') - -cwd = GetCurrentDir() -src = Glob('*.c') + Glob('*.cpp') -CPPPATH = [cwd] - -if rtconfig.PLATFORM == 'armcc': - src += Glob('*_rvds.S') - -if rtconfig.PLATFORM == 'gcc': - src += Glob('*_init.S') - src += Glob('*_gcc.S') - -if rtconfig.PLATFORM == 'iar': - src += Glob('*_iar.S') - -group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/libcpu/arm/zynq7000/armv7.h b/libcpu/arm/zynq7000/armv7.h deleted file mode 100644 index 65f6c27860..0000000000 --- a/libcpu/arm/zynq7000/armv7.h +++ /dev/null @@ -1,65 +0,0 @@ -#ifndef __ARMV7_H__ -#define __ARMV7_H__ -/* - * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -/* the exception stack without VFP registers */ -struct rt_hw_exp_stack -{ - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; -}; - -#define USERMODE 0x10 -#define FIQMODE 0x11 -#define IRQMODE 0x12 -#define SVCMODE 0x13 -#define MONITORMODE 0x16 -#define ABORTMODE 0x17 -#define HYPMODE 0x1b -#define UNDEFMODE 0x1b -#define MODEMASK 0x1f -#define NOINT 0xc0 - -#define T_Bit (1<<5) -#define F_Bit (1<<6) -#define I_Bit (1<<7) -#define A_Bit (1<<8) -#define E_Bit (1<<9) -#define J_Bit (1<<24) - -void rt_hw_mmu_init(void); - -#endif diff --git a/libcpu/arm/zynq7000/context_gcc.S b/libcpu/arm/zynq7000/context_gcc.S deleted file mode 100644 index 98f98a0244..0000000000 --- a/libcpu/arm/zynq7000/context_gcc.S +++ /dev/null @@ -1,92 +0,0 @@ -/* - * Copyright (c) 2006-2018, Shanghai Real-Thread Technology Co., Ltd - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2009-01-20 Bernard first version - */ - -#define NOINT 0xc0 - -/* - * rt_base_t rt_hw_interrupt_disable(); - */ -.globl rt_hw_interrupt_disable -rt_hw_interrupt_disable: - mrs r0, cpsr - orr r1, r0, #NOINT - msr cpsr_c, r1 - bx lr - -/* - * void rt_hw_interrupt_enable(rt_base_t level); - */ -.globl rt_hw_interrupt_enable -rt_hw_interrupt_enable: - msr cpsr, r0 - bx lr - -/* - * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to); - * r0 --> from - * r1 --> to - */ -.globl rt_hw_context_switch -rt_hw_context_switch: - stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC) - stmfd sp!, {r0-r12, lr} @ push lr & register file - - mrs r4, cpsr - tst lr, #0x01 - beq _ARM_MODE - orr r4, r4, #0x20 @ it's thumb code - -_ARM_MODE: - stmfd sp!, {r4} @ push cpsr - - str sp, [r0] @ store sp in preempted tasks TCB - ldr sp, [r1] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task cpsr to spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc, copy spsr to cpsr - -/* - * void rt_hw_context_switch_to(rt_uint32 to); - * r0 --> to - */ -.globl rt_hw_context_switch_to -rt_hw_context_switch_to: - ldr sp, [r0] @ get new task stack pointer - - ldmfd sp!, {r4} @ pop new task spsr - msr spsr_cxsf, r4 - - bic r4, r4, #0x20 @ must be ARM mode - msr cpsr_cxsf, r4 - - ldmfd sp!, {r0-r12, lr, pc}^ @ pop new task r0-r12, lr & pc - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - ldr r2, =rt_thread_switch_interrupt_flag - ldr r3, [r2] - cmp r3, #1 - beq _reswitch - mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1 - str r3, [r2] - ldr r2, =rt_interrupt_from_thread @ set rt_interrupt_from_thread - str r0, [r2] -_reswitch: - ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread - str r1, [r2] - bx lr diff --git a/libcpu/arm/zynq7000/cp15.h b/libcpu/arm/zynq7000/cp15.h deleted file mode 100644 index 75d81736ab..0000000000 --- a/libcpu/arm/zynq7000/cp15.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#ifndef __CP15_H__ -#define __CP15_H__ - -unsigned long rt_cpu_get_smp_id(void); - -void rt_cpu_mmu_disable(void); -void rt_cpu_mmu_enable(void); -void rt_cpu_tlb_set(volatile unsigned long*); - -void rt_cpu_vector_set_base(unsigned int addr); - -#endif diff --git a/libcpu/arm/zynq7000/cp15_gcc.S b/libcpu/arm/zynq7000/cp15_gcc.S deleted file mode 100644 index 0e3e60655c..0000000000 --- a/libcpu/arm/zynq7000/cp15_gcc.S +++ /dev/null @@ -1,125 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -.globl rt_cpu_get_smp_id -rt_cpu_get_smp_id: - mrc p15, #0, r0, c0, c0, #5 - bx lr - -.globl rt_cpu_vector_set_base -rt_cpu_vector_set_base: - mcr p15, #0, r0, c12, c0, #0 - dsb - bx lr - -.globl rt_hw_cpu_dcache_enable -rt_hw_cpu_dcache_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x00000004 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -.globl rt_hw_cpu_icache_enable -rt_hw_cpu_icache_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x00001000 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -_FLD_MAX_WAY: - .word 0x3ff -_FLD_MAX_IDX: - .word 0x7ff - -.globl rt_cpu_dcache_clean_flush -rt_cpu_dcache_clean_flush: - push {r4-r11} - dmb - mrc p15, #1, r0, c0, c0, #1 @ read clid register - ands r3, r0, #0x7000000 @ get level of coherency - mov r3, r3, lsr #23 - beq finished - mov r10, #0 -loop1: - add r2, r10, r10, lsr #1 - mov r1, r0, lsr r2 - and r1, r1, #7 - cmp r1, #2 - blt skip - mcr p15, #2, r10, c0, c0, #0 - isb - mrc p15, #1, r1, c0, c0, #0 - and r2, r1, #7 - add r2, r2, #4 - ldr r4, _FLD_MAX_WAY - ands r4, r4, r1, lsr #3 - clz r5, r4 - ldr r7, _FLD_MAX_IDX - ands r7, r7, r1, lsr #13 -loop2: - mov r9, r4 -loop3: - orr r11, r10, r9, lsl r5 - orr r11, r11, r7, lsl r2 - mcr p15, #0, r11, c7, c14, #2 - subs r9, r9, #1 - bge loop3 - subs r7, r7, #1 - bge loop2 -skip: - add r10, r10, #2 - cmp r3, r10 - bgt loop1 - -finished: - dsb - isb - pop {r4-r11} - bx lr - -.globl rt_hw_cpu_dcache_disable -rt_hw_cpu_dcache_disable: - push {r4-r11, lr} - bl rt_cpu_dcache_clean_flush - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #0x00000004 - mcr p15, #0, r0, c1, c0, #0 - pop {r4-r11, lr} - bx lr - -.globl rt_hw_cpu_icache_disable -rt_hw_cpu_icache_disable: - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #0x00001000 - mcr p15, #0, r0, c1, c0, #0 - bx lr - -.globl rt_cpu_mmu_disable -rt_cpu_mmu_disable: - mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb - mrc p15, #0, r0, c1, c0, #0 - bic r0, r0, #1 - mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit - dsb - bx lr - -.globl rt_cpu_mmu_enable -rt_cpu_mmu_enable: - mrc p15, #0, r0, c1, c0, #0 - orr r0, r0, #0x001 - mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit - dsb - bx lr - -.globl rt_cpu_tlb_set -rt_cpu_tlb_set: - mcr p15, #0, r0, c2, c0, #0 - dmb - bx lr diff --git a/libcpu/arm/zynq7000/cpu.c b/libcpu/arm/zynq7000/cpu.c deleted file mode 100644 index f6b7f5d852..0000000000 --- a/libcpu/arm/zynq7000/cpu.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#include <rthw.h> -#include <rtthread.h> -#include "zynq7000.h" - -/** - * reset cpu by dog's time-out - * - */ -RT_WEAK void rt_hw_cpu_reset() -{ - while (1); /* loop forever and wait for reset to happen */ - - /* NEVER REACHED */ -} - -/** - * shutdown CPU - * - */ -RT_WEAK void rt_hw_cpu_shutdown() -{ - rt_uint32_t level; - rt_kprintf("shutdown...\n"); - - level = rt_hw_interrupt_disable(); - while (level) - { - RT_ASSERT(0); - } -} - diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c deleted file mode 100644 index 76404d4c46..0000000000 --- a/libcpu/arm/zynq7000/gic.c +++ /dev/null @@ -1,228 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#include <rtthread.h> -#include <board.h> - -#include "gic.h" -#include "cp15.h" - -struct arm_gic -{ - rt_uint32_t offset; - - rt_uint32_t dist_hw_base; - rt_uint32_t cpu_hw_base; -}; -static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; - -#define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00) -#define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04) -#define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08) -#define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c) -#define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10) -#define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14) -#define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18) - -#define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000) -#define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004) -#define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + (n/32) * 4) -#define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + (n/32) * 4) -#define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + (n/32) * 4) -#define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + (n/32) * 4) -#define GIC_DIST_ACTIVE_BIT(hw_base) __REG32((hw_base) + 0x300) -#define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + (n/4) * 4) -#define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + (n/4) * 4) -#define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + (n/16) * 4) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) -#define GIC_DIST_CPENDSGI(hw_base, n) __REG32((hw_base) + 0xf10 + (n/4) * 4) -#define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) - -static unsigned int _gic_max_irq; - -int arm_gic_get_active_irq(rt_uint32_t index) -{ - int irq; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base); - irq += _gic_table[index].offset; - return irq; -} - -void arm_gic_ack(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_PENDING_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; - GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq; -} - -void arm_gic_mask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask) -{ - rt_uint32_t old_tgt; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq); - - old_tgt &= ~(0x0FFUL << ((irq % 4)*8)); - old_tgt |= cpumask << ((irq % 4)*8); - - GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt; -} - -void arm_gic_umask(rt_uint32_t index, int irq) -{ - rt_uint32_t mask = 1 << (irq % 32); - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - irq = irq - _gic_table[index].offset; - RT_ASSERT(irq >= 0); - - GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask; -} - -void arm_gic_dump_type(rt_uint32_t index) -{ - unsigned int gic_type; - - gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base); - rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n", - (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf, - _gic_table[index].dist_hw_base, - _gic_max_irq, - gic_type & (1 << 10) ? "has" : "no", - gic_type); -} - -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start) -{ - unsigned int gic_type, i; - rt_uint32_t cpumask = 1 << 0; - - RT_ASSERT(index < ARM_GIC_MAX_NR); - - _gic_table[index].dist_hw_base = dist_base; - _gic_table[index].offset = irq_start; - - /* Find out how many interrupts are supported. */ - gic_type = GIC_DIST_TYPE(dist_base); - _gic_max_irq = ((gic_type & 0x1f) + 1) * 32; - - /* - * The GIC only supports up to 1020 interrupt sources. - * Limit this to either the architected maximum, or the - * platform maximum. - */ - if (_gic_max_irq > 1020) - _gic_max_irq = 1020; - if (_gic_max_irq > ARM_GIC_NR_IRQS) - _gic_max_irq = ARM_GIC_NR_IRQS; - - cpumask |= cpumask << 8; - cpumask |= cpumask << 16; - - GIC_DIST_CTRL(dist_base) = 0x0; - - /* Set all global interrupts to be level triggered, active low. */ - for (i = 32; i < _gic_max_irq; i += 16) - GIC_DIST_CONFIG(dist_base, i) = 0x0; - - /* Set all global interrupts to this CPU only. */ - for (i = 32; i < _gic_max_irq; i += 4) - GIC_DIST_TARGET(dist_base, i) = cpumask; - - /* Set priority on all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 4) - GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0; - - /* Disable all interrupts. */ - for (i = 0; i < _gic_max_irq; i += 32) - GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff; - - /* Set the FIQEn bit, signal FIQ for IGROUP0. */ - GIC_DIST_CTRL(dist_base) = 0x01; - - return 0; -} - -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base) -{ - RT_ASSERT(index < ARM_GIC_MAX_NR); - - _gic_table[index].cpu_hw_base = cpu_base; - - GIC_CPU_PRIMASK(cpu_base) = 0xf0; - /* Enable CPU interrupt */ - GIC_CPU_CTRL(cpu_base) = 0x01; - - return 0; -} - -void arm_gic_set_group(rt_uint32_t index, int vector, int group) -{ - /* As for GICv2, there are only group0 and group1. */ - RT_ASSERT(group <= 1); - RT_ASSERT(vector < _gic_max_irq); - - if (group == 0) - { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) &= ~(1 << (vector % 32)); - } - else if (group == 1) - { - GIC_DIST_IGROUP(_gic_table[index].dist_hw_base, - vector) |= (1 << (vector % 32)); - } -} - -void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq) -{ - unsigned int reg; - - RT_ASSERT(irq <= 15); - RT_ASSERT(target_cpu <= 255); - - reg = (target_cpu << 16) | irq; - GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg; -} - -void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq) -{ - RT_ASSERT(irq <= 15); - RT_ASSERT(target_cpu <= 255); - - GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = target_cpu << (irq % 4); -} diff --git a/libcpu/arm/zynq7000/gic.h b/libcpu/arm/zynq7000/gic.h deleted file mode 100644 index 8fcdf05f6f..0000000000 --- a/libcpu/arm/zynq7000/gic.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#ifndef __GIC_H__ -#define __GIC_H__ - -int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start); -int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base); - -void arm_gic_mask(rt_uint32_t index, int irq); -void arm_gic_umask(rt_uint32_t index, int irq); -void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask); -void arm_gic_set_group(rt_uint32_t index, int vector, int group); - -int arm_gic_get_active_irq(rt_uint32_t index); -void arm_gic_ack(rt_uint32_t index, int irq); - -void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq); -void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq); - -void arm_gic_dump_type(rt_uint32_t index); - -#endif - diff --git a/libcpu/arm/zynq7000/interrupt.c b/libcpu/arm/zynq7000/interrupt.c deleted file mode 100644 index 451785523a..0000000000 --- a/libcpu/arm/zynq7000/interrupt.c +++ /dev/null @@ -1,143 +0,0 @@ -/* - * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd - * - * All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - */ - -#include <rthw.h> -#include <rtthread.h> -#include "zynq7000.h" -#include "cp15.h" -#include "gic.h" - -#define MAX_HANDLERS IRQ_Zynq7000_MAXNR - -extern volatile rt_uint8_t rt_interrupt_nest; - -/* exception and interrupt handler table */ -struct rt_irq_desc isr_table[MAX_HANDLERS]; -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - -static void rt_hw_interrupt_handle(int vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); -} - -const unsigned int VECTOR_BASE = 0x00; -extern int system_vectors; - -static void rt_hw_vector_init(void) -{ - int sctrl; - unsigned int *src = (unsigned int *)&system_vectors; - - /* C12-C0 is only active when SCTLR.V = 0 */ - asm volatile ("mrc p15, #0, %0, c1, c0, #0" - :"=r" (sctrl)); - sctrl &= ~(1 << 13); - asm volatile ("mcr p15, #0, %0, c1, c0, #0" - : - :"r" (sctrl)); - - asm volatile ("mcr p15, #0, %0, c12, c0, #0" - : - :"r" (src)); -} - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - register rt_uint32_t idx; - - /* set vector table */ - rt_hw_vector_init(); - - /* init exceptions table */ - rt_memset(isr_table, 0x00, sizeof(isr_table)); - for (idx = 0; idx < MAX_HANDLERS; idx++) - { - isr_table[idx].handler = rt_hw_interrupt_handle; - } - - /* initialize ARM GIC */ - arm_gic_dist_init(0, Zynq7000_GIC_DIST_BASE, 0); - arm_gic_cpu_init(0, Zynq7000_GIC_CPU_BASE); - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -/** - * This function will mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_mask(int vector) -{ - arm_gic_mask(0, vector); -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int vector) -{ - arm_gic_umask(0, vector); -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param new_handler the interrupt service routine to be installed - * @param old_handler the old interrupt service routine - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, const char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if (vector < MAX_HANDLERS) - { - old_handler = isr_table[vector].handler; - - if (handler != RT_NULL) - { -#ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); -#endif /* RT_USING_INTERRUPT_INFO */ - isr_table[vector].handler = handler; - isr_table[vector].param = param; - } - /* set the interrupt to this cpu */ - arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id()); - } - - return old_handler; -} - -void rt_hw_interrupt_clear(int vector) -{ - /* SGI will be cleared automatically. */ - if (vector < 16) - return; -} diff --git a/libcpu/arm/zynq7000/interrupt.h b/libcpu/arm/zynq7000/interrupt.h deleted file mode 100644 index da266c42a2..0000000000 --- a/libcpu/arm/zynq7000/interrupt.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -void rt_hw_interrupt_clear(int vector); - -#endif /* end of include guard: __INTERRUPT_H__ */ - diff --git a/libcpu/arm/zynq7000/mmu.c b/libcpu/arm/zynq7000/mmu.c deleted file mode 100644 index fbdacca10f..0000000000 --- a/libcpu/arm/zynq7000/mmu.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#include <rtthread.h> -#include <rthw.h> -#include <board.h> - -#include "cp15.h" - -#define DESC_SEC (0x2) -#define CB (3<<2) //cache_on, write_back -#define CNB (2<<2) //cache_on, write_through -#define NCB (1<<2) //cache_off,WR_BUF on -#define NCNB (0<<2) //cache_off,WR_BUF off -#define AP_RW (3<<10) //supervisor=RW, user=RW -#define AP_RO (2<<10) //supervisor=RW, user=RO -#define XN (1<<4) //eXecute Never - -#define DOMAIN_FAULT (0x0) -#define DOMAIN_CHK (0x1) -#define DOMAIN_NOTCHK (0x3) -#define DOMAIN0 (0x0<<5) -#define DOMAIN1 (0x1<<5) - -#define DOMAIN0_ATTR (DOMAIN_CHK<<0) -#define DOMAIN1_ATTR (DOMAIN_FAULT<<2) - -/* Read/Write, cache, write back */ -#define RW_CB (AP_RW|DOMAIN0|CB|DESC_SEC) -/* Read/Write, cache, write through */ -#define RW_CNB (AP_RW|DOMAIN0|CNB|DESC_SEC) -/* Read/Write, device type */ -#define RW_NCB (AP_RW|DOMAIN0|NCB|DESC_SEC) -/* Read/Write strongly ordered type */ -#define RW_NCNB (AP_RW|DOMAIN0|NCNB|DESC_SEC) -/* Read/Write without cache and write buffer, no execute */ -#define RW_NCNBXN (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN) -/* Read/Write without cache and write buffer */ -#define RW_FAULT (AP_RW|DOMAIN1|NCNB|DESC_SEC) - -void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb) -{ - int i; - int fcnt = 0; - - rt_kprintf("page table@%p\n", ptb); - for (i = 0; i < 1024*4; i++) - { - rt_uint32_t pte1 = ptb[i]; - if ((pte1 & 0x3) == 0) - { - rt_kprintf("%03x: ", i); - fcnt++; - if (fcnt == 16) - { - rt_kprintf("fault\n"); - fcnt = 0; - } - continue; - } - if (fcnt != 0) - { - rt_kprintf("fault\n"); - fcnt = 0; - } - - rt_kprintf("%03x: %08x: ", i, pte1); - if ((pte1 & 0x3) == 0x3) - { - rt_kprintf("LPAE\n"); - } - else if ((pte1 & 0x3) == 0x1) - { - rt_kprintf("pte,ns:%d,domain:%d\n", - (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); - /* - *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) - * - 0x80000000 + 0xC0000000)); - */ - } - else if (pte1 & (1 << 18)) - { - rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", - (pte1 >> 19) & 0x1, - ((pte1 >> 13) | (pte1 >> 10))& 0xf, - (pte1 >> 4) & 0x1, - ((pte1 >> 10) | (pte1 >> 2)) & 0x1f); - } - else - { - rt_kprintf("section,ns:%d,ap:%x," - "xn:%d,texcb:%02x,domain:%d\n", - (pte1 >> 19) & 0x1, - ((pte1 >> 13) | (pte1 >> 10))& 0xf, - (pte1 >> 4) & 0x1, - (((pte1 & (0x7 << 12)) >> 10) | - ((pte1 & 0x0c) >> 2)) & 0x1f, - (pte1 >> 5) & 0xf); - } - } -} - -/* level1 page table, each entry for 1MB memory. */ -/* MMUTable is the name used by codes of Xilinx */ -volatile unsigned long MMUTable[4*1024] SECTION("mmu_tbl") __attribute__((aligned(16*1024))); -void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart, - rt_uint32_t vaddrEnd, - rt_uint32_t paddrStart, - rt_uint32_t attr) -{ - volatile rt_uint32_t *pTT; - volatile int i, nSec; - pTT = (rt_uint32_t *)MMUTable + (vaddrStart >> 20); - nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); - for(i = 0; i <= nSec; i++) - { - *pTT = attr | (((paddrStart >> 20) + i) << 20); - pTT++; - } -} - -unsigned long rt_hw_set_domain_register(unsigned long domain_val) -{ - unsigned long old_domain; - - asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); - asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); - - return old_domain; -} - -void rt_hw_mmu_init(void) -{ - extern rt_uint32_t __text_start; - rt_hw_cpu_dcache_disable(); - rt_hw_cpu_icache_disable(); - rt_cpu_mmu_disable(); - - /* set page table */ - /* no access to the memory below .text */ - /* 128M cached DDR memory */ - rt_hw_mmu_setmtt((rt_uint32_t)&__text_start, 0x20000000-1, - 0x1ff00000, RW_CB); - /* PL region */ - rt_hw_mmu_setmtt(0x40000000, 0xBFFFFFFF, 0x40000000, RW_NCNBXN); - /* IOP registers */ - rt_hw_mmu_setmtt(0xE0000000, 0xE02FFFFF, 0xE0000000, RW_NCNBXN); - /* no access to the SMC memory(enable it if you want) */ - /* SLCR, PS and CPU private registers, note we map more memory space as the - * entry is 1MB in size. */ - rt_hw_mmu_setmtt(0xF8000000, 0xF8FFFFFF, 0xF8000000, RW_NCNBXN); - - /*rt_hw_cpu_dump_page_table(MMUTable);*/ - - /* become clients for all domains */ - rt_hw_set_domain_register(0x55555555); - - rt_cpu_tlb_set(MMUTable); - - rt_cpu_mmu_enable(); - - rt_hw_cpu_icache_enable(); - rt_hw_cpu_dcache_enable(); -} - diff --git a/libcpu/arm/zynq7000/stack.c b/libcpu/arm/zynq7000/stack.c deleted file mode 100644 index b38dd160f7..0000000000 --- a/libcpu/arm/zynq7000/stack.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2011-09-23 Bernard the first version - * 2011-10-05 Bernard add thumb mode - * 2013-07-15 Bernard add Cortex-A8 support. - */ -#include <rtthread.h> -#include "zynq7000.h" - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - rt_uint32_t *stk; - - stack_addr += sizeof(rt_uint32_t); - stack_addr = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stack_addr, 8); - stk = (rt_uint32_t *)stack_addr; - *(--stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0xdeadbeef; /* r12 */ - *(--stk) = 0xdeadbeef; /* r11 */ - *(--stk) = 0xdeadbeef; /* r10 */ - *(--stk) = 0xdeadbeef; /* r9 */ - *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = 0xdeadbeef; /* r4 */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = 0xdeadbeef; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - - /* cpsr */ - if ((rt_uint32_t)tentry & 0x01) - *(--stk) = SVCMODE | 0x20; /* thumb mode */ - else - *(--stk) = SVCMODE; /* arm mode */ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} - diff --git a/libcpu/arm/zynq7000/start_gcc.S b/libcpu/arm/zynq7000/start_gcc.S deleted file mode 100644 index 18056f0ad9..0000000000 --- a/libcpu/arm/zynq7000/start_gcc.S +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -.equ Mode_USR, 0x10 -.equ Mode_FIQ, 0x11 -.equ Mode_IRQ, 0x12 -.equ Mode_SVC, 0x13 -.equ Mode_ABT, 0x17 -.equ Mode_UND, 0x1B -.equ Mode_SYS, 0x1F - -.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled -.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled - -.equ UND_Stack_Size, 0x00000000 -.equ SVC_Stack_Size, 0x00000000 -.equ ABT_Stack_Size, 0x00000000 -.equ FIQ_Stack_Size, 0x00000100 -.equ IRQ_Stack_Size, 0x00000100 -.equ USR_Stack_Size, 0x00000000 - -#define ISR_Stack_Size (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \ - FIQ_Stack_Size + IRQ_Stack_Size) - -/* stack */ -.globl stack_start -.globl stack_top - -.align 3 -.bss -stack_start: -.rept ISR_Stack_Size -.long 0 -.endr -stack_top: - -.text -/* reset entry */ -.globl _reset -_reset: - /* invalidate SCU */ - ldr r7, =0xF8F0000C - ldr r6, =0xFFFF - str r6, [r7] - - /* disable MMU */ - mrc p15, 0, r0, c1, c0, 0 /* read CP15 register 1 */ - bic r0, r0, #0x1 /* clear bit 0 */ - mcr p15, 0, r0, c1, c0, 0 /* write value back */ - - /* set the cpu to SVC32 mode and disable interrupt */ - mrs r0, cpsr - bic r0, r0, #0x1f - orr r0, r0, #0x13 - msr cpsr_c, r0 - - /* setup stack */ - bl stack_setup - - /* clear .bss */ - mov r0,#0 /* get a zero */ - ldr r1,=__bss_start /* bss start */ - ldr r2,=__bss_end /* bss end */ - -bss_loop: - cmp r1,r2 /* check if data to clear */ - strlo r0,[r1],#4 /* clear 4 bytes */ - blo bss_loop /* loop until done */ - - /* call C++ constructors of global objects */ - ldr r0, =__ctors_start__ - ldr r1, =__ctors_end__ - -ctor_loop: - cmp r0, r1 - beq ctor_end - ldr r2, [r0], #4 - stmfd sp!, {r0-r1} - mov lr, pc - bx r2 - ldmfd sp!, {r0-r1} - b ctor_loop -ctor_end: - - /* start RT-Thread Kernel */ - ldr pc, _rtthread_startup - -_rtthread_startup: - .word rtthread_startup - -stack_setup: - ldr r0, =stack_top - - @ Set the startup stack for svc - mov sp, r0 - - @ Enter Undefined Instruction Mode and set its Stack Pointer - msr cpsr_c, #Mode_UND|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #UND_Stack_Size - - @ Enter Abort Mode and set its Stack Pointer - msr cpsr_c, #Mode_ABT|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #ABT_Stack_Size - - @ Enter FIQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_FIQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #FIQ_Stack_Size - - @ Enter IRQ Mode and set its Stack Pointer - msr cpsr_c, #Mode_IRQ|I_Bit|F_Bit - mov sp, r0 - sub r0, r0, #IRQ_Stack_Size - - @ Switch back to SVC - msr cpsr_c, #Mode_SVC|I_Bit|F_Bit - - bx lr - -.section .text.isr, "ax" -/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq */ - .align 5 -.globl vector_fiq -vector_fiq: - stmfd sp!,{r0-r7,lr} - bl rt_hw_trap_fiq - ldmfd sp!,{r0-r7,lr} - subs pc,lr,#4 - -.globl rt_interrupt_enter -.globl rt_interrupt_leave -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread - - .align 5 -.globl vector_irq -vector_irq: - stmfd sp!, {r0-r12,lr} - bl rt_interrupt_enter - bl rt_hw_trap_irq - bl rt_interrupt_leave - - @ if rt_thread_switch_interrupt_flag set, jump to - @ rt_hw_context_switch_interrupt_do and don't return - ldr r0, =rt_thread_switch_interrupt_flag - ldr r1, [r0] - cmp r1, #1 - beq rt_hw_context_switch_interrupt_do - - ldmfd sp!, {r0-r12,lr} - subs pc, lr, #4 - -rt_hw_context_switch_interrupt_do: - mov r1, #0 @ clear flag - str r1, [r0] - - mov r1, sp @ r1 point to {r0-r3} in stack - add sp, sp, #4*4 - ldmfd sp!, {r4-r12,lr}@ reload saved registers - mrs r0, spsr @ get cpsr of interrupt thread - sub r2, lr, #4 @ save old task's pc to r2 - - @ Switch to SVC mode with no interrupt. - msr cpsr_c, #I_Bit|F_Bit|Mode_SVC - - stmfd sp!, {r2} @ push old task's pc - stmfd sp!, {r4-r12,lr}@ push old task's lr,r12-r4 - ldmfd r1, {r1-r4} @ restore r0-r3 of the interrupt thread - stmfd sp!, {r1-r4} @ push old task's r0-r3 - stmfd sp!, {r0} @ push old task's cpsr - - ldr r4, =rt_interrupt_from_thread - ldr r5, [r4] - str sp, [r5] @ store sp in preempted tasks's TCB - - ldr r6, =rt_interrupt_to_thread - ldr r7, [r6] - ldr sp, [r7] @ get new task's stack pointer - - ldmfd sp!, {r4} @ pop new task's cpsr to spsr - msr spsr_cxsf, r4 - - ldmfd sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr - - -.macro push_svc_reg - sub sp, sp, #17 * 4 @/* Sizeof(struct rt_hw_exp_stack) */ - stmia sp, {r0 - r12} @/* Calling r0-r12 */ - mov r0, sp - mrs r6, spsr @/* Save CPSR */ - str lr, [r0, #15*4] @/* Push PC */ - str r6, [r0, #16*4] @/* Push CPSR */ - cps #Mode_SVC - str sp, [r0, #13*4] @/* Save calling SP */ - str lr, [r0, #14*4] @/* Save calling PC */ -.endm - - .align 5 - .globl vector_swi -vector_swi: - push_svc_reg - bl rt_hw_trap_swi - b . - - .align 5 - .globl vector_undef -vector_undef: - push_svc_reg - bl rt_hw_trap_undef - b . - - .align 5 - .globl vector_pabt -vector_pabt: - push_svc_reg - bl rt_hw_trap_pabt - b . - - .align 5 - .globl vector_dabt -vector_dabt: - push_svc_reg - bl rt_hw_trap_dabt - b . - - .align 5 - .globl vector_resv -vector_resv: - push_svc_reg - bl rt_hw_trap_resv - b . diff --git a/libcpu/arm/zynq7000/trap.c b/libcpu/arm/zynq7000/trap.c deleted file mode 100644 index 6243ea82b4..0000000000 --- a/libcpu/arm/zynq7000/trap.c +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-20 Bernard first version - */ - -#include <rtthread.h> -#include <rthw.h> - -#include "zynq7000.h" -#include "gic.h" - -extern struct rt_thread *rt_current_thread; -#ifdef RT_USING_FINSH -extern long list_thread(void); -#endif - -/** - * this function will show registers of CPU - * - * @param regs the registers point - */ -void rt_hw_show_register (struct rt_hw_exp_stack *regs) -{ - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10); - rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("cpsr:0x%08x\n", regs->cpsr); -} - -/** - * When comes across an instruction which it cannot handle, - * it takes the undefined instruction trap. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_undef(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("undefined instruction:\n"); - rt_hw_show_register(regs); -#ifdef RT_USING_FINSH - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * The software interrupt instruction (SWI) is used for entering - * Supervisor mode, usually to request a particular supervisor - * function. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_swi(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("software interrupt:\n"); - rt_hw_show_register(regs); -#ifdef RT_USING_FINSH - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during an instruction prefetch. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("prefetch abort:\n"); - rt_hw_show_register(regs); -#ifdef RT_USING_FINSH - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * An abort indicates that the current memory access cannot be completed, - * which occurs during a data access. - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("data abort:"); - rt_hw_show_register(regs); -#ifdef RT_USING_FINSH - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -/** - * Normally, system will never reach here - * - * @param regs system registers - * - * @note never invoke this function in application - */ -void rt_hw_trap_resv(struct rt_hw_exp_stack *regs) -{ - rt_kprintf("reserved trap:\n"); - rt_hw_show_register(regs); -#ifdef RT_USING_FINSH - list_thread(); -#endif - rt_hw_cpu_shutdown(); -} - -#define GIC_ACK_INTID_MASK 0x000003ff - -void rt_hw_trap_irq() -{ - void *param; - unsigned long ir; - unsigned long fullir; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - fullir = arm_gic_get_active_irq(0); - ir = fullir & GIC_ACK_INTID_MASK; - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; - if (isr_func) - { - param = isr_table[ir].param; - /* turn to interrupt service routine */ - isr_func(ir, param); - } - - /* end of interrupt */ - arm_gic_ack(0, fullir); -} - -void rt_hw_trap_fiq() -{ - void *param; - unsigned long ir; - unsigned long fullir; - rt_isr_handler_t isr_func; - extern struct rt_irq_desc isr_table[]; - - fullir = arm_gic_get_active_irq(0); - ir = fullir & GIC_ACK_INTID_MASK; - - /* get interrupt service routine */ - isr_func = isr_table[ir].handler; - param = isr_table[ir].param; - - /* turn to interrupt service routine */ - isr_func(ir, param); - - /* end of interrupt */ - arm_gic_ack(0, fullir); -} - diff --git a/libcpu/arm/zynq7000/vector_gcc.S b/libcpu/arm/zynq7000/vector_gcc.S deleted file mode 100644 index 60d3c6cf1d..0000000000 --- a/libcpu/arm/zynq7000/vector_gcc.S +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2006-2018, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2013-07-05 Bernard the first version - */ - -.section .vectors, "ax" -.code 32 - -.globl system_vectors -system_vectors: - ldr pc, _vector_reset - ldr pc, _vector_undef - ldr pc, _vector_swi - ldr pc, _vector_pabt - ldr pc, _vector_dabt - ldr pc, _vector_resv - ldr pc, _vector_irq - ldr pc, _vector_fiq - -.globl _reset -.globl vector_undef -.globl vector_swi -.globl vector_pabt -.globl vector_dabt -.globl vector_resv -.globl vector_irq -.globl vector_fiq - -_vector_reset: - .word _reset -_vector_undef: - .word vector_undef -_vector_swi: - .word vector_swi -_vector_pabt: - .word vector_pabt -_vector_dabt: - .word vector_dabt -_vector_resv: - .word vector_resv -_vector_irq: - .word vector_irq -_vector_fiq: - .word vector_fiq - -.balignl 16,0xdeadbeef diff --git a/libcpu/arm/zynqmp-r5/armv7.h b/libcpu/arm/zynqmp-r5/armv7.h index 4c34d7da8b..c70d210709 100644 --- a/libcpu/arm/zynqmp-r5/armv7.h +++ b/libcpu/arm/zynqmp-r5/armv7.h @@ -1,23 +1,10 @@ #ifndef __ARMV7_H__ #define __ARMV7_H__ /* - * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd + * Copyright (c) 2006-2021, RT-Thread Development Team * - * All rights reserved. + * SPDX-License-Identifier: Apache-2.0 * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ #ifndef VFP_DATA_NR @@ -27,23 +14,23 @@ /* the exception stack without VFP registers */ struct rt_hw_exp_stack { - unsigned long r0; - unsigned long r1; - unsigned long r2; - unsigned long r3; - unsigned long r4; - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long r8; - unsigned long r9; - unsigned long r10; - unsigned long fp; - unsigned long ip; - unsigned long sp; - unsigned long lr; - unsigned long pc; - unsigned long cpsr; + unsigned long r0; + unsigned long r1; + unsigned long r2; + unsigned long r3; + unsigned long r4; + unsigned long r5; + unsigned long r6; + unsigned long r7; + unsigned long r8; + unsigned long r9; + unsigned long r10; + unsigned long fp; + unsigned long ip; + unsigned long sp; + unsigned long lr; + unsigned long pc; + unsigned long cpsr; }; #define USERMODE 0x10 diff --git a/libcpu/arm/zynqmp-r5/cache.c b/libcpu/arm/zynqmp-r5/cache.c index aa8517e254..d6e7cd2d6d 100644 --- a/libcpu/arm/zynqmp-r5/cache.c +++ b/libcpu/arm/zynqmp-r5/cache.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #include <rthw.h> #include <rtdef.h> @@ -13,154 +13,154 @@ #include "xpseudo_asm_gcc.h" #include "xreg_cortexr5.h" -#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ +#define IRQ_FIQ_MASK 0xC0 /* Mask IRQ and FIQ interrupts in cpsr */ typedef intptr_t INTPTR; typedef rt_uint32_t u32; #if defined (__GNUC__) #define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) #define asm_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) #define asm_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) #define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) #elif defined (__ICCARM__) #define asm_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ - XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) + XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param)) #define asm_clean_inval_dc_line_sw(param) __asm volatile("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) + XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param)) #define asm_clean_inval_dc_line_mva_poc(param) __asm volatile("mcr " \ - XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) + XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param)) #define asm_inval_ic_line_mva_pou(param) __asm volatile("mcr " \ - XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) + XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param)) #endif void Xil_ICacheInvalidateRange(INTPTR adr, u32 len) { - u32 LocalAddr = adr; - const u32 cacheline = 32U; - u32 end; - u32 currmask; + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0x00000000U) { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = LocalAddr + len; - LocalAddr = LocalAddr & ~(cacheline - 1U); + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); + if (len != 0x00000000U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr = LocalAddr & ~(cacheline - 1U); - /* Select cache L0 I-cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); + /* Select cache L0 I-cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U); - while (LocalAddr < end) { + while (LocalAddr < end) { - /* Invalidate L1 I-cache line */ - asm_inval_ic_line_mva_pou(LocalAddr); + /* Invalidate L1 I-cache line */ + asm_inval_ic_line_mva_pou(LocalAddr); - LocalAddr += cacheline; - } - } + LocalAddr += cacheline; + } + } - /* Wait for invalidate to complete */ - dsb(); - mtcpsr(currmask); + /* Wait for invalidate to complete */ + dsb(); + mtcpsr(currmask); } void Xil_DCacheFlushLine(INTPTR adr) { - u32 currmask; + u32 currmask; - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0); - mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); + mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F))); - /* Wait for flush to complete */ - dsb(); - mtcpsr(currmask); + /* Wait for flush to complete */ + dsb(); + mtcpsr(currmask); } void Xil_DCacheInvalidateRange(INTPTR adr, u32 len) { - const u32 cacheline = 32U; - u32 end; - u32 tempadr = adr; - u32 tempend; - u32 currmask; + const u32 cacheline = 32U; + u32 end; + u32 tempadr = adr; + u32 tempend; + u32 currmask; - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0U) { - end = tempadr + len; - tempend = end; - /* Select L1 Data cache in CSSR */ - mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); + if (len != 0U) { + end = tempadr + len; + tempend = end; + /* Select L1 Data cache in CSSR */ + mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U); - if ((tempadr & (cacheline-1U)) != 0U) { - tempadr &= (~(cacheline - 1U)); + if ((tempadr & (cacheline-1U)) != 0U) { + tempadr &= (~(cacheline - 1U)); - Xil_DCacheFlushLine(tempadr); - } - if ((tempend & (cacheline-1U)) != 0U) { - tempend &= (~(cacheline - 1U)); + Xil_DCacheFlushLine(tempadr); + } + if ((tempend & (cacheline-1U)) != 0U) { + tempend &= (~(cacheline - 1U)); - Xil_DCacheFlushLine(tempend); - } + Xil_DCacheFlushLine(tempend); + } - while (tempadr < tempend) { + while (tempadr < tempend) { - /* Invalidate Data cache line */ - asm_inval_dc_line_mva_poc(tempadr); + /* Invalidate Data cache line */ + asm_inval_dc_line_mva_poc(tempadr); - tempadr += cacheline; - } - } + tempadr += cacheline; + } + } - dsb(); - mtcpsr(currmask); + dsb(); + mtcpsr(currmask); } void Xil_DCacheFlushRange(INTPTR adr, u32 len) { - u32 LocalAddr = adr; - const u32 cacheline = 32U; - u32 end; - u32 currmask; + u32 LocalAddr = adr; + const u32 cacheline = 32U; + u32 end; + u32 currmask; - currmask = mfcpsr(); - mtcpsr(currmask | IRQ_FIQ_MASK); + currmask = mfcpsr(); + mtcpsr(currmask | IRQ_FIQ_MASK); - if (len != 0x00000000U) { - /* Back the starting address up to the start of a cache line - * perform cache operations until adr+len - */ - end = LocalAddr + len; - LocalAddr &= ~(cacheline - 1U); + if (len != 0x00000000U) { + /* Back the starting address up to the start of a cache line + * perform cache operations until adr+len + */ + end = LocalAddr + len; + LocalAddr &= ~(cacheline - 1U); - while (LocalAddr < end) { - /* Flush Data cache line */ - asm_clean_inval_dc_line_mva_poc(LocalAddr); + while (LocalAddr < end) { + /* Flush Data cache line */ + asm_clean_inval_dc_line_mva_poc(LocalAddr); - LocalAddr += cacheline; - } - } - dsb(); - mtcpsr(currmask); + LocalAddr += cacheline; + } + } + dsb(); + mtcpsr(currmask); } void rt_hw_cpu_icache_ops(int ops, void *addr, int size) @@ -179,22 +179,22 @@ void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) rt_base_t rt_hw_cpu_icache_status(void) { - register u32 CtrlReg; + register u32 CtrlReg; #if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); #elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); #endif - return CtrlReg & XREG_CP15_CONTROL_I_BIT; + return CtrlReg & XREG_CP15_CONTROL_I_BIT; } rt_base_t rt_hw_cpu_dcache_status(void) { - register u32 CtrlReg; + register u32 CtrlReg; #if defined (__GNUC__) - CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); + CtrlReg = mfcp(XREG_CP15_SYS_CONTROL); #elif defined (__ICCARM__) - mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); + mfcp(XREG_CP15_SYS_CONTROL,CtrlReg); #endif - return CtrlReg & XREG_CP15_CONTROL_C_BIT; + return CtrlReg & XREG_CP15_CONTROL_C_BIT; } diff --git a/libcpu/arm/zynqmp-r5/cpu.c b/libcpu/arm/zynqmp-r5/cpu.c index a2e3b85dc7..d0f1b0204c 100644 --- a/libcpu/arm/zynqmp-r5/cpu.c +++ b/libcpu/arm/zynqmp-r5/cpu.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #include <rthw.h> diff --git a/libcpu/arm/zynqmp-r5/gic.c b/libcpu/arm/zynqmp-r5/gic.c index 3acefbc9bf..67360d93ce 100644 --- a/libcpu/arm/zynqmp-r5/gic.c +++ b/libcpu/arm/zynqmp-r5/gic.c @@ -1,18 +1,18 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #include <rtthread.h> #include "board.h" #include "gic.h" -/* ZynqMP-RPU uses the Arm PL-390 generic interrupt controller that is +/* ZynqMP-RPU uses the Arm PL-390 generic interrupt controller that is * compliant to the GICv1 architecture specification. */ struct arm_gic @@ -39,12 +39,12 @@ static struct arm_gic _gic_table[ARM_GIC_MAX_NR]; #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4) #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4) #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4) -#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) +#define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4) #define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4) #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4) #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4) #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4) -#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) +#define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00) #define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8) static unsigned int _gic_max_irq; @@ -206,4 +206,4 @@ void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq) void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq) { /* SGI will be cleared automatically. */ -}
\ No newline at end of file +} diff --git a/libcpu/arm/zynqmp-r5/gic.h b/libcpu/arm/zynqmp-r5/gic.h index 7cffec3f88..3f591c0652 100644 --- a/libcpu/arm/zynqmp-r5/gic.h +++ b/libcpu/arm/zynqmp-r5/gic.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #ifndef __GIC_H__ diff --git a/libcpu/arm/zynqmp-r5/interrupt.c b/libcpu/arm/zynqmp-r5/interrupt.c index 12ba638345..fa37674761 100644 --- a/libcpu/arm/zynqmp-r5/interrupt.c +++ b/libcpu/arm/zynqmp-r5/interrupt.c @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #include <rthw.h> @@ -130,4 +130,4 @@ void rt_hw_interrupt_trigger(int vector) void rt_hw_interrupt_clear(int vector) { /* SGI will be cleared automatically. */ -}
\ No newline at end of file +} diff --git a/libcpu/arm/zynqmp-r5/interrupt.h b/libcpu/arm/zynqmp-r5/interrupt.h index 71459fa0a9..35490a047b 100644 --- a/libcpu/arm/zynqmp-r5/interrupt.h +++ b/libcpu/arm/zynqmp-r5/interrupt.h @@ -1,11 +1,11 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2020-03-19 WangHuachen first version + * 2020-03-19 WangHuachen first version */ #ifndef __INTERRUPT_H__ diff --git a/libcpu/arm/zynqmp-r5/mpu.c b/libcpu/arm/zynqmp-r5/mpu.c index dc33a5fe65..fc2ae7dc44 100644 --- a/libcpu/arm/zynqmp-r5/mpu.c +++ b/libcpu/arm/zynqmp-r5/mpu.c @@ -14,8 +14,8 @@ * * Ver Who Date Changes * ----- ---- -------- --------------------------------------------------- -* 5.00 pkp 02/20/14 First release -* 5.04 pkp 12/18/15 Updated MPU initialization as per the proper address map +* 5.00 pkp 02/20/14 First release +* 5.04 pkp 12/18/15 Updated MPU initialization as per the proper address map * 6.00 pkp 06/27/16 moving the Init_MPU code to .boot section since it is a * part of processor boot process * 6.2 mus 01/27/17 Updated to support IAR compiler @@ -46,37 +46,37 @@ typedef rt_uint32_t u32; /************************** Variable Definitions *****************************/ static const struct { - u64 size; - unsigned int encoding; + u64 size; + unsigned int encoding; }region_size[] = { - { 0x20, REGION_32B }, - { 0x40, REGION_64B }, - { 0x80, REGION_128B }, - { 0x100, REGION_256B }, - { 0x200, REGION_512B }, - { 0x400, REGION_1K }, - { 0x800, REGION_2K }, - { 0x1000, REGION_4K }, - { 0x2000, REGION_8K }, - { 0x4000, REGION_16K }, - { 0x8000, REGION_32K }, - { 0x10000, REGION_64K }, - { 0x20000, REGION_128K }, - { 0x40000, REGION_256K }, - { 0x80000, REGION_512K }, - { 0x100000, REGION_1M }, - { 0x200000, REGION_2M }, - { 0x400000, REGION_4M }, - { 0x800000, REGION_8M }, - { 0x1000000, REGION_16M }, - { 0x2000000, REGION_32M }, - { 0x4000000, REGION_64M }, - { 0x8000000, REGION_128M }, - { 0x10000000, REGION_256M }, - { 0x20000000, REGION_512M }, - { 0x40000000, REGION_1G }, - { 0x80000000, REGION_2G }, - { 0x100000000, REGION_4G }, + { 0x20, REGION_32B }, + { 0x40, REGION_64B }, + { 0x80, REGION_128B }, + { 0x100, REGION_256B }, + { 0x200, REGION_512B }, + { 0x400, REGION_1K }, + { 0x800, REGION_2K }, + { 0x1000, REGION_4K }, + { 0x2000, REGION_8K }, + { 0x4000, REGION_16K }, + { 0x8000, REGION_32K }, + { 0x10000, REGION_64K }, + { 0x20000, REGION_128K }, + { 0x40000, REGION_256K }, + { 0x80000, REGION_512K }, + { 0x100000, REGION_1M }, + { 0x200000, REGION_2M }, + { 0x400000, REGION_4M }, + { 0x800000, REGION_8M }, + { 0x1000000, REGION_16M }, + { 0x2000000, REGION_32M }, + { 0x4000000, REGION_64M }, + { 0x8000000, REGION_128M }, + { 0x10000000, REGION_256M }, + { 0x20000000, REGION_512M }, + { 0x40000000, REGION_1G }, + { 0x80000000, REGION_2G }, + { 0x100000000, REGION_4G }, }; /************************** Function Prototypes ******************************/ @@ -96,129 +96,129 @@ static void Xil_DisableMPURegions(void); * MPU with default memory attributes for rest of address range for Cortex R5 * processor. * -* @param None. +* @param None. * -* @return None. +* @return None. * * ******************************************************************************/ void Init_MPU(void) { - u32 Addr; - u32 RegSize = 0U; - u32 Attrib; - u32 RegNum = 0, i, Offset = 0; - u64 size; + u32 Addr; + u32 RegSize = 0U; + u32 Attrib; + u32 RegNum = 0, i, Offset = 0; + u64 size; - Xil_DisableMPURegions(); + Xil_DisableMPURegions(); - Addr = 0x00000000U; -#ifdef XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR - /* If the DDR is present, configure region as per DDR size */ - size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1; - if (size < 0x80000000) { - /* Lookup the size. */ - for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) { - if (size <= region_size[i].size) { - RegSize = region_size[i].encoding; + Addr = 0x00000000U; +#ifdef XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR + /* If the DDR is present, configure region as per DDR size */ + size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1; + if (size < 0x80000000) { + /* Lookup the size. */ + for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) { + if (size <= region_size[i].size) { + RegSize = region_size[i].encoding; - /* Check if DDR size is in power of 2*/ - if ( XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR == 0x100000) - Offset = XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR; - if (region_size[i].size > (size + Offset + 1)) { - rt_kprintf ("WARNING: DDR size mapped to Cortexr5 processor is not \ - in power of 2. As processor allocates MPU regions size \ - in power of 2, address range %llx to %x has been \ - incorrectly mapped as normal memory \n", \ - region_size[i].size - 1, ((u32)XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR + 1)); - } - break; - } - } - } else { - /* if the DDR size is > 2GB, truncate it to 2GB */ - RegSize = REGION_2G; - } + /* Check if DDR size is in power of 2*/ + if ( XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR == 0x100000) + Offset = XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR; + if (region_size[i].size > (size + Offset + 1)) { + rt_kprintf ("WARNING: DDR size mapped to Cortexr5 processor is not \ + in power of 2. As processor allocates MPU regions size \ + in power of 2, address range %llx to %x has been \ + incorrectly mapped as normal memory \n", \ + region_size[i].size - 1, ((u32)XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR + 1)); + } + break; + } + } + } else { + /* if the DDR size is > 2GB, truncate it to 2GB */ + RegSize = REGION_2G; + } #else - /* For DDRless system, configure region for TCM */ - RegSize = REGION_256K; + /* For DDRless system, configure region for TCM */ + RegSize = REGION_256K; #endif - Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* - * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL. - * 512 MB - LPD-PL interface - * 256 MB - FPD-PL (HPM0) interface - * 256 MB - FPD-PL (HPM1) interface - */ - Addr = 0x80000000; - RegSize = REGION_1G; - Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* + * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL. + * 512 MB - LPD-PL interface + * 256 MB - FPD-PL (HPM0) interface + * 256 MB - FPD-PL (HPM1) interface + */ + Addr = 0x80000000; + RegSize = REGION_1G; + Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */ - Addr = 0xC0000000U; - RegSize = REGION_512M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */ + Addr = 0xC0000000U; + RegSize = REGION_512M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */ - Addr = 0xE0000000U; - RegSize = REGION_256M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */ + Addr = 0xE0000000U; + RegSize = REGION_256M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */ - Addr = 0xF8000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */ + Addr = 0xF8000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */ - Addr = 0xF9000000U; - RegSize = REGION_1M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */ + Addr = 0xF9000000U; + RegSize = REGION_1M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */ - Addr = 0xFD000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */ + Addr = 0xFD000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */ - Addr = 0xFE000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */ + Addr = 0xFE000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* - * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves, - * CSU, PMU, TCM, OCM - */ - Addr = 0xFF000000U; - RegSize = REGION_16M; - Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - RegNum++; + /* + * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves, + * CSU, PMU, TCM, OCM + */ + Addr = 0xFF000000U; + RegSize = REGION_16M; + Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + RegNum++; - /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */ - Addr = 0xFFFC0000U; - RegSize = REGION_256K; - Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ; - Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); + /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */ + Addr = 0xFFFC0000U; + RegSize = REGION_256K; + Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ; + Xil_SetAttribute(Addr,RegSize,RegNum, Attrib); - /* A total of 10 MPU regions are allocated with another 6 being free for users */ + /* A total of 10 MPU regions are allocated with another 6 being free for users */ } @@ -228,28 +228,28 @@ void Init_MPU(void) * of the region size defined by reg_size having attributes attrib of region number * reg_num * -* @param addr is the address for which attributes are to be set. -* @param attrib specifies the attributes for that memory region. -* @param reg_size specifies the size for that memory region. -* @param reg_num specifies the number for that memory region. -* @return None. +* @param addr is the address for which attributes are to be set. +* @param attrib specifies the attributes for that memory region. +* @param reg_size specifies the size for that memory region. +* @param reg_num specifies the number for that memory region. +* @return None. * * ******************************************************************************/ static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) { - u32 Local_reg_size = reg_size; + u32 Local_reg_size = reg_size; - Local_reg_size = Local_reg_size<<1U; - Local_reg_size |= REGION_EN; - dsb(); - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); - isb(); - mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */ - mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */ - mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/ - dsb(); - isb(); /* synchronize context on this processor */ + Local_reg_size = Local_reg_size<<1U; + Local_reg_size |= REGION_EN; + dsb(); + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num); + isb(); + mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */ + mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */ + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/ + dsb(); + isb(); /* synchronize context on this processor */ } @@ -257,29 +257,29 @@ static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) * * Disable all the MPU regions if any of them is enabled * -* @param None. +* @param None. * -* @return None. +* @return None. * * ******************************************************************************/ static void Xil_DisableMPURegions(void) { - u32 Temp = 0U; - u32 Index = 0U; - for (Index = 0; Index <= 15; Index++) { - mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); + u32 Temp = 0U; + u32 Index = 0U; + for (Index = 0; Index <= 15; Index++) { + mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index); #if defined (__GNUC__) - Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); + Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN); #elif defined (__ICCARM__) - mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); + mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); #endif - Temp &= (~REGION_EN); - dsb(); - mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); - dsb(); - isb(); - } + Temp &= (~REGION_EN); + dsb(); + mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp); + dsb(); + isb(); + } } diff --git a/libcpu/arm/zynqmp-r5/stack.c b/libcpu/arm/zynqmp-r5/stack.c index c8ba712c49..20a6e23987 100644 --- a/libcpu/arm/zynqmp-r5/stack.c +++ b/libcpu/arm/zynqmp-r5/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/zynqmp-r5/trap.c b/libcpu/arm/zynqmp-r5/trap.c index 7a48a3c190..64d4cbf5e8 100644 --- a/libcpu/arm/zynqmp-r5/trap.c +++ b/libcpu/arm/zynqmp-r5/trap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h b/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h index f3f978d9eb..7a65ef6ece 100644 --- a/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h +++ b/libcpu/arm/zynqmp-r5/xpseudo_asm_gcc.h @@ -36,7 +36,7 @@ * * Ver Who Date Changes * ----- -------- -------- ----------------------------------------------- -* 5.00 pkp 05/21/14 First release +* 5.00 pkp 05/21/14 First release * 6.0 mus 07/27/16 Consolidated file for a53,a9 and r5 processors * </pre> * @@ -59,38 +59,38 @@ extern "C" { /***************** Macros (Inline Functions) Definitions ********************/ /* necessary for pre-processor */ -#define stringify(s) tostring(s) -#define tostring(s) #s +#define stringify(s) tostring(s) +#define tostring(s) #s #if defined (__aarch64__) /* pseudo assembler instructions */ -#define mfcpsr() ({rt_uint32_t rval = 0U; \ - asm volatile("mrs %0, DAIF" : "=r" (rval));\ - rval;\ - }) +#define mfcpsr() ({rt_uint32_t rval = 0U; \ + asm volatile("mrs %0, DAIF" : "=r" (rval));\ + rval;\ + }) #define mtcpsr(v) __asm__ __volatile__ ("msr DAIF, %0" : : "r" (v)) -#define cpsiei() //__asm__ __volatile__("cpsie i\n") -#define cpsidi() //__asm__ __volatile__("cpsid i\n") +#define cpsiei() //__asm__ __volatile__("cpsie i\n") +#define cpsidi() //__asm__ __volatile__("cpsid i\n") -#define cpsief() //__asm__ __volatile__("cpsie f\n") -#define cpsidf() //__asm__ __volatile__("cpsid f\n") +#define cpsief() //__asm__ __volatile__("cpsie f\n") +#define cpsidf() //__asm__ __volatile__("cpsid f\n") -#define mtgpr(rn, v) /*__asm__ __volatile__(\ - "mov r" stringify(rn) ", %0 \n"\ - : : "r" (v)\ - )*/ +#define mtgpr(rn, v) /*__asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + )*/ -#define mfgpr(rn) /*({rt_uint32_t rval; \ - __asm__ __volatile__(\ - "mov %0,r" stringify(rn) "\n"\ - : "=r" (rval)\ - );\ - rval;\ - })*/ +#define mfgpr(rn) /*({rt_uint32_t rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + })*/ /* memory synchronization operations */ @@ -105,13 +105,13 @@ extern "C" { /* Memory Operations */ -#define ldr(adr) ({u64 rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) +#define ldr(adr) ({u64 rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) #define mfelrel3() ({u64 rval = 0U; \ asm volatile("mrs %0, ELR_EL3" : "=r" (rval));\ @@ -123,39 +123,39 @@ extern "C" { #else /* pseudo assembler instructions */ -#define mfcpsr() ({rt_uint32_t rval = 0U; \ - __asm__ __volatile__(\ - "mrs %0, cpsr\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) +#define mfcpsr() ({rt_uint32_t rval = 0U; \ + __asm__ __volatile__(\ + "mrs %0, cpsr\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) -#define mtcpsr(v) __asm__ __volatile__(\ - "msr cpsr,%0\n"\ - : : "r" (v)\ - ) +#define mtcpsr(v) __asm__ __volatile__(\ + "msr cpsr,%0\n"\ + : : "r" (v)\ + ) -#define cpsiei() __asm__ __volatile__("cpsie i\n") -#define cpsidi() __asm__ __volatile__("cpsid i\n") +#define cpsiei() __asm__ __volatile__("cpsie i\n") +#define cpsidi() __asm__ __volatile__("cpsid i\n") -#define cpsief() __asm__ __volatile__("cpsie f\n") -#define cpsidf() __asm__ __volatile__("cpsid f\n") +#define cpsief() __asm__ __volatile__("cpsie f\n") +#define cpsidf() __asm__ __volatile__("cpsid f\n") -#define mtgpr(rn, v) __asm__ __volatile__(\ - "mov r" stringify(rn) ", %0 \n"\ - : : "r" (v)\ - ) +#define mtgpr(rn, v) __asm__ __volatile__(\ + "mov r" stringify(rn) ", %0 \n"\ + : : "r" (v)\ + ) -#define mfgpr(rn) ({rt_uint32_t rval; \ - __asm__ __volatile__(\ - "mov %0,r" stringify(rn) "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) +#define mfgpr(rn) ({rt_uint32_t rval; \ + __asm__ __volatile__(\ + "mov %0,r" stringify(rn) "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) /* memory synchronization operations */ @@ -170,72 +170,72 @@ extern "C" { /* Memory Operations */ -#define ldr(adr) ({rt_uint32_t rval; \ - __asm__ __volatile__(\ - "ldr %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) +#define ldr(adr) ({rt_uint32_t rval; \ + __asm__ __volatile__(\ + "ldr %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) #endif -#define ldrb(adr) ({rt_uint8_t rval; \ - __asm__ __volatile__(\ - "ldrb %0,[%1]"\ - : "=r" (rval) : "r" (adr)\ - );\ - rval;\ - }) +#define ldrb(adr) ({rt_uint8_t rval; \ + __asm__ __volatile__(\ + "ldrb %0,[%1]"\ + : "=r" (rval) : "r" (adr)\ + );\ + rval;\ + }) -#define str(adr, val) __asm__ __volatile__(\ - "str %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) +#define str(adr, val) __asm__ __volatile__(\ + "str %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) -#define strb(adr, val) __asm__ __volatile__(\ - "strb %0,[%1]\n"\ - : : "r" (val), "r" (adr)\ - ) +#define strb(adr, val) __asm__ __volatile__(\ + "strb %0,[%1]\n"\ + : : "r" (val), "r" (adr)\ + ) /* Count leading zeroes (clz) */ -#define clz(arg) ({rt_uint8_t rval; \ - __asm__ __volatile__(\ - "clz %0,%1"\ - : "=r" (rval) : "r" (arg)\ - );\ - rval;\ - }) +#define clz(arg) ({rt_uint8_t rval; \ + __asm__ __volatile__(\ + "clz %0,%1"\ + : "=r" (rval) : "r" (arg)\ + );\ + rval;\ + }) #if defined (__aarch64__) -#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) -#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) +#define mtcpdc(reg,val) __asm__ __volatile__("dc " #reg ",%0" : : "r" (val)) +#define mtcpic(reg,val) __asm__ __volatile__("ic " #reg ",%0" : : "r" (val)) -#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) -#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) -#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) +#define mtcpicall(reg) __asm__ __volatile__("ic " #reg) +#define mtcptlbi(reg) __asm__ __volatile__("tlbi " #reg) +#define mtcpat(reg,val) __asm__ __volatile__("at " #reg ",%0" : : "r" (val)) /* CP15 operations */ -#define mfcp(reg) ({u64 rval = 0U;\ - __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ - rval;\ - }) +#define mfcp(reg) ({u64 rval = 0U;\ + __asm__ __volatile__("mrs %0, " #reg : "=r" (rval));\ + rval;\ + }) -#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) +#define mtcp(reg,val) __asm__ __volatile__("msr " #reg ",%0" : : "r" (val)) #else /* CP15 operations */ -#define mtcp(rn, v) __asm__ __volatile__(\ - "mcr " rn "\n"\ - : : "r" (v)\ - ); +#define mtcp(rn, v) __asm__ __volatile__(\ + "mcr " rn "\n"\ + : : "r" (v)\ + ); -#define mfcp(rn) ({rt_uint32_t rval = 0U; \ - __asm__ __volatile__(\ - "mrc " rn "\n"\ - : "=r" (rval)\ - );\ - rval;\ - }) +#define mfcp(rn) ({rt_uint32_t rval = 0U; \ + __asm__ __volatile__(\ + "mrc " rn "\n"\ + : "=r" (rval)\ + );\ + rval;\ + }) #endif /************************** Variable Definitions ****************************/ diff --git a/libcpu/arm/zynqmp-r5/xreg_cortexr5.h b/libcpu/arm/zynqmp-r5/xreg_cortexr5.h index 263f213567..9c0ae2b440 100644 --- a/libcpu/arm/zynqmp-r5/xreg_cortexr5.h +++ b/libcpu/arm/zynqmp-r5/xreg_cortexr5.h @@ -23,86 +23,86 @@ * </pre> * ******************************************************************************/ -#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */ -#define XREG_CORTEXR5_H /* by using protection macros */ +#ifndef XREG_CORTEXR5_H /* prevent circular inclusions */ +#define XREG_CORTEXR5_H /* by using protection macros */ #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /* GPRs */ -#define XREG_GPR0 r0 -#define XREG_GPR1 r1 -#define XREG_GPR2 r2 -#define XREG_GPR3 r3 -#define XREG_GPR4 r4 -#define XREG_GPR5 r5 -#define XREG_GPR6 r6 -#define XREG_GPR7 r7 -#define XREG_GPR8 r8 -#define XREG_GPR9 r9 -#define XREG_GPR10 r10 -#define XREG_GPR11 r11 -#define XREG_GPR12 r12 -#define XREG_GPR13 r13 -#define XREG_GPR14 r14 -#define XREG_GPR15 r15 -#define XREG_CPSR cpsr +#define XREG_GPR0 r0 +#define XREG_GPR1 r1 +#define XREG_GPR2 r2 +#define XREG_GPR3 r3 +#define XREG_GPR4 r4 +#define XREG_GPR5 r5 +#define XREG_GPR6 r6 +#define XREG_GPR7 r7 +#define XREG_GPR8 r8 +#define XREG_GPR9 r9 +#define XREG_GPR10 r10 +#define XREG_GPR11 r11 +#define XREG_GPR12 r12 +#define XREG_GPR13 r13 +#define XREG_GPR14 r14 +#define XREG_GPR15 r15 +#define XREG_CPSR cpsr /* Coprocessor number defines */ -#define XREG_CP0 0 -#define XREG_CP1 1 -#define XREG_CP2 2 -#define XREG_CP3 3 -#define XREG_CP4 4 -#define XREG_CP5 5 -#define XREG_CP6 6 -#define XREG_CP7 7 -#define XREG_CP8 8 -#define XREG_CP9 9 -#define XREG_CP10 10 -#define XREG_CP11 11 -#define XREG_CP12 12 -#define XREG_CP13 13 -#define XREG_CP14 14 -#define XREG_CP15 15 +#define XREG_CP0 0 +#define XREG_CP1 1 +#define XREG_CP2 2 +#define XREG_CP3 3 +#define XREG_CP4 4 +#define XREG_CP5 5 +#define XREG_CP6 6 +#define XREG_CP7 7 +#define XREG_CP8 8 +#define XREG_CP9 9 +#define XREG_CP10 10 +#define XREG_CP11 11 +#define XREG_CP12 12 +#define XREG_CP13 13 +#define XREG_CP14 14 +#define XREG_CP15 15 /* Coprocessor control register defines */ -#define XREG_CR0 cr0 -#define XREG_CR1 cr1 -#define XREG_CR2 cr2 -#define XREG_CR3 cr3 -#define XREG_CR4 cr4 -#define XREG_CR5 cr5 -#define XREG_CR6 cr6 -#define XREG_CR7 cr7 -#define XREG_CR8 cr8 -#define XREG_CR9 cr9 -#define XREG_CR10 cr10 -#define XREG_CR11 cr11 -#define XREG_CR12 cr12 -#define XREG_CR13 cr13 -#define XREG_CR14 cr14 -#define XREG_CR15 cr15 +#define XREG_CR0 cr0 +#define XREG_CR1 cr1 +#define XREG_CR2 cr2 +#define XREG_CR3 cr3 +#define XREG_CR4 cr4 +#define XREG_CR5 cr5 +#define XREG_CR6 cr6 +#define XREG_CR7 cr7 +#define XREG_CR8 cr8 +#define XREG_CR9 cr9 +#define XREG_CR10 cr10 +#define XREG_CR11 cr11 +#define XREG_CR12 cr12 +#define XREG_CR13 cr13 +#define XREG_CR14 cr14 +#define XREG_CR15 cr15 /* Current Processor Status Register (CPSR) Bits */ -#define XREG_CPSR_THUMB_MODE 0x20U -#define XREG_CPSR_MODE_BITS 0x1FU -#define XREG_CPSR_SYSTEM_MODE 0x1FU -#define XREG_CPSR_UNDEFINED_MODE 0x1BU -#define XREG_CPSR_DATA_ABORT_MODE 0x17U -#define XREG_CPSR_SVC_MODE 0x13U -#define XREG_CPSR_IRQ_MODE 0x12U -#define XREG_CPSR_FIQ_MODE 0x11U -#define XREG_CPSR_USER_MODE 0x10U +#define XREG_CPSR_THUMB_MODE 0x20U +#define XREG_CPSR_MODE_BITS 0x1FU +#define XREG_CPSR_SYSTEM_MODE 0x1FU +#define XREG_CPSR_UNDEFINED_MODE 0x1BU +#define XREG_CPSR_DATA_ABORT_MODE 0x17U +#define XREG_CPSR_SVC_MODE 0x13U +#define XREG_CPSR_IRQ_MODE 0x12U +#define XREG_CPSR_FIQ_MODE 0x11U +#define XREG_CPSR_USER_MODE 0x10U -#define XREG_CPSR_IRQ_ENABLE 0x80U -#define XREG_CPSR_FIQ_ENABLE 0x40U +#define XREG_CPSR_IRQ_ENABLE 0x80U +#define XREG_CPSR_FIQ_ENABLE 0x40U -#define XREG_CPSR_N_BIT 0x80000000U -#define XREG_CPSR_Z_BIT 0x40000000U -#define XREG_CPSR_C_BIT 0x20000000U -#define XREG_CPSR_V_BIT 0x10000000U +#define XREG_CPSR_N_BIT 0x80000000U +#define XREG_CPSR_Z_BIT 0x40000000U +#define XREG_CPSR_C_BIT 0x20000000U +#define XREG_CPSR_V_BIT 0x10000000U /*MPU region definitions*/ #define REGION_32B 0x00000004U @@ -138,99 +138,99 @@ extern "C" { -#define SHAREABLE 0x00000004U /*shareable */ -#define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/ +#define SHAREABLE 0x00000004U /*shareable */ +#define STRONG_ORDERD_SHARED 0x00000000U /*strongly ordered, always shareable*/ -#define DEVICE_SHARED 0x00000001U /*device, shareable*/ -#define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/ +#define DEVICE_SHARED 0x00000001U /*device, shareable*/ +#define DEVICE_NONSHARED 0x00000010U /*device, non shareable*/ -#define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/ -#define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/ +#define NORM_NSHARED_WT_NWA 0x00000002U /*Outer and Inner write-through, no write-allocate non-shareable*/ +#define NORM_SHARED_WT_NWA 0x00000006U /*Outer and Inner write-through, no write-allocate shareable*/ -#define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/ -#define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/ +#define NORM_NSHARED_WB_NWA 0x00000003U /*Outer and Inner write-back, no write-allocate non shareable*/ +#define NORM_SHARED_WB_NWA 0x00000007U /*Outer and Inner write-back, no write-allocate shareable*/ -#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/ -#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/ +#define NORM_NSHARED_NCACHE 0x00000008U /*Outer and Inner Non cacheable non shareable*/ +#define NORM_SHARED_NCACHE 0x0000000CU /*Outer and Inner Non cacheable shareable*/ -#define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/ -#define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/ +#define NORM_NSHARED_WB_WA 0x0000000BU /*Outer and Inner write-back non shared*/ +#define NORM_SHARED_WB_WA 0x0000000FU /*Outer and Inner write-back shared*/ /* inner and outer cache policies can be combined for different combinations */ -#define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/ -#define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/ -#define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/ -#define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/ +#define NORM_IN_POLICY_NCACHE 0x00000020U /*inner non cacheable*/ +#define NORM_IN_POLICY_WB_WA 0x00000021U /*inner write back write allocate*/ +#define NORM_IN_POLICY_WT_NWA 0x00000022U /*inner write through no write allocate*/ +#define NORM_IN_POLICY_WB_NWA 0x00000023U /*inner write back no write allocate*/ -#define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/ -#define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/ -#define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/ -#define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/ +#define NORM_OUT_POLICY_NCACHE 0x00000020U /*outer non cacheable*/ +#define NORM_OUT_POLICY_WB_WA 0x00000028U /*outer write back write allocate*/ +#define NORM_OUT_POLICY_WT_NWA 0x00000030U /*outer write through no write allocate*/ +#define NORM_OUT_POLICY_WB_NWA 0x00000038U /*outer write back no write allocate*/ -#define NO_ACCESS (0x00000000U<<8U) /*No access*/ -#define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/ -#define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/ -#define PRIV_RW_USER_RW (0x00000003U<<8U) /*Full Access*/ -#define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/ -#define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/ +#define NO_ACCESS (0x00000000U<<8U) /*No access*/ +#define PRIV_RW_USER_NA (0x00000001U<<8U) /*Privileged access only*/ +#define PRIV_RW_USER_RO (0x00000002U<<8U) /*Writes in User mode generate permission faults*/ +#define PRIV_RW_USER_RW (0x00000003U<<8U) /*Full Access*/ +#define PRIV_RO_USER_NA (0x00000005U<<8U) /*Privileged eead only*/ +#define PRIV_RO_USER_RO (0x00000006U<<8U) /*Privileged/User read-only*/ -#define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/ +#define EXECUTE_NEVER (0x00000001U<<12U) /* Bit 12*/ /* CP15 defines */ /* C0 Register defines */ -#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" -#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" -#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" -#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" -#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4" -#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" +#define XREG_CP15_MAIN_ID "p15, 0, %0, c0, c0, 0" +#define XREG_CP15_CACHE_TYPE "p15, 0, %0, c0, c0, 1" +#define XREG_CP15_TCM_TYPE "p15, 0, %0, c0, c0, 2" +#define XREG_CP15_TLB_TYPE "p15, 0, %0, c0, c0, 3" +#define XREG_CP15_MPU_TYPE "p15, 0, %0, c0, c0, 4" +#define XREG_CP15_MULTI_PROC_AFFINITY "p15, 0, %0, c0, c0, 5" -#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" -#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" -#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" -#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" -#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" -#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" -#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" +#define XREG_CP15_PROC_FEATURE_0 "p15, 0, %0, c0, c1, 0" +#define XREG_CP15_PROC_FEATURE_1 "p15, 0, %0, c0, c1, 1" +#define XREG_CP15_DEBUG_FEATURE_0 "p15, 0, %0, c0, c1, 2" +#define XREG_CP15_MEMORY_FEATURE_0 "p15, 0, %0, c0, c1, 4" +#define XREG_CP15_MEMORY_FEATURE_1 "p15, 0, %0, c0, c1, 5" +#define XREG_CP15_MEMORY_FEATURE_2 "p15, 0, %0, c0, c1, 6" +#define XREG_CP15_MEMORY_FEATURE_3 "p15, 0, %0, c0, c1, 7" -#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" -#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" -#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" -#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" -#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" -#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5" +#define XREG_CP15_INST_FEATURE_0 "p15, 0, %0, c0, c2, 0" +#define XREG_CP15_INST_FEATURE_1 "p15, 0, %0, c0, c2, 1" +#define XREG_CP15_INST_FEATURE_2 "p15, 0, %0, c0, c2, 2" +#define XREG_CP15_INST_FEATURE_3 "p15, 0, %0, c0, c2, 3" +#define XREG_CP15_INST_FEATURE_4 "p15, 0, %0, c0, c2, 4" +#define XREG_CP15_INST_FEATURE_5 "p15, 0, %0, c0, c2, 5" -#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" -#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" -#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" +#define XREG_CP15_CACHE_SIZE_ID "p15, 1, %0, c0, c0, 0" +#define XREG_CP15_CACHE_LEVEL_ID "p15, 1, %0, c0, c0, 1" +#define XREG_CP15_AUXILARY_ID "p15, 1, %0, c0, c0, 7" -#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" +#define XREG_CP15_CACHE_SIZE_SEL "p15, 2, %0, c0, c0, 0" /* C1 Register Defines */ -#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" -#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" -#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" +#define XREG_CP15_SYS_CONTROL "p15, 0, %0, c1, c0, 0" +#define XREG_CP15_AUX_CONTROL "p15, 0, %0, c1, c0, 1" +#define XREG_CP15_CP_ACCESS_CONTROL "p15, 0, %0, c1, c0, 2" /* XREG_CP15_CONTROL bit defines */ -#define XREG_CP15_CONTROL_TE_BIT 0x40000000U -#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U -#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U -#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U -#define XREG_CP15_CONTROL_EE_BIT 0x02000000U -#define XREG_CP15_CONTROL_HA_BIT 0x00020000U -#define XREG_CP15_CONTROL_RR_BIT 0x00004000U -#define XREG_CP15_CONTROL_V_BIT 0x00002000U -#define XREG_CP15_CONTROL_I_BIT 0x00001000U -#define XREG_CP15_CONTROL_Z_BIT 0x00000800U -#define XREG_CP15_CONTROL_SW_BIT 0x00000400U -#define XREG_CP15_CONTROL_B_BIT 0x00000080U -#define XREG_CP15_CONTROL_C_BIT 0x00000004U -#define XREG_CP15_CONTROL_A_BIT 0x00000002U -#define XREG_CP15_CONTROL_M_BIT 0x00000001U +#define XREG_CP15_CONTROL_TE_BIT 0x40000000U +#define XREG_CP15_CONTROL_AFE_BIT 0x20000000U +#define XREG_CP15_CONTROL_TRE_BIT 0x10000000U +#define XREG_CP15_CONTROL_NMFI_BIT 0x08000000U +#define XREG_CP15_CONTROL_EE_BIT 0x02000000U +#define XREG_CP15_CONTROL_HA_BIT 0x00020000U +#define XREG_CP15_CONTROL_RR_BIT 0x00004000U +#define XREG_CP15_CONTROL_V_BIT 0x00002000U +#define XREG_CP15_CONTROL_I_BIT 0x00001000U +#define XREG_CP15_CONTROL_Z_BIT 0x00000800U +#define XREG_CP15_CONTROL_SW_BIT 0x00000400U +#define XREG_CP15_CONTROL_B_BIT 0x00000080U +#define XREG_CP15_CONTROL_C_BIT 0x00000004U +#define XREG_CP15_CONTROL_A_BIT 0x00000002U +#define XREG_CP15_CONTROL_M_BIT 0x00000001U /* C2 Register Defines */ /* Not Used */ @@ -241,55 +241,55 @@ extern "C" { /* Not Used */ /* C5 Register Defines */ -#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" -#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" +#define XREG_CP15_DATA_FAULT_STATUS "p15, 0, %0, c5, c0, 0" +#define XREG_CP15_INST_FAULT_STATUS "p15, 0, %0, c5, c0, 1" -#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" -#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" +#define XREG_CP15_AUX_DATA_FAULT_STATUS "p15, 0, %0, c5, c1, 0" +#define XREG_CP15_AUX_INST_FAULT_STATUS "p15, 0, %0, c5, c1, 1" /* C6 Register Defines */ -#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" -#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" +#define XREG_CP15_DATA_FAULT_ADDRESS "p15, 0, %0, c6, c0, 0" +#define XREG_CP15_INST_FAULT_ADDRESS "p15, 0, %0, c6, c0, 2" -#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0" -#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2" -#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4" +#define XREG_CP15_MPU_REG_BASEADDR "p15, 0, %0, c6, c1, 0" +#define XREG_CP15_MPU_REG_SIZE_EN "p15, 0, %0, c6, c1, 2" +#define XREG_CP15_MPU_REG_ACCESS_CTRL "p15, 0, %0, c6, c1, 4" -#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0" +#define XREG_CP15_MPU_MEMORY_REG_NUMBER "p15, 0, %0, c6, c2, 0" /* C7 Register Defines */ -#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" +#define XREG_CP15_NOP "p15, 0, %0, c7, c0, 4" -#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" -#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" +#define XREG_CP15_INVAL_IC_POU "p15, 0, %0, c7, c5, 0" +#define XREG_CP15_INVAL_IC_LINE_MVA_POU "p15, 0, %0, c7, c5, 1" /* The CP15 register access below has been deprecated in favor of the new * isb instruction in Cortex R5. */ -#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" -#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" -#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7" +#define XREG_CP15_INST_SYNC_BARRIER "p15, 0, %0, c7, c5, 4" +#define XREG_CP15_INVAL_BRANCH_ARRAY "p15, 0, %0, c7, c5, 6" +#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE "p15, 0, %0, c7, c5, 7" -#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" -#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" +#define XREG_CP15_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c6, 1" +#define XREG_CP15_INVAL_DC_LINE_SW "p15, 0, %0, c7, c6, 2" -#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" -#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" +#define XREG_CP15_CLEAN_DC_LINE_MVA_POC "p15, 0, %0, c7, c10, 1" +#define XREG_CP15_CLEAN_DC_LINE_SW "p15, 0, %0, c7, c10, 2" -#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0" +#define XREG_CP15_INVAL_DC_ALL "p15, 0, %0, c15, c5, 0" /* The next two CP15 register accesses below have been deprecated in favor * of the new dsb and dmb instructions in Cortex R5. */ -#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" -#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" +#define XREG_CP15_DATA_SYNC_BARRIER "p15, 0, %0, c7, c10, 4" +#define XREG_CP15_DATA_MEMORY_BARRIER "p15, 0, %0, c7, c10, 5" -#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" +#define XREG_CP15_CLEAN_DC_LINE_MVA_POU "p15, 0, %0, c7, c11, 1" -#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" +#define XREG_CP15_NOP2 "p15, 0, %0, c7, c13, 1" -#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" -#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC "p15, 0, %0, c7, c14, 1" +#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW "p15, 0, %0, c7, c14, 2" /* C8 Register Defines */ /* Not Used */ @@ -297,24 +297,24 @@ extern "C" { /* C9 Register Defines */ -#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1" -#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0" -#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0" +#define XREG_CP15_ATCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 1" +#define XREG_CP15_BTCM_REG_SIZE_ADDR "p15, 0, %0, c9, c1, 0" +#define XREG_CP15_TCM_SELECTION "p15, 0, %0, c9, c2, 0" -#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" -#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" -#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" -#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" -#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" -#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" +#define XREG_CP15_PERF_MONITOR_CTRL "p15, 0, %0, c9, c12, 0" +#define XREG_CP15_COUNT_ENABLE_SET "p15, 0, %0, c9, c12, 1" +#define XREG_CP15_COUNT_ENABLE_CLR "p15, 0, %0, c9, c12, 2" +#define XREG_CP15_V_FLAG_STATUS "p15, 0, %0, c9, c12, 3" +#define XREG_CP15_SW_INC "p15, 0, %0, c9, c12, 4" +#define XREG_CP15_EVENT_CNTR_SEL "p15, 0, %0, c9, c12, 5" -#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" -#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" -#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" +#define XREG_CP15_PERF_CYCLE_COUNTER "p15, 0, %0, c9, c13, 0" +#define XREG_CP15_EVENT_TYPE_SEL "p15, 0, %0, c9, c13, 1" +#define XREG_CP15_PERF_MONITOR_COUNT "p15, 0, %0, c9, c13, 2" -#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" -#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" -#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" +#define XREG_CP15_USER_ENABLE "p15, 0, %0, c9, c14, 0" +#define XREG_CP15_INTR_ENABLE_SET "p15, 0, %0, c9, c14, 1" +#define XREG_CP15_INTR_ENABLE_CLR "p15, 0, %0, c9, c14, 2" /* C10 Register Defines */ /* Not used */ @@ -326,90 +326,90 @@ extern "C" { /* Not used */ /* C13 Register Defines */ -#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" -#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" -#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" -#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" +#define XREG_CP15_CONTEXT_ID "p15, 0, %0, c13, c0, 1" +#define USER_RW_THREAD_PID "p15, 0, %0, c13, c0, 2" +#define USER_RO_THREAD_PID "p15, 0, %0, c13, c0, 3" +#define USER_PRIV_THREAD_PID "p15, 0, %0, c13, c0, 4" /* C14 Register Defines */ /* not used */ /* C15 Register Defines */ -#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0" +#define XREG_CP15_SEC_AUX_CTRL "p15, 0, %0, c15, c0, 0" /* MPE register definitions */ -#define XREG_FPSID c0 -#define XREG_FPSCR c1 -#define XREG_MVFR1 c6 -#define XREG_MVFR0 c7 -#define XREG_FPEXC c8 -#define XREG_FPINST c9 -#define XREG_FPINST2 c10 +#define XREG_FPSID c0 +#define XREG_FPSCR c1 +#define XREG_MVFR1 c6 +#define XREG_MVFR0 c7 +#define XREG_FPEXC c8 +#define XREG_FPINST c9 +#define XREG_FPINST2 c10 /* FPSID bits */ -#define XREG_FPSID_IMPLEMENTER_BIT (24U) -#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) -#define XREG_FPSID_SOFTWARE (0X00000001U << 23U) -#define XREG_FPSID_ARCH_BIT (16U) -#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) -#define XREG_FPSID_PART_BIT (8U) -#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) -#define XREG_FPSID_VARIANT_BIT (4U) -#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) -#define XREG_FPSID_REV_BIT (0U) -#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) +#define XREG_FPSID_IMPLEMENTER_BIT (24U) +#define XREG_FPSID_IMPLEMENTER_MASK (0x000000FFU << FPSID_IMPLEMENTER_BIT) +#define XREG_FPSID_SOFTWARE (0X00000001U << 23U) +#define XREG_FPSID_ARCH_BIT (16U) +#define XREG_FPSID_ARCH_MASK (0x0000000FU << FPSID_ARCH_BIT) +#define XREG_FPSID_PART_BIT (8U) +#define XREG_FPSID_PART_MASK (0x000000FFU << FPSID_PART_BIT) +#define XREG_FPSID_VARIANT_BIT (4U) +#define XREG_FPSID_VARIANT_MASK (0x0000000FU << FPSID_VARIANT_BIT) +#define XREG_FPSID_REV_BIT (0U) +#define XREG_FPSID_REV_MASK (0x0000000FU << FPSID_REV_BIT) /* FPSCR bits */ -#define XREG_FPSCR_N_BIT (0X00000001U << 31U) -#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) -#define XREG_FPSCR_C_BIT (0X00000001U << 29U) -#define XREG_FPSCR_V_BIT (0X00000001U << 28U) -#define XREG_FPSCR_QC (0X00000001U << 27U) -#define XREG_FPSCR_AHP (0X00000001U << 26U) -#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) -#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) -#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) -#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) -#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) -#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) -#define XREG_FPSCR_RMODE_BIT (22U) -#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) -#define XREG_FPSCR_STRIDE_BIT (20U) -#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) -#define XREG_FPSCR_LENGTH_BIT (16U) -#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) -#define XREG_FPSCR_IDC (0X00000001U << 7U) -#define XREG_FPSCR_IXC (0X00000001U << 4U) -#define XREG_FPSCR_UFC (0X00000001U << 3U) -#define XREG_FPSCR_OFC (0X00000001U << 2U) -#define XREG_FPSCR_DZC (0X00000001U << 1U) -#define XREG_FPSCR_IOC (0X00000001U << 0U) +#define XREG_FPSCR_N_BIT (0X00000001U << 31U) +#define XREG_FPSCR_Z_BIT (0X00000001U << 30U) +#define XREG_FPSCR_C_BIT (0X00000001U << 29U) +#define XREG_FPSCR_V_BIT (0X00000001U << 28U) +#define XREG_FPSCR_QC (0X00000001U << 27U) +#define XREG_FPSCR_AHP (0X00000001U << 26U) +#define XREG_FPSCR_DEFAULT_NAN (0X00000001U << 25U) +#define XREG_FPSCR_FLUSHTOZERO (0X00000001U << 24U) +#define XREG_FPSCR_ROUND_NEAREST (0X00000000U << 22U) +#define XREG_FPSCR_ROUND_PLUSINF (0X00000001U << 22U) +#define XREG_FPSCR_ROUND_MINUSINF (0X00000002U << 22U) +#define XREG_FPSCR_ROUND_TOZERO (0X00000003U << 22U) +#define XREG_FPSCR_RMODE_BIT (22U) +#define XREG_FPSCR_RMODE_MASK (0X00000003U << FPSCR_RMODE_BIT) +#define XREG_FPSCR_STRIDE_BIT (20U) +#define XREG_FPSCR_STRIDE_MASK (0X00000003U << FPSCR_STRIDE_BIT) +#define XREG_FPSCR_LENGTH_BIT (16U) +#define XREG_FPSCR_LENGTH_MASK (0X00000007U << FPSCR_LENGTH_BIT) +#define XREG_FPSCR_IDC (0X00000001U << 7U) +#define XREG_FPSCR_IXC (0X00000001U << 4U) +#define XREG_FPSCR_UFC (0X00000001U << 3U) +#define XREG_FPSCR_OFC (0X00000001U << 2U) +#define XREG_FPSCR_DZC (0X00000001U << 1U) +#define XREG_FPSCR_IOC (0X00000001U << 0U) /* MVFR0 bits */ -#define XREG_MVFR0_RMODE_BIT (28U) -#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) -#define XREG_MVFR0_SHORT_VEC_BIT (24U) -#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) -#define XREG_MVFR0_SQRT_BIT (20U) -#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) -#define XREG_MVFR0_DIVIDE_BIT (16U) -#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) -#define XREG_MVFR0_EXEC_TRAP_BIT (12U) -#define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) -#define XREG_MVFR0_DP_BIT (8U) -#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) -#define XREG_MVFR0_SP_BIT (4U) -#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) -#define XREG_MVFR0_A_SIMD_BIT (0U) -#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) +#define XREG_MVFR0_RMODE_BIT (28U) +#define XREG_MVFR0_RMODE_MASK (0x0000000FU << XREG_MVFR0_RMODE_BIT) +#define XREG_MVFR0_SHORT_VEC_BIT (24U) +#define XREG_MVFR0_SHORT_VEC_MASK (0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT) +#define XREG_MVFR0_SQRT_BIT (20U) +#define XREG_MVFR0_SQRT_MASK (0x0000000FU << XREG_MVFR0_SQRT_BIT) +#define XREG_MVFR0_DIVIDE_BIT (16U) +#define XREG_MVFR0_DIVIDE_MASK (0x0000000FU << XREG_MVFR0_DIVIDE_BIT) +#define XREG_MVFR0_EXEC_TRAP_BIT (12U) +#define XREG_MVFR0_EXEC_TRAP_MASK (0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT) +#define XREG_MVFR0_DP_BIT (8U) +#define XREG_MVFR0_DP_MASK (0x0000000FU << XREG_MVFR0_DP_BIT) +#define XREG_MVFR0_SP_BIT (4U) +#define XREG_MVFR0_SP_MASK (0x0000000FU << XREG_MVFR0_SP_BIT) +#define XREG_MVFR0_A_SIMD_BIT (0U) +#define XREG_MVFR0_A_SIMD_MASK (0x0000000FU << MVFR0_A_SIMD_BIT) /* FPEXC bits */ -#define XREG_FPEXC_EX (0X00000001U << 31U) -#define XREG_FPEXC_EN (0X00000001U << 30U) -#define XREG_FPEXC_DEX (0X00000001U << 29U) +#define XREG_FPEXC_EX (0X00000001U << 31U) +#define XREG_FPEXC_EN (0X00000001U << 30U) +#define XREG_FPEXC_DEX (0X00000001U << 29U) #ifdef __cplusplus diff --git a/libcpu/avr32/uc3/cpu.c b/libcpu/avr32/uc3/cpu.c index fdd8a4d56c..1d4ea5adfa 100644 --- a/libcpu/avr32/uc3/cpu.c +++ b/libcpu/avr32/uc3/cpu.c @@ -25,7 +25,7 @@ */ RT_WEAK void rt_hw_cpu_reset() { - /*NOTREACHED*/ + /*NOTREACHED*/ } /** @@ -34,9 +34,9 @@ RT_WEAK void rt_hw_cpu_reset() */ void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - RT_ASSERT(0); + RT_ASSERT(0); } /*@}*/ diff --git a/libcpu/avr32/uc3/serial.c b/libcpu/avr32/uc3/serial.c index 14ef865448..66fb6ca8b9 100644 --- a/libcpu/avr32/uc3/serial.c +++ b/libcpu/avr32/uc3/serial.c @@ -24,8 +24,8 @@ struct rt_device _rt_usart_device; struct avr32_serial_int_rx _rt_usart_rx; struct avr32_serial_device uart = { - .uart_device = (avr32_usart_t *) &AVR32_USART1, - .int_rx = &_rt_usart_rx + .uart_device = (avr32_usart_t *) &AVR32_USART1, + .int_rx = &_rt_usart_rx }; /** @@ -36,163 +36,163 @@ struct avr32_serial_device uart = /* RT-Thread Device Interface */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct avr32_serial_device* uart = (struct avr32_serial_device*) dev->user_data; + struct avr32_serial_device* uart = (struct avr32_serial_device*) dev->user_data; - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = 0; - uart->int_rx->save_index = 0; - } + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = 0; + uart->int_rx->save_index = 0; + } - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct avr32_serial_device* uart; + rt_uint8_t* ptr; + rt_err_t err_code; + struct avr32_serial_device* uart; - ptr = buffer; - err_code = RT_EOK; - uart = (struct avr32_serial_device*)dev->user_data; + ptr = buffer; + err_code = RT_EOK; + uart = (struct avr32_serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* interrupt mode Rx */ - while (size) - { - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* interrupt mode Rx */ + while (size) + { + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - /* read a character */ - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size--; + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + /* read a character */ + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size--; - /* move to next position */ - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; + /* move to next position */ + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (usart_test_hit(uart->uart_device)) - { - *ptr = uart->uart_device->rhr & 0xff; - ptr ++; - } - } - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (usart_test_hit(uart->uart_device)) + { + *ptr = uart->uart_device->rhr & 0xff; + ptr ++; + } + } + } - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct avr32_serial_device* uart; + rt_uint8_t* ptr; + rt_err_t err_code; + struct avr32_serial_device* uart; - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct avr32_serial_device*)dev->user_data; + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct avr32_serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx, does not support */ - RT_ASSERT(0); - } - else - { - /* polling mode */ - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - usart_putchar(uart->uart_device, (int) *ptr); + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx, does not support */ + RT_ASSERT(0); + } + else + { + /* polling mode */ + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + usart_putchar(uart->uart_device, (int) *ptr); - ++ptr; --size; - } - } - else - { - /* write data directly */ - while (size) - { - usart_bw_write_char(uart->uart_device, (int) *ptr); + ++ptr; --size; + } + } + else + { + /* write data directly */ + while (size) + { + usart_bw_write_char(uart->uart_device, (int) *ptr); - ++ptr; --size; - } - } - } + ++ptr; --size; + } + } + } - /* set error code */ - rt_set_errno(err_code); + /* set error code */ + rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - struct avr32_serial_device* uart; + struct avr32_serial_device* uart; - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - uart = (struct avr32_serial_device*)dev->user_data; - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; + uart = (struct avr32_serial_device*)dev->user_data; + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } - return RT_EOK; + return RT_EOK; } /* @@ -201,77 +201,77 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - if ((flag & RT_DEVICE_FLAG_DMA_RX) || - (flag & RT_DEVICE_FLAG_INT_TX)) - { - RT_ASSERT(0); - } + if ((flag & RT_DEVICE_FLAG_DMA_RX) || + (flag & RT_DEVICE_FLAG_INT_TX)) + { + RT_ASSERT(0); + } - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } /* ISR for serial interrupt */ void rt_hw_serial_isr(void) { - struct avr32_serial_device* uart = (struct avr32_serial_device*) _rt_usart_device.user_data; - rt_base_t level; + struct avr32_serial_device* uart = (struct avr32_serial_device*) _rt_usart_device.user_data; + rt_base_t level; - if (usart_test_hit(uart->uart_device)) - { - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + if (usart_test_hit(uart->uart_device)) + { + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* save character */ - uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->rhr & 0xff; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; + /* save character */ + uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->rhr & 0xff; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - /* invoke callback */ - if (_rt_usart_device.rx_indicate != RT_NULL) - { - rt_size_t rx_length; + /* invoke callback */ + if (_rt_usart_device.rx_indicate != RT_NULL) + { + rt_size_t rx_length; - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; - _rt_usart_device.rx_indicate(&_rt_usart_device, rx_length); - } - } - else - { - usart_reset_status(uart->uart_device); - } + _rt_usart_device.rx_indicate(&_rt_usart_device, rx_length); + } + } + else + { + usart_reset_status(uart->uart_device); + } } /*@}*/ diff --git a/libcpu/avr32/uc3/serial.h b/libcpu/avr32/uc3/serial.h index a17338701b..fef65a12be 100644 --- a/libcpu/avr32/uc3/serial.h +++ b/libcpu/avr32/uc3/serial.h @@ -21,29 +21,29 @@ #include "compiler.h" #include "usart.h" -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_DMA_NODE_SIZE 4 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_DMA_NODE_SIZE 4 /* data node for Tx Mode */ struct avr32_serial_data_node { - rt_uint8_t *data_ptr; - rt_size_t data_size; - struct avr32_serial_data_node *next, *prev; + rt_uint8_t *data_ptr; + rt_size_t data_size; + struct avr32_serial_data_node *next, *prev; }; struct avr32_serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct avr32_serial_device { - avr32_usart_t *uart_device; + avr32_usart_t *uart_device; - /* rx structure */ - struct avr32_serial_int_rx* int_rx; + /* rx structure */ + struct avr32_serial_int_rx* int_rx; }; rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct avr32_serial_device *serial); diff --git a/libcpu/avr32/uc3/stack.c b/libcpu/avr32/uc3/stack.c index dd43b5edbc..dee1161c12 100644 --- a/libcpu/avr32/uc3/stack.c +++ b/libcpu/avr32/uc3/stack.c @@ -30,28 +30,28 @@ */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - *(stk) = 0; /* r8 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r12 */ - *(--stk) = (unsigned long)texit; /* lr */ - *(--stk) = (unsigned long)tentry; /* entry point, pc */ - *(--stk) = 0x00600000; /* sr */ - *(--stk) = 0; /* r0 */ - *(--stk) = 0; /* r1 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r7 */ + stk = (unsigned long *)stack_addr; + *(stk) = 0; /* r8 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r12 */ + *(--stk) = (unsigned long)texit; /* lr */ + *(--stk) = (unsigned long)tentry; /* entry point, pc */ + *(--stk) = 0x00600000; /* sr */ + *(--stk) = 0; /* r0 */ + *(--stk) = 0; /* r1 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r7 */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/libcpu/blackfin/bf53x/cpuport.c b/libcpu/blackfin/bf53x/cpuport.c index 91cfaeb403..2d69ccc99a 100644 --- a/libcpu/blackfin/bf53x/cpuport.c +++ b/libcpu/blackfin/bf53x/cpuport.c @@ -8,8 +8,8 @@ * http://www.rt-thread.org/license/LICENSE * * Change Logs: - * Date Author Notes - * 2012-02-13 mojingxian first version + * Date Author Notes + * 2012-02-13 mojingxian first version */ #include <rtthread.h> @@ -23,10 +23,10 @@ rt_uint32_t rt_thread_switch_interrupt_flag; * initializes stack of thread */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { unsigned char i; - unsigned long *stk; + unsigned long *stk; stk = (unsigned long *)stack_addr; /* Load stack pointer */ diff --git a/libcpu/blackfin/bf53x/serial.c b/libcpu/blackfin/bf53x/serial.c index b8a4c52570..4a6484a647 100644 --- a/libcpu/blackfin/bf53x/serial.c +++ b/libcpu/blackfin/bf53x/serial.c @@ -29,206 +29,206 @@ */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct serial_device* uart = (struct serial_device*) dev->user_data; + struct serial_device* uart = (struct serial_device*) dev->user_data; - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } - - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } - return RT_EOK; + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } + + return RT_EOK; } /* save a char to serial buffer */ static void rt_serial_savechar(struct serial_device* uart, char ch) { - rt_base_t level; - - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + rt_base_t level; + + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) -{ - RT_ASSERT(dev != RT_NULL); - - return RT_EOK; +{ + RT_ASSERT(dev != RT_NULL); + + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) -{ - RT_ASSERT(dev != RT_NULL); +{ + RT_ASSERT(dev != RT_NULL); - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - //while (uart->uart_device->ustat & USTAT_RCV_READY) - { - *ptr = uart->uart_device->rbr_thr & 0xff; - ptr ++; - } - } - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + //while (uart->uart_device->ustat & USTAT_RCV_READY) + { + *ptr = uart->uart_device->rbr_thr & 0xff; + ptr ++; + } + } + } - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; - - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; + + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - - -- size; + -- size; - /* move to next position */ - uart->int_tx->save_index ++; - - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } - - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->lsr & 0x20)); - uart->uart_device->rbr_thr = '\r'; - } + /* move to next position */ + uart->int_tx->save_index ++; - while (!(uart->uart_device->lsr & 0x20)); - uart->uart_device->rbr_thr = (*ptr & 0xFF); + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } - ++ptr; --size; - } - } + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->lsr & 0x20)); + uart->uart_device->rbr_thr = '\r'; + } - /* set error code */ - rt_set_errno(err_code); - - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + while (!(uart->uart_device->lsr & 0x20)); + uart->uart_device->rbr_thr = (*ptr & 0xFF); + + ++ptr; --size; + } + } + + /* set error code */ + rt_set_errno(err_code); + + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); + + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; - - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } - - return RT_EOK; + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } + + return RT_EOK; } /* @@ -236,49 +236,49 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } - + /* ISR for serial interrupt */ void rt_hw_serial_isr(rt_device_t device) { - struct serial_device* uart = (struct serial_device*) device->user_data; - - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + struct serial_device* uart = (struct serial_device*) device->user_data; + + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + + /* save on rx buffer */ + //while (uart->uart_device->ustat & USTAT_RCV_READY) + { + rt_serial_savechar(uart, uart->uart_device->rbr_thr & 0xff); + } - /* save on rx buffer */ - //while (uart->uart_device->ustat & USTAT_RCV_READY) - { - rt_serial_savechar(uart, uart->uart_device->rbr_thr & 0xff); - } + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; - - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; - device->rx_indicate(device, rx_length); - } + device->rx_indicate(device, rx_length); + } } /*@}*/ diff --git a/libcpu/blackfin/bf53x/serial.h b/libcpu/blackfin/bf53x/serial.h index 8d85193634..7969c5514e 100644 --- a/libcpu/blackfin/bf53x/serial.h +++ b/libcpu/blackfin/bf53x/serial.h @@ -4,49 +4,49 @@ #include <rthw.h> #include <rtthread.h> -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ -#define BPS 115200 /* serial baudrate */ +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_TXB_EMPTY 0x02 /* tx buffer empty */ +#define BPS 115200 /* serial baudrate */ -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 struct serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct serial_int_tx { - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; }; typedef struct uartport { - volatile rt_uint16_t rbr_thr; //receive buffer register and transmit hold register - volatile rt_uint16_t reserved0; - volatile rt_uint16_t reserved1; - volatile rt_uint16_t reserved2; - volatile rt_uint16_t reserved3; - volatile rt_uint16_t reserved4; - volatile rt_uint16_t reserved5; - volatile rt_uint16_t reserved6; - volatile rt_uint16_t reserved7; - volatile rt_uint16_t reserved8; - volatile rt_uint16_t lsr; //line status register + volatile rt_uint16_t rbr_thr; //receive buffer register and transmit hold register + volatile rt_uint16_t reserved0; + volatile rt_uint16_t reserved1; + volatile rt_uint16_t reserved2; + volatile rt_uint16_t reserved3; + volatile rt_uint16_t reserved4; + volatile rt_uint16_t reserved5; + volatile rt_uint16_t reserved6; + volatile rt_uint16_t reserved7; + volatile rt_uint16_t reserved8; + volatile rt_uint16_t lsr; //line status register }uartport; struct serial_device { - uartport* uart_device; - - /* rx structure */ - struct serial_int_rx* int_rx; + uartport* uart_device; - /* tx structure */ - struct serial_int_tx* int_tx; + /* rx structure */ + struct serial_int_rx* int_rx; + + /* tx structure */ + struct serial_int_tx* int_tx; }; rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); diff --git a/libcpu/c-sky/ck802/contex_ck802_gcc.S b/libcpu/c-sky/ck802/contex_ck802_gcc.S index 44f2c331dd..a4431b0f74 100644 --- a/libcpu/c-sky/ck802/contex_ck802_gcc.S +++ b/libcpu/c-sky/ck802/contex_ck802_gcc.S @@ -1,21 +1,7 @@ /* - * File : contex_ck802.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/libcpu/c-sky/ck802/core_ck802.c b/libcpu/c-sky/ck802/core_ck802.c index 047c417267..d8cfce09f7 100644 --- a/libcpu/c-sky/ck802/core_ck802.c +++ b/libcpu/c-sky/ck802/core_ck802.c @@ -1,21 +1,7 @@ /* - * File : core_ck802.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/libcpu/c-sky/ck802/core_ck802.h b/libcpu/c-sky/ck802/core_ck802.h index 6c335f8178..e7185131e4 100644 --- a/libcpu/c-sky/ck802/core_ck802.h +++ b/libcpu/c-sky/ck802/core_ck802.h @@ -1,21 +1,7 @@ /* - * File : core_ck802.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -147,24 +133,24 @@ extern "C" { */ /** - \brief ���ʴ�����״̬�Ĵ���(PSR)�������嶨��. + \brief 访问处理器状态寄存器(PSR)的联合体定义. */ typedef union { struct { - uint32_t C: 1; /*!< bit: 0 �����룯��λλ */ - uint32_t _reserved0: 5; /*!< bit: 2.. 5 ���� */ - uint32_t IE: 1; /*!< bit: 6 �ж���Ч����λ */ - uint32_t IC: 1; /*!< bit: 7 �жϿ���λ */ - uint32_t EE: 1; /*!< bit: 8 �쳣��Ч����λ */ - uint32_t MM: 1; /*!< bit: 9 �������쳣�ڸ�λ */ - uint32_t _reserved1: 6; /*!< bit: 10..15 ���� */ - uint32_t VEC: 8; /*!< bit: 16..23 �쳣�¼�����ֵ */ - uint32_t _reserved2: 7; /*!< bit: 24..30 ���� */ - uint32_t S: 1; /*!< bit: 31 �����û�ģʽ����λ */ - } b; /*!< Structure ������λ���� */ - uint32_t w; /*!< Type �����Ĵ������� */ + uint32_t C: 1; /*!< bit: 0 条件码／进位位 */ + uint32_t _reserved0: 5; /*!< bit: 2.. 5 保留 */ + uint32_t IE: 1; /*!< bit: 6 中断有效控制位 */ + uint32_t IC: 1; /*!< bit: 7 中断控制位 */ + uint32_t EE: 1; /*!< bit: 8 异常有效控制位 */ + uint32_t MM: 1; /*!< bit: 9 不对齐异常掩盖位 */ + uint32_t _reserved1: 6; /*!< bit: 10..15 保留 */ + uint32_t VEC: 8; /*!< bit: 16..23 异常事件向量值 */ + uint32_t _reserved2: 7; /*!< bit: 24..30 保留 */ + uint32_t S: 1; /*!< bit: 31 超级用户模式设置位 */ + } b; /*!< Structure 用来按位访问 */ + uint32_t w; /*!< Type 整个寄存器访问 */ } PSR_Type; /* PSR Register Definitions */ @@ -190,21 +176,21 @@ typedef union #define PSR_C_Msk (1UL << PSR_C_Pos) /*!< PSR: C Mask */ /** - \brief ���ʸ��ٻ������üĴ���(CCR, CR<18, 0>)�������嶨��. + \brief 访问高速缓存配置寄存器(CCR, CR<18, 0>)的联合体定义. */ typedef union { struct { - uint32_t MP: 1; /*!< bit: 0 �ڴ汣������λ */ - uint32_t _reserved0: 6; /*!< bit: 1.. 6 ���� */ - uint32_t BE: 1; /*!< bit: 7 Endianģʽ */ - uint32_t SCK: 3; /*!< bit: 8..10 ϵͳ�ʹ�������ʱ�ӱ� */ - uint32_t _reserved1: 2; /*!< bit: 11..12 ���� */ - uint32_t BE_V2: 1; /*!< bit: 13 V2�汾��С�� */ - uint32_t _reserved2: 18; /*!< bit: 14..31 ���� */ - } b; /*!< Structure ������λ���� */ - uint32_t w; /*!< Type �����Ĵ������� */ + uint32_t MP: 1; /*!< bit: 0 内存保护设置位 */ + uint32_t _reserved0: 6; /*!< bit: 1.. 6 保留 */ + uint32_t BE: 1; /*!< bit: 7 Endian模式 */ + uint32_t SCK: 3; /*!< bit: 8..10 系统和处理器的时钟比 */ + uint32_t _reserved1: 2; /*!< bit: 11..12 保留 */ + uint32_t BE_V2: 1; /*!< bit: 13 V2版本大小端 */ + uint32_t _reserved2: 18; /*!< bit: 14..31 保留 */ + } b; /*!< Structure 用来按位访问 */ + uint32_t w; /*!< Type 整个寄存器访问 */ } CCR_Type; /* CCR Register Definitions */ @@ -221,38 +207,38 @@ typedef union #define CCR_MP_Msk (0x1UL << CCR_MP_Pos) /*!< CCR: MP Mask */ /** - \brief ���ʿɸ��ͷ���Ȩ�����üĴ���(CAPR, CR<19,0>)�������嶨��.. + \brief 访问可高缓和访问权限配置寄存器(CAPR, CR<19,0>)的联合体定义.. */ typedef union { struct { - uint32_t X0: 1; /*!< bit: 0 ����ִ����������λ */ - uint32_t X1: 1; /*!< bit: 1 ����ִ����������λ */ - uint32_t X2: 1; /*!< bit: 2 ����ִ����������λ */ - uint32_t X3: 1; /*!< bit: 3 ����ִ����������λ */ - uint32_t X4: 1; /*!< bit: 4 ����ִ����������λ */ - uint32_t X5: 1; /*!< bit: 5 ����ִ����������λ */ - uint32_t X6: 1; /*!< bit: 6 ����ִ����������λ */ - uint32_t X7: 1; /*!< bit: 7 ����ִ����������λ */ - uint32_t AP0: 2; /*!< bit: 8.. 9 ����Ȩ������λ */ - uint32_t AP1: 2; /*!< bit: 10..11 ����Ȩ������λ */ - uint32_t AP2: 2; /*!< bit: 12..13 ����Ȩ������λ */ - uint32_t AP3: 2; /*!< bit: 14..15 ����Ȩ������λ */ - uint32_t AP4: 2; /*!< bit: 16..17 ����Ȩ������λ */ - uint32_t AP5: 2; /*!< bit: 18..19 ����Ȩ������λ */ - uint32_t AP6: 2; /*!< bit: 20..21 ����Ȩ������λ */ - uint32_t AP7: 2; /*!< bit: 22..23 ����Ȩ������λ */ - uint32_t S0: 1; /*!< bit: 24 ��ȫ��������λ */ - uint32_t S1: 1; /*!< bit: 25 ��ȫ��������λ */ - uint32_t S2: 1; /*!< bit: 26 ��ȫ��������λ */ - uint32_t S3: 1; /*!< bit: 27 ��ȫ��������λ */ - uint32_t S4: 1; /*!< bit: 28 ��ȫ��������λ */ - uint32_t S5: 1; /*!< bit: 29 ��ȫ��������λ */ - uint32_t S6: 1; /*!< bit: 30 ��ȫ��������λ */ - uint32_t S7: 1; /*!< bit: 31 ��ȫ��������λ */ - } b; /*!< Structure ������λ���� */ - uint32_t w; /*!< Type �����Ĵ������� */ + uint32_t X0: 1; /*!< bit: 0 不可执行属性设置位 */ + uint32_t X1: 1; /*!< bit: 1 不可执行属性设置位 */ + uint32_t X2: 1; /*!< bit: 2 不可执行属性设置位 */ + uint32_t X3: 1; /*!< bit: 3 不可执行属性设置位 */ + uint32_t X4: 1; /*!< bit: 4 不可执行属性设置位 */ + uint32_t X5: 1; /*!< bit: 5 不可执行属性设置位 */ + uint32_t X6: 1; /*!< bit: 6 不可执行属性设置位 */ + uint32_t X7: 1; /*!< bit: 7 不可执行属性设置位 */ + uint32_t AP0: 2; /*!< bit: 8.. 9 访问权限设置位 */ + uint32_t AP1: 2; /*!< bit: 10..11 访问权限设置位 */ + uint32_t AP2: 2; /*!< bit: 12..13 访问权限设置位 */ + uint32_t AP3: 2; /*!< bit: 14..15 访问权限设置位 */ + uint32_t AP4: 2; /*!< bit: 16..17 访问权限设置位 */ + uint32_t AP5: 2; /*!< bit: 18..19 访问权限设置位 */ + uint32_t AP6: 2; /*!< bit: 20..21 访问权限设置位 */ + uint32_t AP7: 2; /*!< bit: 22..23 访问权限设置位 */ + uint32_t S0: 1; /*!< bit: 24 安全属性设置位 */ + uint32_t S1: 1; /*!< bit: 25 安全属性设置位 */ + uint32_t S2: 1; /*!< bit: 26 安全属性设置位 */ + uint32_t S3: 1; /*!< bit: 27 安全属性设置位 */ + uint32_t S4: 1; /*!< bit: 28 安全属性设置位 */ + uint32_t S5: 1; /*!< bit: 29 安全属性设置位 */ + uint32_t S6: 1; /*!< bit: 30 安全属性设置位 */ + uint32_t S7: 1; /*!< bit: 31 安全属性设置位 */ + } b; /*!< Structure 用来按位访问 */ + uint32_t w; /*!< Type 整个寄存器访问 */ } CAPR_Type; /* CAPR Register Definitions */ @@ -329,18 +315,18 @@ typedef union #define CAPR_X0_Msk (0x1UL << CAPR_X0_Pos) /*!< CAPR: X0 Mask */ /** - \brief ���ʱ��������ƼĴ���(PACR, CR<20,0>)�������嶨��. + \brief 访问保护区控制寄存器(PACR, CR<20,0>)的联合体定义. */ typedef union { struct { - uint32_t E: 1; /*!< bit: 0 ��������Ч���� */ - uint32_t Size: 5; /*!< bit: 1.. 5 ��������С */ - uint32_t _reserved0: 4; /*!< bit: 6.. 9 ���� */ - uint32_t base_addr: 22; /*!< bit: 10..31 ��������ַ�ĸ�λ */ - } b; /*!< Structure ������λ���� */ - uint32_t w; /*!< Type �����Ĵ������� */ + uint32_t E: 1; /*!< bit: 0 保护区有效设置 */ + uint32_t Size: 5; /*!< bit: 1.. 5 保护区大小 */ + uint32_t _reserved0: 4; /*!< bit: 6.. 9 保留 */ + uint32_t base_addr: 22; /*!< bit: 10..31 保护区地址的高位 */ + } b; /*!< Structure 用来按位访问 */ + uint32_t w; /*!< Type 整个寄存器访问 */ } PACR_Type; /* PACR Register Definitions */ @@ -354,16 +340,16 @@ typedef union #define PACK_E_Msk (0x1UL << PACR_E_Pos) /*!< PACR: E Mask */ /** - \brief ���ʱ�����ѡ��Ĵ���(PRSR,CR<21,0>)�������嶨��. + \brief 访问保护区选择寄存器(PRSR,CR<21,0>)的联合体定义. */ typedef union { struct { - uint32_t RID: 3; /*!< bit: 0.. 2 ����������ֵ */ - uint32_t _reserved0: 30; /*!< bit: 3..31 ���� */ - } b; /*!< Structure ������λ���� */ - uint32_t w; /*!< Type �����Ĵ������� */ + uint32_t RID: 3; /*!< bit: 0.. 2 保护区索引值 */ + uint32_t _reserved0: 30; /*!< bit: 3..31 保留 */ + } b; /*!< Structure 用来按位访问 */ + uint32_t w; /*!< Type 整个寄存器访问 */ } PRSR_Type; /* PRSR Register Definitions */ @@ -381,30 +367,30 @@ typedef union */ /** - \brief ����ʸ���жϿ������Ľṹ��. + \brief 访问矢量中断控制器的结构体. */ typedef struct { - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) �ж�ʹ�����üĴ��� */ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) 中断使能设置寄存器 */ uint32_t RESERVED0[15U]; - __IOM uint32_t IWER[1U]; /*!< Offset: 0x040 (R/W) �жϵ��Ļ������üĴ��� */ + __IOM uint32_t IWER[1U]; /*!< Offset: 0x040 (R/W) 中断低功耗唤醒设置寄存器 */ uint32_t RESERVED1[15U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) �ж�ʹ������Ĵ��� */ + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) 中断使能清除寄存器 */ uint32_t RESERVED2[15U]; - __IOM uint32_t IWDR[1U]; /*!< Offset: 0x0c0 (R/W) �жϵ��Ļ�������Ĵ��� */ + __IOM uint32_t IWDR[1U]; /*!< Offset: 0x0c0 (R/W) 中断低功耗唤醒清除寄存器 */ uint32_t RESERVED3[15U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) �жϵȴ����üĴ��� */ + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) 中断等待设置寄存器 */ uint32_t RESERVED4[15U]; - __IOM uint32_t ISSR[1U]; /*!< Offset: 0x140 (R/W) ��ȫ�ж�ʹ�����üĴ��� */ + __IOM uint32_t ISSR[1U]; /*!< Offset: 0x140 (R/W) 安全中断使能设置寄存器 */ uint32_t RESERVED5[15U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) �жϵȴ�����Ĵ��� */ + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) 中断等待清除寄存器 */ uint32_t RESERVED6[31U]; - __IOM uint32_t IABR[1U]; /*!< Offset: 0x200 (R/W) �ж���Ӧ״̬�Ĵ��� */ + __IOM uint32_t IABR[1U]; /*!< Offset: 0x200 (R/W) 中断响应状态寄存器 */ uint32_t RESERVED7[63U]; - __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) �ж����ȼ����üĴ��� */ + __IOM uint32_t IPR[8U]; /*!< Offset: 0x300 (R/W) 中断优先级设置寄存器 */ uint32_t RESERVED8[504U]; - __IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) �ж�״̬�Ĵ��� */ - __IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) �ж����ȼ���ֵ�Ĵ��� */ + __IM uint32_t ISR; /*!< Offset: 0xB00 (R/ ) 中断状态寄存器 */ + __IOM uint32_t IPTR; /*!< Offset: 0xB04 (R/W) 中断优先级阈值寄存器 */ } NVIC_Type; /*@} end of group CSI_NVIC */ @@ -417,14 +403,14 @@ typedef struct */ /** - \brief ����ϵͳ��ʱ�������ݽṹ. + \brief 访问系统计时器的数据结构. */ typedef struct { - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) ����״̬�Ĵ��� */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) ����ֵ�Ĵ��� */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) ��ǰֵ�Ĵ��� */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) У�Ĵ��� */ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) 控制状态寄存器 */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) 回填值寄存器 */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) 当前值寄存器 */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) 校准寄存器 */ } CORET_Type; /* CORET Control / Status Register Definitions */ @@ -468,7 +454,7 @@ typedef struct */ /** - \brief ����DCC�����ݽṹ. + \brief 访问DCC的数据结构. */ typedef struct { @@ -478,8 +464,8 @@ typedef struct uint32_t RESERVED1[6U]; union { - __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) ���ݽ����Ĵ��� CPU��*/ - __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) ���ݽ����Ĵ��� CPUд*/ + __IM uint32_t DERJW; /*!< Offset: 0x058 (R/ ) 数据交换寄存器 CPU读*/ + __OM uint32_t DERJR; /*!< Offset: 0x058 ( /W) 数据交换寄存器 CPU写*/ }; } DCC_Type; diff --git a/libcpu/c-sky/ck802/stack_ck802.c b/libcpu/c-sky/ck802/stack_ck802.c index 01fed9ad34..087722072e 100644 --- a/libcpu/c-sky/ck802/stack_ck802.c +++ b/libcpu/c-sky/ck802/stack_ck802.c @@ -1,21 +1,7 @@ /* - * File : stack_ck802.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2017, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/libcpu/ia32/__udivsi3.c b/libcpu/ia32/__udivsi3.c index ec7c59d1cb..ced90b5aba 100644 --- a/libcpu/ia32/__udivsi3.c +++ b/libcpu/ia32/__udivsi3.c @@ -1,11 +1,7 @@ /* - * File : __udivsi3.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -16,31 +12,31 @@ uint32_t __udivsi3(uint32_t num, uint32_t den) { - uint32_t quot = 0, qbit = 1; + uint32_t quot = 0, qbit = 1; - if (den == 0) - { - asm volatile ("int $0"); - return 0; /* If trap returns... */ - } + if (den == 0) + { + asm volatile ("int $0"); + return 0; /* If trap returns... */ + } - /* Left-justify denominator and count shift */ - while ((int32_t) den >= 0) - { - den <<= 1; - qbit <<= 1; - } + /* Left-justify denominator and count shift */ + while ((int32_t) den >= 0) + { + den <<= 1; + qbit <<= 1; + } - while (qbit) - { - if (den <= num) - { - num -= den; - quot += qbit; - } - den >>= 1; - qbit >>= 1; - } + while (qbit) + { + if (den <= num) + { + num -= den; + quot += qbit; + } + den >>= 1; + qbit >>= 1; + } - return quot; + return quot; } diff --git a/libcpu/ia32/__umodsi3.c b/libcpu/ia32/__umodsi3.c index 226a2c0800..ddc5db5488 100644 --- a/libcpu/ia32/__umodsi3.c +++ b/libcpu/ia32/__umodsi3.c @@ -1,11 +1,7 @@ /* - * File : __umodsi3.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -16,31 +12,31 @@ uint32_t __umodsi3(uint32_t num, uint32_t den) { - register uint32_t quot = 0, qbit = 1; + register uint32_t quot = 0, qbit = 1; - if (den == 0) - { - asm volatile ("int $0"); - return 0; /* if trap returns... */ - } + if (den == 0) + { + asm volatile ("int $0"); + return 0; /* if trap returns... */ + } - /* left-justify denominator and count shift */ - while ((int32_t) den >= 0) - { - den <<= 1; - qbit <<= 1; - } + /* left-justify denominator and count shift */ + while ((int32_t) den >= 0) + { + den <<= 1; + qbit <<= 1; + } - while (qbit) - { - if (den <= num) - { - num -= den; - quot += qbit; - } - den >>= 1; - qbit >>= 1; - } + while (qbit) + { + if (den <= num) + { + num -= den; + quot += qbit; + } + den >>= 1; + qbit >>= 1; + } - return num; + return num; } diff --git a/libcpu/ia32/backtrace.c b/libcpu/ia32/backtrace.c deleted file mode 100644 index b8f094d90f..0000000000 --- a/libcpu/ia32/backtrace.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * File : backtrace.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2008-07-29 Bernard first version - */ - -#include <rtthread.h> - -void rt_hw_backtrace(rt_uint32_t *fp, rt_uint32_t thread_entry) -{ - /* no implementation */ -} diff --git a/libcpu/ia32/context_gcc.S b/libcpu/ia32/context_gcc.S index a8ad867b91..32233303c7 100644 --- a/libcpu/ia32/context_gcc.S +++ b/libcpu/ia32/context_gcc.S @@ -1,11 +1,7 @@ /* - * File : context_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -83,31 +79,3 @@ rt_hw_context_switch_to: pop %ds add $4, %esp /* skip irqno */ iret - -/* - * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to); - */ -.globl rt_thread_switch_interrupt_flag -.globl rt_interrupt_from_thread -.globl rt_interrupt_to_thread -.globl rt_hw_context_switch_interrupt -rt_hw_context_switch_interrupt: - pushl %ebp - movl %esp, %ebp - movl 0xc(%ebp), %eax - movl 0x8(%ebp), %ebx - - movl $rt_thread_switch_interrupt_flag, %ecx - movl (%ecx), %edx - cmp $0x1, %edx - jz _reswitch - - movl $0x1, %edx /*set rt_thread_switch_interrupt_flag to 1*/ - movl %edx, (%ecx) - movl $rt_interrupt_from_thread, %edx /*set rt_interrupt_from_thread*/ - movl %ebx, (%edx) -_reswitch: - movl $rt_interrupt_to_thread, %edx /*set rt_interrupt_to_thread*/ - movl %eax, (%edx) - leave - ret diff --git a/libcpu/ia32/cpuport.c b/libcpu/ia32/cpuport.c new file mode 100644 index 0000000000..2e0380d9f8 --- /dev/null +++ b/libcpu/ia32/cpuport.c @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2021/02/19 Bernard Implement rt_hw_context_switch_interrupt in C + */ + +#include <rthw.h> +#include <rtthread.h> + +volatile rt_ubase_t rt_interrupt_from_thread = 0; +volatile rt_ubase_t rt_interrupt_to_thread = 0; +volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0; + +rt_base_t rt_hw_interrupt_disable(void) +{ + rt_base_t level; + + __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory"); + return level; +} + +void rt_hw_interrupt_enable(rt_base_t level) +{ + __asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc"); +} + +void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) +{ + if (rt_thread_switch_interrupt_flag == 0) + rt_interrupt_from_thread = from; + + rt_interrupt_to_thread = to; + rt_thread_switch_interrupt_flag = 1; + + return ; +} + +/** + * This function will initialize thread stack + * + * @param tentry the entry of thread + * @param parameter the parameter of entry + * @param stack_addr the beginning stack address + * @param texit the function will be called when thread exit + * + * @return stack address + */ +rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, + rt_uint8_t *stack_addr, void *texit) +{ + unsigned long *stk; + + stk = (unsigned long *)stack_addr; + *(--stk) = (unsigned long)parameter; + *(--stk) = (unsigned long)texit; + *(--stk) = 0x200; /*flags*/ + *(--stk) = 0x08; /*cs*/ + *(--stk) = (unsigned long)tentry; /*eip*/ + *(--stk) = 0; /*irqno*/ + *(--stk) = 0x10; /*ds*/ + *(--stk) = 0x10; /*es*/ + *(--stk) = 0; /*eax*/ + *(--stk) = 0; /*ecx*/ + *(--stk) = 0; /*edx*/ + *(--stk) = 0; /*ebx*/ + *(--stk) = 0; /*esp*/ + *(--stk) = 0; /*ebp*/ + *(--stk) = 0; /*esi*/ + *(--stk) = 0; /*edi*/ + + /* return task's current stack address */ + return (rt_uint8_t *)stk; +} diff --git a/libcpu/ia32/hdisr_gcc.S b/libcpu/ia32/hdisr_gcc.S index 6f79fe4c2a..24c4c17990 100644 --- a/libcpu/ia32/hdisr_gcc.S +++ b/libcpu/ia32/hdisr_gcc.S @@ -1,11 +1,7 @@ /* - * File : hdisr_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/libcpu/ia32/interrupt.c b/libcpu/ia32/interrupt.c index e620cbe76c..473bf7714a 100644 --- a/libcpu/ia32/interrupt.c +++ b/libcpu/ia32/interrupt.c @@ -1,38 +1,20 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2015/9/15 Bernard Update to new interrupt framework. */ - -#include <rtthread.h> + #include <rthw.h> +#include <rtthread.h> #include <bsp.h> -extern rt_uint32_t rt_interrupt_nest; extern void rt_hw_idt_init(void); -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - /* exception and interrupt handler table */ struct rt_irq_desc irq_desc[MAX_HANDLERS]; @@ -50,45 +32,39 @@ void rt_hw_interrupt_handle(int vector, void* param); */ void rt_hw_pic_init() { - outb(IO_PIC1, 0x11); - outb(IO_PIC1+1, IRQ_OFFSET); - outb(IO_PIC1+1, 1<<IRQ_SLAVE); - outb(IO_PIC1+1, 0x3); - outb(IO_PIC1+1, 0xff); - outb(IO_PIC1, 0x68); - outb(IO_PIC1, 0x0a); - outb(IO_PIC2, 0x11); - outb(IO_PIC2+1, IRQ_OFFSET + 8); - outb(IO_PIC2+1, IRQ_SLAVE); - outb(IO_PIC2+1, 0x3); - outb(IO_PIC2+1, 0xff); - outb(IO_PIC2, 0x68); - outb(IO_PIC2, 0x0a); - - if (irq_mask_8259A != 0xFFFF) - { - outb(IO_PIC1+1, (char)irq_mask_8259A); - outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8)); - } + outb(IO_PIC1, 0x11); + outb(IO_PIC1+1, IRQ_OFFSET); + outb(IO_PIC1+1, 1<<IRQ_SLAVE); + outb(IO_PIC1+1, 0x3); + outb(IO_PIC1+1, 0xff); + outb(IO_PIC1, 0x68); + outb(IO_PIC1, 0x0a); + outb(IO_PIC2, 0x11); + outb(IO_PIC2+1, IRQ_OFFSET + 8); + outb(IO_PIC2+1, IRQ_SLAVE); + outb(IO_PIC2+1, 0x3); + outb(IO_PIC2+1, 0xff); + outb(IO_PIC2, 0x68); + outb(IO_PIC2, 0x0a); - /* init interrupt nest, and context */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + if (irq_mask_8259A != 0xFFFF) + { + outb(IO_PIC1+1, (char)irq_mask_8259A); + outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8)); + } } void rt_hw_interrupt_handle(int vector, void* param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } void rt_hw_isr(int vector) { - if (vector < MAX_HANDLERS) - { - irq_desc[vector].handler(vector, irq_desc[vector].param); - } + if (vector < MAX_HANDLERS) + { + irq_desc[vector].handler(vector, irq_desc[vector].param); + } } /** @@ -97,10 +73,10 @@ void rt_hw_isr(int vector) */ void rt_hw_interrupt_init(void) { - int idx; - - rt_hw_idt_init(); - rt_hw_pic_init(); + int idx; + + rt_hw_idt_init(); + rt_hw_pic_init(); /* init exceptions table */ for(idx=0; idx < MAX_HANDLERS; idx++) @@ -116,16 +92,16 @@ void rt_hw_interrupt_init(void) void rt_hw_interrupt_umask(int vector) { - irq_mask_8259A = irq_mask_8259A&~(1<<vector); - outb(IO_PIC1+1, (char)irq_mask_8259A); - outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8)); + irq_mask_8259A = irq_mask_8259A&~(1<<vector); + outb(IO_PIC1+1, (char)irq_mask_8259A); + outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8)); } void rt_hw_interrupt_mask(int vector) { - irq_mask_8259A = irq_mask_8259A | (1<<vector); - outb(IO_PIC1+1, (char)irq_mask_8259A); - outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8)); + irq_mask_8259A = irq_mask_8259A | (1<<vector); + outb(IO_PIC1+1, (char)irq_mask_8259A); + outb(IO_PIC2+1, (char)(irq_mask_8259A >> 8)); } rt_isr_handler_t rt_hw_interrupt_install(int vector, @@ -152,17 +128,4 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, return old_handler; } -rt_base_t rt_hw_interrupt_disable(void) -{ - rt_base_t level; - - __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (level): :"memory"); - return level; -} - -void rt_hw_interrupt_enable(rt_base_t level) -{ - __asm__ __volatile__("pushl %0 ; popfl": :"g" (level):"memory", "cc"); -} - /*@}*/ diff --git a/libcpu/ia32/showmem.c b/libcpu/ia32/showmem.c deleted file mode 100644 index 38f037f83d..0000000000 --- a/libcpu/ia32/showmem.c +++ /dev/null @@ -1,42 +0,0 @@ -/* - * File : showmem.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, 2008 RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - * 2008-07-29 Bernard first version from QiuYi implementation - */ - -#include <rtthread.h> - -void rt_hw_show_memory(rt_uint32_t addr, rt_uint32_t size) -{ - int i = 0, j =0; - - RT_ASSERT(addr); - - addr = addr & ~0xF; - size = 4*((size + 3)/4); - - while(i < size) - { - rt_kprintf("0x%08x: ", addr ); - - for(j=0; j<4; j++) - { - rt_kprintf("0x%08x ", *(rt_uint32_t *)addr); - - addr += 4; - i++; - } - - rt_kprintf("\n"); - } - - return; -} diff --git a/libcpu/ia32/stack.c b/libcpu/ia32/stack.c deleted file mode 100644 index 9d656a73d6..0000000000 --- a/libcpu/ia32/stack.c +++ /dev/null @@ -1,59 +0,0 @@ -/* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE - * - * Change Logs: - * Date Author Notes - */ - -#include <rtthread.h> - -#include <i386.h> - -/** - * @addtogroup I386 - */ -/*@{*/ - -/** - * This function will initialize thread stack - * - * @param tentry the entry of thread - * @param parameter the parameter of entry - * @param stack_addr the beginning stack address - * @param texit the function will be called when thread exit - * - * @return stack address - */ -rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) -{ - unsigned long *stk; - - stk = (unsigned long *)stack_addr; - *(--stk) = (unsigned long)parameter; - *(--stk) = (unsigned long)texit; - *(--stk) = 0x200; /*flags*/ - *(--stk) = 0x08; /*cs*/ - *(--stk) = (unsigned long)tentry; /*eip*/ - *(--stk) = 0; /*irqno*/ - *(--stk) = 0x10; /*ds*/ - *(--stk) = 0x10; /*es*/ - *(--stk) = 0; /*eax*/ - *(--stk) = 0; /*ecx*/ - *(--stk) = 0; /*edx*/ - *(--stk) = 0; /*ebx*/ - *(--stk) = 0; /*esp*/ - *(--stk) = 0; /*ebp*/ - *(--stk) = 0; /*esi*/ - *(--stk) = 0; /*edi*/ - - /* return task's current stack address */ - return (rt_uint8_t *)stk; -} -/*@}*/ diff --git a/libcpu/ia32/start_gcc.S b/libcpu/ia32/start_gcc.S index 84adc83fe2..ee7d2787fd 100644 --- a/libcpu/ia32/start_gcc.S +++ b/libcpu/ia32/start_gcc.S @@ -1,11 +1,7 @@ /* - * File : start.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -52,8 +48,8 @@ multiboot_entry: pushl $0 popf - /*rebuild globe describe table*/ - lgdt mygdtdesc + /* rebuild globe describe table */ + lgdt __gdtdesc movl $0x10,%eax movw %ax,%ds @@ -77,7 +73,7 @@ spin: .data .p2align 2 -mygdt: +__gdt: .word 0,0,0,0 .word 0x07FF /* 8Mb - limit=2047 */ @@ -90,8 +86,8 @@ mygdt: .word 0x9200 /* data read/write */ .word 0x00C0 -mygdtdesc: +__gdtdesc: .word 0x17 - .long mygdt + .long __gdt /*@}*/ diff --git a/libcpu/ia32/trap.c b/libcpu/ia32/trap.c index 5e9a51d6d2..c77a20c890 100644 --- a/libcpu/ia32/trap.c +++ b/libcpu/ia32/trap.c @@ -1,18 +1,14 @@ /* - * File : trap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://openlab.rt-thread.com/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes */ -#include <rtthread.h> #include <rthw.h> +#include <rtthread.h> #include <bsp.h> @@ -22,13 +18,14 @@ struct Gatedesc idt[256] = { {0}, }; struct Pseudodesc idt_pd = { - 0, sizeof(idt) - 1, (unsigned long) idt, + 0, sizeof(idt) - 1, (unsigned long) idt, }; /* exception and interrupt handler table */ extern rt_isr_handler_t isr_table[]; extern rt_isr_handler_t trap_func[]; extern rt_isr_handler_t hdinterrupt_func[]; +extern void rt_hw_interrupt_handle(int vector, void* param); /** * @addtogroup I386 @@ -40,36 +37,36 @@ extern rt_isr_handler_t hdinterrupt_func[]; * */ void rt_hw_idt_init(void) -{ - extern void Xdefault; - int i, j, func; +{ + extern void Xdefault(void); + int i, j, func; + + // install a default handler + for (i = 0; i < sizeof(idt)/sizeof(idt[0]); i++) + SETGATE(idt[i], 0, GD_KT, &Xdefault, 0); + + /*install trap handler*/ + for(i = 0; i < 16; i++) + { + func = (int)trap_func[i]; + SETGATE(idt[i], 0, GD_KT, func, 0); + } - // install a default handler - for (i = 0; i < sizeof(idt)/sizeof(idt[0]); i++) - SETGATE(idt[i], 0, GD_KT, &Xdefault, 0); + func = (int)trap_func[3]; + SETGATE(idt[3], 0, GD_KT, func, 3); - /*install trap handler*/ - for(i = 0; i < 16; i++) - { - func = (int)trap_func[i]; - SETGATE(idt[i], 0, GD_KT, func, 0); - } + i = 0; - func = (int)trap_func[3]; - SETGATE(idt[3], 0, GD_KT, func, 3); + /*install exteral interrupt handler*/ + for(j = IRQ_OFFSET; j < IRQ_OFFSET + MAX_HANDLERS; j++) + { + func = (int)hdinterrupt_func[i]; + SETGATE(idt[j], 0, GD_KT, func, 0); + i++; + } - i = 0; - - /*install exteral interrupt handler*/ - for(j = IRQ_OFFSET; j < IRQ_OFFSET + MAX_HANDLERS; j++) - { - func = (int)hdinterrupt_func[i]; - SETGATE(idt[j], 0, GD_KT, func, 0); - i++; - } - - // Load the IDT - asm volatile("lidt idt_pd + 2"); + // Load the IDT + asm volatile("lidt idt_pd + 2"); } /** @@ -80,24 +77,24 @@ void rt_hw_idt_init(void) */ void rt_hw_trap_irq(int trapno) { - switch(trapno) - { - case T_DIVIDE: - rt_kprintf("Divide error interrupt\n"); - RT_ASSERT(0); - case T_PGFLT: - rt_kprintf("Page fault interrupt\n"); - RT_ASSERT(0); - case T_GPFLT: - rt_kprintf("General protection interrupt\n"); - RT_ASSERT(0); - case T_DEFAULT: - rt_hw_interrupt_handle(T_DEFAULT); - return; - } + switch(trapno) + { + case T_DIVIDE: + rt_kprintf("Divide error interrupt\n"); + RT_ASSERT(0); + case T_PGFLT: + rt_kprintf("Page fault interrupt\n"); + RT_ASSERT(0); + case T_GPFLT: + rt_kprintf("General protection interrupt\n"); + RT_ASSERT(0); + case T_DEFAULT: + rt_hw_interrupt_handle(T_DEFAULT, RT_NULL); + return; + } - /*kernel bug if run here*/ - RT_ASSERT(0); + /*kernel bug if run here*/ + RT_ASSERT(0); } /*@}*/ diff --git a/libcpu/ia32/trapisr_gcc.S b/libcpu/ia32/trapisr_gcc.S index be7e97a5fb..82887ecda3 100644 --- a/libcpu/ia32/trapisr_gcc.S +++ b/libcpu/ia32/trapisr_gcc.S @@ -1,11 +1,7 @@ /* - * File : trapisr_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rt-thread.org/license/LICENSE + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -22,6 +18,7 @@ .globl proc;\ .type proc,@function;\ proc: + #define TRAPFNC(name,num)\ ENTRY(name)\ pushl $(num);\ @@ -29,6 +26,7 @@ .data;\ .long name;\ .text + #define TRAPFNC_NOEC(name,num)\ ENTRY(name)\ pushl $0;\ @@ -54,17 +52,17 @@ TRAPFNC_NOEC(Xoflow, 4) TRAPFNC_NOEC(Xbound, 5) TRAPFNC_NOEC(Xillop, 6) TRAPFNC_NOEC(Xdevice, 7) -TRAPFNC (Xdblflt, 8) -TRAPFNC (Xtss, 9) -TRAPFNC (Xsegnp, 10) -TRAPFNC (Xstack, 11) -TRAPFNC (Xgpflt, 12) -TRAPFNC (Xpgflt, 13) +TRAPFNC (Xdblflt, 8) +TRAPFNC (Xtss, 9) +TRAPFNC (Xsegnp, 10) +TRAPFNC (Xstack, 11) +TRAPFNC (Xgpflt, 12) +TRAPFNC (Xpgflt, 13) TRAPFNC_NOEC(Xfperr, 14) -TRAPFNC (Xalign, 15) +TRAPFNC (Xalign, 15) /* default handler -- not for any specific trap */ -TRAPFNC (Xdefault, 500) +TRAPFNC (Xdefault, 500) .p2align 4,0x90 .globl _traps diff --git a/libcpu/m16c/m16c62p/cpuport.c b/libcpu/m16c/m16c62p/cpuport.c index c66f73b727..8f9a50d89a 100644 --- a/libcpu/m16c/m16c62p/cpuport.c +++ b/libcpu/m16c/m16c62p/cpuport.c @@ -113,4 +113,4 @@ void rt_hw_interrupt_enable(rt_base_t level) temp = level & 0xffff; asm("LDC %0, FLG": :"r" (temp)); } -#endif
\ No newline at end of file +#endif diff --git a/libcpu/mips/common/asm.h b/libcpu/mips/common/asm.h index 1b39eea05a..355c05ab39 100644 --- a/libcpu/mips/common/asm.h +++ b/libcpu/mips/common/asm.h @@ -1,7 +1,7 @@ /* * Assembly Macros For MIPS * - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -18,101 +18,101 @@ /* * LEAF - declare leaf routine */ -#define LEAF(symbol) \ - .globl symbol; \ - .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ -symbol: .frame sp,0,ra +#define LEAF(symbol) \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ +symbol: .frame sp,0,ra /* * NESTED - declare nested routine entry point */ -#define NESTED(symbol, framesize, rpc) \ - .globl symbol; \ - .align 2; \ - .type symbol,@function; \ - .ent symbol,0; \ -symbol: .frame sp, framesize, rpc +#define NESTED(symbol, framesize, rpc) \ + .globl symbol; \ + .align 2; \ + .type symbol,@function; \ + .ent symbol,0; \ +symbol: .frame sp, framesize, rpc /* * END - mark end of function */ -#define END(function) \ - .end function; \ - .size function,.-function +#define END(function) \ + .end function; \ + .size function,.-function /* * EXPORT - export definition of symbol */ -#define EXPORT(symbol) \ - .globl symbol; \ +#define EXPORT(symbol) \ + .globl symbol; \ symbol: /* * FEXPORT - export definition of a function symbol */ -#define FEXPORT(symbol) \ - .globl symbol; \ - .type symbol,@function; \ +#define FEXPORT(symbol) \ + .globl symbol; \ + .type symbol,@function; \ symbol: /* * Global data declaration with size. */ -#define EXPORTS(name,sz) \ - .globl name; \ - .type name,@object; \ - .size name,sz; \ +#define EXPORTS(name,sz) \ + .globl name; \ + .type name,@object; \ + .size name,sz; \ name: /* * Weak data declaration with size. */ -#define WEXPORT(name,sz) \ - .weakext name; \ - .type name,@object; \ - .size name,sz; \ +#define WEXPORT(name,sz) \ + .weakext name; \ + .type name,@object; \ + .size name,sz; \ name: /* * Global data reference with size. */ -#define IMPORT(name, size) \ - .extern name,size +#define IMPORT(name, size) \ + .extern name,size /* * Global zeroed data. */ -#define BSS(name,size) \ - .type name,@object; \ - .comm name,size +#define BSS(name,size) \ + .type name,@object; \ + .comm name,size /* * Local zeroed data. */ -#define LBSS(name,size) \ - .lcomm name,size +#define LBSS(name,size) \ + .lcomm name,size /* * ABS - export absolute symbol */ -#define ABS(symbol,value) \ - .globl symbol; \ -symbol = value +#define ABS(symbol,value) \ + .globl symbol; \ +symbol = value -#define TEXT(msg) \ - .pushsection .data; \ -8: .asciiz msg; \ +#define TEXT(msg) \ + .pushsection .data; \ +8: .asciiz msg; \ .popsection; -#define ENTRY(name) \ - .globl name; \ - .align 2; \ - .ent name,0; \ +#define ENTRY(name) \ + .globl name; \ + .align 2; \ + .ent name,0; \ name##: /* @@ -122,185 +122,185 @@ symbol = value /* * Size of a register */ -#define SZREG 8 +#define SZREG 8 /* * Use the following macros in assemblercode to load/store registers, * pointers etc. */ -#define REG_S sd -#define REG_L ld -#define REG_SUBU dsubu -#define REG_ADDU daddu +#define REG_S sd +#define REG_L ld +#define REG_SUBU dsubu +#define REG_ADDU daddu /* * How to add/sub/load/store/shift C int variables. */ -#define INT_ADD dadd -#define INT_ADDU daddu -#define INT_ADDI daddi -#define INT_ADDIU daddiu -#define INT_SUB dsub -#define INT_SUBU dsubu -#define INT_L ld -#define INT_S sd -#define INT_SLL dsll -#define INT_SLLV dsllv -#define INT_SRL dsrl -#define INT_SRLV dsrlv -#define INT_SRA dsra -#define INT_SRAV dsrav +#define INT_ADD dadd +#define INT_ADDU daddu +#define INT_ADDI daddi +#define INT_ADDIU daddiu +#define INT_SUB dsub +#define INT_SUBU dsubu +#define INT_L ld +#define INT_S sd +#define INT_SLL dsll +#define INT_SLLV dsllv +#define INT_SRL dsrl +#define INT_SRLV dsrlv +#define INT_SRA dsra +#define INT_SRAV dsrav /* * Use the following macros in assemblercode to load/store registers, * pointers etc. */ -#define LONG_ADD dadd -#define LONG_ADDU daddu -#define LONG_ADDI daddi -#define LONG_ADDIU daddiu -#define LONG_SUB dsub -#define LONG_SUBU dsubu -#define LONG_L ld -#define LONG_S sd -#define LONG_SP sdp -#define LONG_SLL dsll -#define LONG_SLLV dsllv -#define LONG_SRL dsrl -#define LONG_SRLV dsrlv -#define LONG_SRA dsra -#define LONG_SRAV dsrav +#define LONG_ADD dadd +#define LONG_ADDU daddu +#define LONG_ADDI daddi +#define LONG_ADDIU daddiu +#define LONG_SUB dsub +#define LONG_SUBU dsubu +#define LONG_L ld +#define LONG_S sd +#define LONG_SP sdp +#define LONG_SLL dsll +#define LONG_SLLV dsllv +#define LONG_SRL dsrl +#define LONG_SRLV dsrlv +#define LONG_SRA dsra +#define LONG_SRAV dsrav -#define LONG .dword -#define LONGSIZE 8 -#define LONGMASK 7 -#define LONGLOG 3 +#define LONG .dword +#define LONGSIZE 8 +#define LONGMASK 7 +#define LONGLOG 3 /* * How to add/sub/load/store/shift pointers. */ -#define PTR_ADD dadd -#define PTR_ADDU daddu -#define PTR_ADDI daddi -#define PTR_ADDIU daddiu -#define PTR_SUB dsub -#define PTR_SUBU dsubu -#define PTR_L ld -#define PTR_S sd -#define PTR_LA dla -#define PTR_LI dli -#define PTR_SLL dsll -#define PTR_SLLV dsllv -#define PTR_SRL dsrl -#define PTR_SRLV dsrlv -#define PTR_SRA dsra -#define PTR_SRAV dsrav +#define PTR_ADD dadd +#define PTR_ADDU daddu +#define PTR_ADDI daddi +#define PTR_ADDIU daddiu +#define PTR_SUB dsub +#define PTR_SUBU dsubu +#define PTR_L ld +#define PTR_S sd +#define PTR_LA dla +#define PTR_LI dli +#define PTR_SLL dsll +#define PTR_SLLV dsllv +#define PTR_SRL dsrl +#define PTR_SRLV dsrlv +#define PTR_SRA dsra +#define PTR_SRAV dsrav -#define PTR_SCALESHIFT 3 +#define PTR_SCALESHIFT 3 -#define PTR .dword -#define PTRSIZE 8 -#define PTRLOG 3 +#define PTR .dword +#define PTRSIZE 8 +#define PTRLOG 3 -#define MFC0 dmfc0 -#define MTC0 dmtc0 +#define MFC0 dmfc0 +#define MTC0 dmtc0 #else /* * Size of a register */ -#define SZREG 4 +#define SZREG 4 /* * Use the following macros in assemblercode to load/store registers, * pointers etc. */ -#define REG_S sw -#define REG_L lw -#define REG_SUBU subu -#define REG_ADDU addu +#define REG_S sw +#define REG_L lw +#define REG_SUBU subu +#define REG_ADDU addu /* * How to add/sub/load/store/shift C int variables. */ -#define INT_ADD add -#define INT_ADDU addu -#define INT_ADDI addi -#define INT_ADDIU addiu -#define INT_SUB sub -#define INT_SUBU subu -#define INT_L lw -#define INT_S sw -#define INT_SLL sll -#define INT_SLLV sllv -#define INT_SRL srl -#define INT_SRLV srlv -#define INT_SRA sra -#define INT_SRAV srav +#define INT_ADD add +#define INT_ADDU addu +#define INT_ADDI addi +#define INT_ADDIU addiu +#define INT_SUB sub +#define INT_SUBU subu +#define INT_L lw +#define INT_S sw +#define INT_SLL sll +#define INT_SLLV sllv +#define INT_SRL srl +#define INT_SRLV srlv +#define INT_SRA sra +#define INT_SRAV srav /* * How to add/sub/load/store/shift C long variables. */ -#define LONG_ADD add -#define LONG_ADDU addu -#define LONG_ADDI addi -#define LONG_ADDIU addiu -#define LONG_SUB sub -#define LONG_SUBU subu -#define LONG_L lw -#define LONG_S sw -#define LONG_SLL sll -#define LONG_SLLV sllv -#define LONG_SRL srl -#define LONG_SRLV srlv -#define LONG_SRA sra -#define LONG_SRAV srav +#define LONG_ADD add +#define LONG_ADDU addu +#define LONG_ADDI addi +#define LONG_ADDIU addiu +#define LONG_SUB sub +#define LONG_SUBU subu +#define LONG_L lw +#define LONG_S sw +#define LONG_SLL sll +#define LONG_SLLV sllv +#define LONG_SRL srl +#define LONG_SRLV srlv +#define LONG_SRA sra +#define LONG_SRAV srav -#define LONG .word -#define LONGSIZE 4 -#define LONGMASK 3 -#define LONGLOG 2 +#define LONG .word +#define LONGSIZE 4 +#define LONGMASK 3 +#define LONGLOG 2 /* * How to add/sub/load/store/shift pointers. */ -#define PTR_ADD add -#define PTR_ADDU addu -#define PTR_ADDI addi -#define PTR_ADDIU addiu -#define PTR_SUB sub -#define PTR_SUBU subu -#define PTR_L lw -#define PTR_S sw -#define PTR_LA la -#define PTR_SLL sll -#define PTR_SLLV sllv -#define PTR_SRL srl -#define PTR_SRLV srlv -#define PTR_SRA sra -#define PTR_SRAV srav +#define PTR_ADD add +#define PTR_ADDU addu +#define PTR_ADDI addi +#define PTR_ADDIU addiu +#define PTR_SUB sub +#define PTR_SUBU subu +#define PTR_L lw +#define PTR_S sw +#define PTR_LA la +#define PTR_SLL sll +#define PTR_SLLV sllv +#define PTR_SRL srl +#define PTR_SRLV srlv +#define PTR_SRA sra +#define PTR_SRAV srav -#define PTR_SCALESHIFT 2 +#define PTR_SCALESHIFT 2 -#define PTR .word -#define PTRSIZE 4 -#define PTRLOG 2 +#define PTR .word +#define PTRSIZE 4 +#define PTRLOG 2 /* * Some cp0 registers were extended to 64bit for MIPS III. */ -#define MFC0 mfc0 -#define MTC0 mtc0 +#define MFC0 mfc0 +#define MTC0 mtc0 #endif -#define SSNOP sll zero, zero, 1 +#define SSNOP sll zero, zero, 1 #endif /* end of __ASM_H__ */ diff --git a/libcpu/mips/common/exception.c b/libcpu/mips/common/exception.c index 3da8ecead6..9c9858f5e1 100644 --- a/libcpu/mips/common/exception.c +++ b/libcpu/mips/common/exception.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -164,7 +164,7 @@ void rt_general_exc_dispatch(struct pt_regs *regs) { rt_ubase_t cause, exccode; cause = read_c0_cause(); - exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; + exccode = (cause & CAUSEF_EXCCODE) >> CAUSEB_EXCCODE; if (exccode == 0) { diff --git a/libcpu/mips/common/exception.h b/libcpu/mips/common/exception.h index 68107f6235..af9312b5bc 100644 --- a/libcpu/mips/common/exception.h +++ b/libcpu/mips/common/exception.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/common/mips.h b/libcpu/mips/common/mips.h index 94f664308c..abe3b73945 100644 --- a/libcpu/mips/common/mips.h +++ b/libcpu/mips/common/mips.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/common/mips_addrspace.h b/libcpu/mips/common/mips_addrspace.h index f3bb60662e..0bc6a5f181 100644 --- a/libcpu/mips/common/mips_addrspace.h +++ b/libcpu/mips/common/mips_addrspace.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,15 +19,15 @@ #define _ATYPE_ #define _ATYPE32_ #define _ATYPE64_ -#define _CONST64_(x) x +#define _CONST64_(x) x #else -#define _ATYPE_ __PTRDIFF_TYPE__ -#define _ATYPE32_ int -#define _ATYPE64_ __s64 +#define _ATYPE_ __PTRDIFF_TYPE__ +#define _ATYPE32_ int +#define _ATYPE64_ __s64 #ifdef ARCH_MIPS64 -#define _CONST64_(x) x ## L +#define _CONST64_(x) x ## L #else -#define _CONST64_(x) x ## LL +#define _CONST64_(x) x ## LL #endif #endif @@ -38,21 +38,21 @@ #define _ACAST32_ #define _ACAST64_ #else -#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ -#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ +#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */ +#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */ #endif /* * Returns the kernel segment base of a given address */ -#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) +#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000) /* * Returns the physical address of a CKSEGx / XKPHYS address */ -#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) -#define XPHYSADDR(a) ((_ACAST64_(a)) & \ - _CONST64_(0x000000ffffffffff)) +#define CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff) +#define XPHYSADDR(a) ((_ACAST64_(a)) & \ + _CONST64_(0x000000ffffffffff)) #ifdef ARCH_MIPS64 @@ -61,56 +61,56 @@ * The compatibility segments use the full 64-bit sign extended value. Note * the R8000 doesn't have them so don't reference these in generic MIPS code. */ -#define XKUSEG _CONST64_(0x0000000000000000) -#define XKSSEG _CONST64_(0x4000000000000000) -#define XKPHYS _CONST64_(0x8000000000000000) -#define XKSEG _CONST64_(0xc000000000000000) -#define CKSEG0 _CONST64_(0xffffffff80000000) -#define CKSEG1 _CONST64_(0xffffffffa0000000) -#define CKSSEG _CONST64_(0xffffffffc0000000) -#define CKSEG3 _CONST64_(0xffffffffe0000000) +#define XKUSEG _CONST64_(0x0000000000000000) +#define XKSSEG _CONST64_(0x4000000000000000) +#define XKPHYS _CONST64_(0x8000000000000000) +#define XKSEG _CONST64_(0xc000000000000000) +#define CKSEG0 _CONST64_(0xffffffff80000000) +#define CKSEG1 _CONST64_(0xffffffffa0000000) +#define CKSSEG _CONST64_(0xffffffffc0000000) +#define CKSEG3 _CONST64_(0xffffffffe0000000) -#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) +#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) -#define KUSEGBASE 0xffffffff00000000 -#define KSEG0BASE 0xffffffff80000000 -#define KSEG1BASE 0xffffffffa0000000 -#define KSEG2BASE 0xffffffffc0000000 -#define KSEG3BASE 0xffffffffe0000000 +#define KUSEGBASE 0xffffffff00000000 +#define KSEG0BASE 0xffffffff80000000 +#define KSEG1BASE 0xffffffffa0000000 +#define KSEG2BASE 0xffffffffc0000000 +#define KSEG3BASE 0xffffffffe0000000 #else -#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) -#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) -#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) -#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) +#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) +#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) +#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) +#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) /* * Map an address to a certain kernel segment */ -#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) -#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) -#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) -#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) +#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0BASE) +#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1BASE) +#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2BASE) +#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3BASE) -#define CKUSEG 0x00000000 -#define CKSEG0 0x80000000 -#define CKSEG1 0xa0000000 -#define CKSEG2 0xc0000000 -#define CKSEG3 0xe0000000 +#define CKUSEG 0x00000000 +#define CKSEG0 0x80000000 +#define CKSEG1 0xa0000000 +#define CKSEG2 0xc0000000 +#define CKSEG3 0xe0000000 /* * Memory segments (32bit kernel mode addresses) * These are the traditional names used in the 32-bit universe. */ -#define KUSEGBASE 0x00000000 -#define KSEG0BASE 0x80000000 -#define KSEG1BASE 0xa0000000 -#define KSEG2BASE 0xc0000000 -#define KSEG3BASE 0xe0000000 +#define KUSEGBASE 0x00000000 +#define KSEG0BASE 0x80000000 +#define KSEG1BASE 0xa0000000 +#define KSEG2BASE 0xc0000000 +#define KSEG3BASE 0xe0000000 #endif @@ -118,23 +118,23 @@ /* * Cache modes for XKPHYS address conversion macros */ -#define K_CALG_COH_EXCL1_NOL2 0 -#define K_CALG_COH_SHRL1_NOL2 1 -#define K_CALG_UNCACHED 2 -#define K_CALG_NONCOHERENT 3 -#define K_CALG_COH_EXCL 4 -#define K_CALG_COH_SHAREABLE 5 -#define K_CALG_NOTUSED 6 -#define K_CALG_UNCACHED_ACCEL 7 +#define K_CALG_COH_EXCL1_NOL2 0 +#define K_CALG_COH_SHRL1_NOL2 1 +#define K_CALG_UNCACHED 2 +#define K_CALG_NONCOHERENT 3 +#define K_CALG_COH_EXCL 4 +#define K_CALG_COH_SHAREABLE 5 +#define K_CALG_NOTUSED 6 +#define K_CALG_UNCACHED_ACCEL 7 /* * 64-bit address conversions */ -#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) -#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) -#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) -#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ - (_CONST64_(cm) << 59) | (a)) +#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p)) +#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p)) +#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK) +#define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ + (_CONST64_(cm) << 59) | (a)) /* * Returns the uncached address of a sdram address @@ -146,20 +146,20 @@ * the region, 3 bits for the CCA mode. This leaves 59 bits of which the * R8000 implements most with its 48-bit physical address space. */ -#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ -#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) -#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ +#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ +#define COMPAT_K1BASE32 _CONST64_(0xffffffffa0000000) +#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */ -#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) -#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) +#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK) +#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE) #endif #ifndef __ASSEMBLY__ -#define REG8( addr ) (*(volatile u8 *) (addr)) -#define REG16( addr ) (*(volatile u16 *)(addr)) -#define REG32( addr ) (*(volatile u32 *)(addr)) -#define REG64( addr ) (*(volatile u64 *)(addr)) +#define REG8( addr ) (*(volatile u8 *) (addr)) +#define REG16( addr ) (*(volatile u16 *)(addr)) +#define REG32( addr ) (*(volatile u32 *)(addr)) +#define REG64( addr ) (*(volatile u64 *)(addr)) #endif #endif /* _MIPS_ADDRSPACE_H_ */ diff --git a/libcpu/mips/common/mips_cache.c b/libcpu/mips/common/mips_cache.c index 8c86bb131a..a969f5c751 100644 --- a/libcpu/mips/common/mips_cache.c +++ b/libcpu/mips/common/mips_cache.c @@ -1,21 +1,7 @@ /* - * File : mips_cache.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -28,7 +14,7 @@ extern void cache_init(rt_ubase_t cache_size, rt_ubase_t cache_line_size); void r4k_cache_init(void) { -// cache_init(dcache_size, cpu_dcache_line_size); +// cache_init(dcache_size, cpu_dcache_line_size); } void r4k_cache_flush_all(void) @@ -45,7 +31,7 @@ void r4k_icache_flush_all(void) void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; + rt_ubase_t end, a; if (size > g_mips_core.icache_size) { @@ -53,7 +39,7 @@ void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) } else { - rt_ubase_t ic_lsize = g_mips_core.icache_line_size; + rt_ubase_t ic_lsize = g_mips_core.icache_line_size; a = addr & ~(ic_lsize - 1); end = ((addr + size) - 1) & ~(ic_lsize - 1); @@ -69,8 +55,8 @@ void r4k_icache_flush_range(rt_ubase_t addr, rt_ubase_t size) void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; - rt_ubase_t ic_lsize = g_mips_core.icache_line_size; + rt_ubase_t end, a; + rt_ubase_t ic_lsize = g_mips_core.icache_line_size; a = addr & ~(ic_lsize - 1); end = ((addr + size) - 1) & ~(ic_lsize - 1); @@ -85,7 +71,7 @@ void r4k_icache_lock_range(rt_ubase_t addr, rt_ubase_t size) void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; + rt_ubase_t end, a; rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; a = addr & ~(dc_lsize - 1); @@ -101,7 +87,7 @@ void r4k_dcache_inv(rt_ubase_t addr, rt_ubase_t size) void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size) { - rt_ubase_t end, a; + rt_ubase_t end, a; if (size >= g_mips_core.dcache_size) { @@ -109,7 +95,7 @@ void r4k_dcache_wback_inv(rt_ubase_t addr, rt_ubase_t size) } else { - rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; + rt_ubase_t dc_lsize = g_mips_core.dcache_line_size; a = addr & ~(dc_lsize - 1); end = ((addr + size) - 1) & ~(dc_lsize - 1); diff --git a/libcpu/mips/common/mips_cache.h b/libcpu/mips/common/mips_cache.h index 438dd76cde..4a459b1ae4 100644 --- a/libcpu/mips/common/mips_cache.h +++ b/libcpu/mips/common/mips_cache.h @@ -1,21 +1,7 @@ /* - * File : mips_cache.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -116,7 +102,7 @@ enum dma_data_direction #define INDEX_STORE_DATA_D 0x1d #define INDEX_STORE_DATA_S 0x1f -#define cache_op(op, addr) \ +#define cache_op(op, addr) \ __asm__ __volatile__( \ ".set push\n" \ ".set noreorder\n" \ @@ -126,95 +112,95 @@ enum dma_data_direction : \ : "i" (op), "R" (*(unsigned char *)(addr))) -#define cache16_unroll32(base, op) \ - __asm__ __volatile__( \ - " .set noreorder \n" \ - " .set mips3 \n" \ - " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ - " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ - " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ - " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ - " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ - " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ - " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ - " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ - " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ - " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ - " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ - " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ - " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ - " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ - " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ - " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ - " .set mips0 \n" \ - " .set reorder \n" \ - : \ - : "r" (base), \ - "i" (op)); +#define cache16_unroll32(base, op) \ + __asm__ __volatile__( \ + " .set noreorder \n" \ + " .set mips3 \n" \ + " cache %1, 0x000(%0); cache %1, 0x010(%0) \n" \ + " cache %1, 0x020(%0); cache %1, 0x030(%0) \n" \ + " cache %1, 0x040(%0); cache %1, 0x050(%0) \n" \ + " cache %1, 0x060(%0); cache %1, 0x070(%0) \n" \ + " cache %1, 0x080(%0); cache %1, 0x090(%0) \n" \ + " cache %1, 0x0a0(%0); cache %1, 0x0b0(%0) \n" \ + " cache %1, 0x0c0(%0); cache %1, 0x0d0(%0) \n" \ + " cache %1, 0x0e0(%0); cache %1, 0x0f0(%0) \n" \ + " cache %1, 0x100(%0); cache %1, 0x110(%0) \n" \ + " cache %1, 0x120(%0); cache %1, 0x130(%0) \n" \ + " cache %1, 0x140(%0); cache %1, 0x150(%0) \n" \ + " cache %1, 0x160(%0); cache %1, 0x170(%0) \n" \ + " cache %1, 0x180(%0); cache %1, 0x190(%0) \n" \ + " cache %1, 0x1a0(%0); cache %1, 0x1b0(%0) \n" \ + " cache %1, 0x1c0(%0); cache %1, 0x1d0(%0) \n" \ + " cache %1, 0x1e0(%0); cache %1, 0x1f0(%0) \n" \ + " .set mips0 \n" \ + " .set reorder \n" \ + : \ + : "r" (base), \ + "i" (op)); static inline void flush_icache_line_indexed(rt_ubase_t addr) { - cache_op(INDEX_INVALIDATE_I, addr); + cache_op(INDEX_INVALIDATE_I, addr); } static inline void flush_dcache_line_indexed(rt_ubase_t addr) { - cache_op(INDEX_WRITEBACK_INV_D, addr); + cache_op(INDEX_WRITEBACK_INV_D, addr); } static inline void flush_icache_line(rt_ubase_t addr) { - cache_op(HIT_INVALIDATE_I, addr); + cache_op(HIT_INVALIDATE_I, addr); } static inline void lock_icache_line(rt_ubase_t addr) { - cache_op(FETCH_AND_LOCK_I, addr); + cache_op(FETCH_AND_LOCK_I, addr); } static inline void lock_dcache_line(rt_ubase_t addr) { - cache_op(FETCH_AND_LOCK_D, addr); + cache_op(FETCH_AND_LOCK_D, addr); } static inline void flush_dcache_line(rt_ubase_t addr) { - cache_op(HIT_WRITEBACK_INV_D, addr); + cache_op(HIT_WRITEBACK_INV_D, addr); } static inline void invalidate_dcache_line(rt_ubase_t addr) { - cache_op(HIT_INVALIDATE_D, addr); + cache_op(HIT_INVALIDATE_D, addr); } static inline void blast_dcache16(void) { - rt_ubase_t start = KSEG0BASE; - rt_ubase_t end = start + g_mips_core.dcache_size; - rt_ubase_t addr; + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.dcache_size; + rt_ubase_t addr; - for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) - cache16_unroll32(addr, INDEX_WRITEBACK_INV_D); + for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) + cache16_unroll32(addr, INDEX_WRITEBACK_INV_D); } static inline void inv_dcache16(void) { - rt_ubase_t start = KSEG0BASE; - rt_ubase_t end = start + g_mips_core.dcache_size; - rt_ubase_t addr; + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.dcache_size; + rt_ubase_t addr; - for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) - cache16_unroll32(addr, HIT_INVALIDATE_D); + for (addr = start; addr < end; addr += g_mips_core.dcache_line_size) + cache16_unroll32(addr, HIT_INVALIDATE_D); } static inline void blast_icache16(void) { - rt_ubase_t start = KSEG0BASE; - rt_ubase_t end = start + g_mips_core.icache_size; - rt_ubase_t addr; + rt_ubase_t start = KSEG0BASE; + rt_ubase_t end = start + g_mips_core.icache_size; + rt_ubase_t addr; - for (addr = start; addr < end; addr += g_mips_core.icache_line_size) - cache16_unroll32(addr, INDEX_INVALIDATE_I); + for (addr = start; addr < end; addr += g_mips_core.icache_line_size) + cache16_unroll32(addr, INDEX_INVALIDATE_I); } void r4k_cache_init(void); diff --git a/libcpu/mips/common/mips_cfg.h b/libcpu/mips/common/mips_cfg.h index f7e38b4af4..d5531e35fb 100644 --- a/libcpu/mips/common/mips_cfg.h +++ b/libcpu/mips/common/mips_cfg.h @@ -1,21 +1,7 @@ /* - * File : mips_cfg.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -38,7 +24,7 @@ typedef struct mips32_core_cfg uint16_t dcache_ways; uint16_t dcache_size; - uint16_t max_tlb_entries; /* number of tlb entry */ + uint16_t max_tlb_entries; /* number of tlb entry */ } mips32_core_cfg_t; extern mips32_core_cfg_t g_mips_core; diff --git a/libcpu/mips/common/mips_fpu.h b/libcpu/mips/common/mips_fpu.h index 50df3746a5..85aa125fa3 100644 --- a/libcpu/mips/common/mips_fpu.h +++ b/libcpu/mips/common/mips_fpu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/common/mips_regs.h b/libcpu/mips/common/mips_regs.h index a13e24b539..a2f6053cf5 100644 --- a/libcpu/mips/common/mips_regs.h +++ b/libcpu/mips/common/mips_regs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -11,129 +11,129 @@ #ifndef _MIPS_REGS_H_ #define _MIPS_REGS_H_ #include <rtconfig.h> -#define REG_A0 4 -#define REG_SP 29 -#define REG_GP 28 -#define REG_FP 30 -#define REG_RA 31 +#define REG_A0 4 +#define REG_SP 29 +#define REG_GP 28 +#define REG_FP 30 +#define REG_RA 31 #ifndef ARCH_MIPS64 -#define zero $0 /* wired zero */ -#define AT $1 /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define t0 $8 /* caller saved */ -#define t1 $9 -#define t2 $10 -#define t3 $11 -#define t4 $12 -#define ta0 $12 -#define t5 $13 -#define ta1 $13 -#define t6 $14 -#define ta2 $14 -#define t7 $15 -#define ta3 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel scratch */ -#define k1 $27 -#define gp $28 /* global pointer */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* same like fp! */ -#define ra $31 /* return address */ +#define zero $0 /* wired zero */ +#define AT $1 /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 /* caller saved */ +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define ta0 $12 +#define t5 $13 +#define ta1 $13 +#define t6 $14 +#define ta2 $14 +#define t7 $15 +#define ta3 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel scratch */ +#define k1 $27 +#define gp $28 /* global pointer */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* same like fp! */ +#define ra $31 /* return address */ #else -#define zero $0 /* wired zero */ -#define AT $at /* assembler temp - uppercase because of ".set at" */ -#define v0 $2 /* return value - caller saved */ -#define v1 $3 -#define a0 $4 /* argument registers */ -#define a1 $5 -#define a2 $6 -#define a3 $7 -#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ -#define ta0 $8 -#define a5 $9 -#define ta1 $9 -#define a6 $10 -#define ta2 $10 -#define a7 $11 -#define ta3 $11 -#define t0 $12 /* caller saved */ -#define t1 $13 -#define t2 $14 -#define t3 $15 -#define s0 $16 /* callee saved */ -#define s1 $17 -#define s2 $18 -#define s3 $19 -#define s4 $20 -#define s5 $21 -#define s6 $22 -#define s7 $23 -#define t8 $24 /* caller saved */ -#define t9 $25 /* callee address for PIC/temp */ -#define jp $25 /* PIC jump register */ -#define k0 $26 /* kernel temporary */ -#define k1 $27 -#define gp $28 /* global pointer - caller saved for PIC */ -#define sp $29 /* stack pointer */ -#define fp $30 /* frame pointer */ -#define s8 $30 /* callee saved */ -#define ra $31 /* return address */ +#define zero $0 /* wired zero */ +#define AT $at /* assembler temp - uppercase because of ".set at" */ +#define v0 $2 /* return value - caller saved */ +#define v1 $3 +#define a0 $4 /* argument registers */ +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */ +#define ta0 $8 +#define a5 $9 +#define ta1 $9 +#define a6 $10 +#define ta2 $10 +#define a7 $11 +#define ta3 $11 +#define t0 $12 /* caller saved */ +#define t1 $13 +#define t2 $14 +#define t3 $15 +#define s0 $16 /* callee saved */ +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 /* caller saved */ +#define t9 $25 /* callee address for PIC/temp */ +#define jp $25 /* PIC jump register */ +#define k0 $26 /* kernel temporary */ +#define k1 $27 +#define gp $28 /* global pointer - caller saved for PIC */ +#define sp $29 /* stack pointer */ +#define fp $30 /* frame pointer */ +#define s8 $30 /* callee saved */ +#define ra $31 /* return address */ #endif -#define fv0 $f0 /* return value */ -#define fv0f $f1 -#define fv1 $f2 -#define fv1f $f3 -#define fa0 $f12 /* argument registers */ -#define fa0f $f13 -#define fa1 $f14 -#define fa1f $f15 -#define ft0 $f4 /* caller saved */ -#define ft0f $f5 -#define ft1 $f6 -#define ft1f $f7 -#define ft2 $f8 -#define ft2f $f9 -#define ft3 $f10 -#define ft3f $f11 -#define ft4 $f16 -#define ft4f $f17 -#define ft5 $f18 -#define ft5f $f19 -#define fs0 $f20 /* callee saved */ -#define fs0f $f21 -#define fs1 $f22 -#define fs1f $f23 -#define fs2 $f24 -#define fs2f $f25 -#define fs3 $f26 -#define fs3f $f27 -#define fs4 $f28 -#define fs4f $f29 -#define fs5 $f30 -#define fs5f $f31 +#define fv0 $f0 /* return value */ +#define fv0f $f1 +#define fv1 $f2 +#define fv1f $f3 +#define fa0 $f12 /* argument registers */ +#define fa0f $f13 +#define fa1 $f14 +#define fa1f $f15 +#define ft0 $f4 /* caller saved */ +#define ft0f $f5 +#define ft1 $f6 +#define ft1f $f7 +#define ft2 $f8 +#define ft2f $f9 +#define ft3 $f10 +#define ft3f $f11 +#define ft4 $f16 +#define ft4f $f17 +#define ft5 $f18 +#define ft5f $f19 +#define fs0 $f20 /* callee saved */ +#define fs0f $f21 +#define fs1 $f22 +#define fs1f $f23 +#define fs2 $f24 +#define fs2f $f25 +#define fs3 $f26 +#define fs3f $f27 +#define fs4 $f28 +#define fs4f $f29 +#define fs5 $f30 +#define fs5f $f31 -#define fcr31 $31 /* FPU status register */ +#define fcr31 $31 /* FPU status register */ /* @@ -217,157 +217,157 @@ /* * TX39 Series */ -#define CP0_TX39_CACHE $7 +#define CP0_TX39_CACHE $7 /* * Coprocessor 1 (FPU) register names */ -#define CP1_REVISION $0 -#define CP1_UFR $1 -#define CP1_UNFR $4 -#define CP1_FCCR $25 -#define CP1_FEXR $26 -#define CP1_FENR $28 -#define CP1_STATUS $31 +#define CP1_REVISION $0 +#define CP1_UFR $1 +#define CP1_UNFR $4 +#define CP1_FCCR $25 +#define CP1_FEXR $26 +#define CP1_FENR $28 +#define CP1_STATUS $31 /* * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. */ -#define MIPS_FPIR_S (_ULCAST_(1) << 16) -#define MIPS_FPIR_D (_ULCAST_(1) << 17) -#define MIPS_FPIR_PS (_ULCAST_(1) << 18) -#define MIPS_FPIR_3D (_ULCAST_(1) << 19) -#define MIPS_FPIR_W (_ULCAST_(1) << 20) -#define MIPS_FPIR_L (_ULCAST_(1) << 21) -#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) -#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) -#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) -#define MIPS_FPIR_FREP (_ULCAST_(1) << 29) +#define MIPS_FPIR_S (_ULCAST_(1) << 16) +#define MIPS_FPIR_D (_ULCAST_(1) << 17) +#define MIPS_FPIR_PS (_ULCAST_(1) << 18) +#define MIPS_FPIR_3D (_ULCAST_(1) << 19) +#define MIPS_FPIR_W (_ULCAST_(1) << 20) +#define MIPS_FPIR_L (_ULCAST_(1) << 21) +#define MIPS_FPIR_F64 (_ULCAST_(1) << 22) +#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) +#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) +#define MIPS_FPIR_FREP (_ULCAST_(1) << 29) /* * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register. */ -#define MIPS_FCCR_CONDX_S 0 -#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S) -#define MIPS_FCCR_COND0_S 0 -#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S) -#define MIPS_FCCR_COND1_S 1 -#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S) -#define MIPS_FCCR_COND2_S 2 -#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S) -#define MIPS_FCCR_COND3_S 3 -#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S) -#define MIPS_FCCR_COND4_S 4 -#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S) -#define MIPS_FCCR_COND5_S 5 -#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S) -#define MIPS_FCCR_COND6_S 6 -#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S) -#define MIPS_FCCR_COND7_S 7 -#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S) +#define MIPS_FCCR_CONDX_S 0 +#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S) +#define MIPS_FCCR_COND0_S 0 +#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S) +#define MIPS_FCCR_COND1_S 1 +#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S) +#define MIPS_FCCR_COND2_S 2 +#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S) +#define MIPS_FCCR_COND3_S 3 +#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S) +#define MIPS_FCCR_COND4_S 4 +#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S) +#define MIPS_FCCR_COND5_S 5 +#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S) +#define MIPS_FCCR_COND6_S 6 +#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S) +#define MIPS_FCCR_COND7_S 7 +#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S) /* * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register. */ -#define MIPS_FENR_FS_S 2 -#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S) +#define MIPS_FENR_FS_S 2 +#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S) /* * FPU Status Register Values */ -#define FPU_CSR_COND_S 23 /* $fcc0 */ -#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S) +#define FPU_CSR_COND_S 23 /* $fcc0 */ +#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S) -#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */ -#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S) +#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */ +#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S) #define FPU_CSR_FO 0x00400000 #define FPU_CSR_FN 0x00200000 -#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */ -#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S) -#define FPU_CSR_COND1_S 25 /* $fcc1 */ -#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S) -#define FPU_CSR_COND2_S 26 /* $fcc2 */ -#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S) -#define FPU_CSR_COND3_S 27 /* $fcc3 */ -#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S) -#define FPU_CSR_COND4_S 28 /* $fcc4 */ -#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S) -#define FPU_CSR_COND5_S 29 /* $fcc5 */ -#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S) -#define FPU_CSR_COND6_S 30 /* $fcc6 */ -#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S) -#define FPU_CSR_COND7_S 31 /* $fcc7 */ -#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) +#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */ +#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S) +#define FPU_CSR_COND1_S 25 /* $fcc1 */ +#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S) +#define FPU_CSR_COND2_S 26 /* $fcc2 */ +#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S) +#define FPU_CSR_COND3_S 27 /* $fcc3 */ +#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S) +#define FPU_CSR_COND4_S 28 /* $fcc4 */ +#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S) +#define FPU_CSR_COND5_S 29 /* $fcc5 */ +#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S) +#define FPU_CSR_COND6_S 30 /* $fcc6 */ +#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S) +#define FPU_CSR_COND7_S 31 /* $fcc7 */ +#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) /* * Bits 22:20 of the FPU Status Register will be read as 0, * and should be written as zero. */ -#define FPU_CSR_RSVD (_ULCAST_(7) << 20) +#define FPU_CSR_RSVD (_ULCAST_(7) << 20) -#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) -#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) +#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) +#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) /* * X the exception cause indicator * E the exception enable * S the sticky/flag bit */ -#define FPU_CSR_ALL_X 0x0003f000 -#define FPU_CSR_UNI_X 0x00020000 -#define FPU_CSR_INV_X 0x00010000 -#define FPU_CSR_DIV_X 0x00008000 -#define FPU_CSR_OVF_X 0x00004000 -#define FPU_CSR_UDF_X 0x00002000 -#define FPU_CSR_INE_X 0x00001000 +#define FPU_CSR_ALL_X 0x0003f000 +#define FPU_CSR_UNI_X 0x00020000 +#define FPU_CSR_INV_X 0x00010000 +#define FPU_CSR_DIV_X 0x00008000 +#define FPU_CSR_OVF_X 0x00004000 +#define FPU_CSR_UDF_X 0x00002000 +#define FPU_CSR_INE_X 0x00001000 -#define FPU_CSR_ALL_E 0x00000f80 -#define FPU_CSR_INV_E 0x00000800 -#define FPU_CSR_DIV_E 0x00000400 -#define FPU_CSR_OVF_E 0x00000200 -#define FPU_CSR_UDF_E 0x00000100 -#define FPU_CSR_INE_E 0x00000080 +#define FPU_CSR_ALL_E 0x00000f80 +#define FPU_CSR_INV_E 0x00000800 +#define FPU_CSR_DIV_E 0x00000400 +#define FPU_CSR_OVF_E 0x00000200 +#define FPU_CSR_UDF_E 0x00000100 +#define FPU_CSR_INE_E 0x00000080 -#define FPU_CSR_ALL_S 0x0000007c -#define FPU_CSR_INV_S 0x00000040 -#define FPU_CSR_DIV_S 0x00000020 -#define FPU_CSR_OVF_S 0x00000010 -#define FPU_CSR_UDF_S 0x00000008 -#define FPU_CSR_INE_S 0x00000004 +#define FPU_CSR_ALL_S 0x0000007c +#define FPU_CSR_INV_S 0x00000040 +#define FPU_CSR_DIV_S 0x00000020 +#define FPU_CSR_OVF_S 0x00000010 +#define FPU_CSR_UDF_S 0x00000008 +#define FPU_CSR_INE_S 0x00000004 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ -#define FPU_CSR_RM 0x00000003 -#define FPU_CSR_RN 0x0 /* nearest */ -#define FPU_CSR_RZ 0x1 /* towards zero */ -#define FPU_CSR_RU 0x2 /* towards +Infinity */ -#define FPU_CSR_RD 0x3 /* towards -Infinity */ +#define FPU_CSR_RM 0x00000003 +#define FPU_CSR_RN 0x0 /* nearest */ +#define FPU_CSR_RZ 0x1 /* towards zero */ +#define FPU_CSR_RU 0x2 /* towards +Infinity */ +#define FPU_CSR_RD 0x3 /* towards -Infinity */ -#define PM_4K 0x00000000 -#define PM_16K 0x00006000 -#define PM_64K 0x0001e000 -#define PM_256K 0x0007e000 -#define PM_1M 0x001fe000 -#define PM_4M 0x007fe000 -#define PM_16M 0x01ffe000 -#define PM_64M 0x07ffe000 -#define PM_256M 0x1fffe000 +#define PM_4K 0x00000000 +#define PM_16K 0x00006000 +#define PM_64K 0x0001e000 +#define PM_256K 0x0007e000 +#define PM_1M 0x001fe000 +#define PM_4M 0x007fe000 +#define PM_16M 0x01ffe000 +#define PM_64M 0x07ffe000 +#define PM_256M 0x1fffe000 /* * Values used for computation of new tlb entries */ -#define PL_4K 12 -#define PL_16K 14 -#define PL_64K 16 -#define PL_256K 18 -#define PL_1M 20 -#define PL_4M 22 -#define PL_16M 24 -#define PL_64M 26 -#define PL_256M 28 +#define PL_4K 12 +#define PL_16K 14 +#define PL_64K 16 +#define PL_256K 18 +#define PL_1M 20 +#define PL_4M 22 +#define PL_16M 24 +#define PL_64M 26 +#define PL_256M 28 /* * R4x00 interrupt enable / cause bits @@ -396,202 +396,202 @@ /* * Bitfields in the R4xx0 cp0 status register */ -#define ST0_IE 0x00000001 -#define ST0_EXL 0x00000002 -#define ST0_ERL 0x00000004 -#define ST0_KSU 0x00000018 -# define KSU_USER 0x00000010 -# define KSU_SUPERVISOR 0x00000008 -# define KSU_KERNEL 0x00000000 -#define ST0_UX 0x00000020 -#define ST0_SX 0x00000040 -#define ST0_KX 0x00000080 -#define ST0_DE 0x00010000 -#define ST0_CE 0x00020000 +#define ST0_IE 0x00000001 +#define ST0_EXL 0x00000002 +#define ST0_ERL 0x00000004 +#define ST0_KSU 0x00000018 +# define KSU_USER 0x00000010 +# define KSU_SUPERVISOR 0x00000008 +# define KSU_KERNEL 0x00000000 +#define ST0_UX 0x00000020 +#define ST0_SX 0x00000040 +#define ST0_KX 0x00000080 +#define ST0_DE 0x00010000 +#define ST0_CE 0x00020000 /* * Bitfields in the R[23]000 cp0 status register. */ #define ST0_IEC 0x00000001 -#define ST0_KUC 0x00000002 -#define ST0_IEP 0x00000004 -#define ST0_KUP 0x00000008 -#define ST0_IEO 0x00000010 -#define ST0_KUO 0x00000020 +#define ST0_KUC 0x00000002 +#define ST0_IEP 0x00000004 +#define ST0_KUP 0x00000008 +#define ST0_IEO 0x00000010 +#define ST0_KUO 0x00000020 /* bits 6 & 7 are reserved on R[23]000 */ -#define ST0_ISC 0x00010000 -#define ST0_SWC 0x00020000 -#define ST0_CM 0x00080000 +#define ST0_ISC 0x00010000 +#define ST0_SWC 0x00020000 +#define ST0_CM 0x00080000 /* * Bits specific to the R4640/R4650 */ -#define ST0_UM (_ULCAST_(1) << 4) -#define ST0_IL (_ULCAST_(1) << 23) -#define ST0_DL (_ULCAST_(1) << 24) +#define ST0_UM (_ULCAST_(1) << 4) +#define ST0_IL (_ULCAST_(1) << 23) +#define ST0_DL (_ULCAST_(1) << 24) /* * Status register bits available in all MIPS CPUs. */ -#define ST0_IM 0x0000ff00 -#define STATUSB_IP0 8 -#define STATUSF_IP0 (_ULCAST_(1) << 8) -#define STATUSB_IP1 9 -#define STATUSF_IP1 (_ULCAST_(1) << 9) -#define STATUSB_IP2 10 -#define STATUSF_IP2 (_ULCAST_(1) << 10) -#define STATUSB_IP3 11 -#define STATUSF_IP3 (_ULCAST_(1) << 11) -#define STATUSB_IP4 12 -#define STATUSF_IP4 (_ULCAST_(1) << 12) -#define STATUSB_IP5 13 -#define STATUSF_IP5 (_ULCAST_(1) << 13) -#define STATUSB_IP6 14 -#define STATUSF_IP6 (_ULCAST_(1) << 14) -#define STATUSB_IP7 15 -#define STATUSF_IP7 (_ULCAST_(1) << 15) -#define STATUSB_IP8 0 -#define STATUSF_IP8 (_ULCAST_(1) << 0) -#define STATUSB_IP9 1 -#define STATUSF_IP9 (_ULCAST_(1) << 1) -#define STATUSB_IP10 2 -#define STATUSF_IP10 (_ULCAST_(1) << 2) -#define STATUSB_IP11 3 -#define STATUSF_IP11 (_ULCAST_(1) << 3) -#define STATUSB_IP12 4 -#define STATUSF_IP12 (_ULCAST_(1) << 4) -#define STATUSB_IP13 5 -#define STATUSF_IP13 (_ULCAST_(1) << 5) -#define STATUSB_IP14 6 -#define STATUSF_IP14 (_ULCAST_(1) << 6) -#define STATUSB_IP15 7 -#define STATUSF_IP15 (_ULCAST_(1) << 7) -#define ST0_CH 0x00040000 -#define ST0_SR 0x00100000 -#define ST0_TS 0x00200000 -#define ST0_BEV 0x00400000 -#define ST0_RE 0x02000000 -#define ST0_FR 0x04000000 -#define ST0_CU 0xf0000000 -#define ST0_CU0 0x10000000 -#define ST0_CU1 0x20000000 -#define ST0_CU1_SHIFT 29 -#define ST0_CU2 0x40000000 -#define ST0_CU3 0x80000000 -#define ST0_XX 0x80000000 /* MIPS IV naming */ +#define ST0_IM 0x0000ff00 +#define STATUSB_IP0 8 +#define STATUSF_IP0 (_ULCAST_(1) << 8) +#define STATUSB_IP1 9 +#define STATUSF_IP1 (_ULCAST_(1) << 9) +#define STATUSB_IP2 10 +#define STATUSF_IP2 (_ULCAST_(1) << 10) +#define STATUSB_IP3 11 +#define STATUSF_IP3 (_ULCAST_(1) << 11) +#define STATUSB_IP4 12 +#define STATUSF_IP4 (_ULCAST_(1) << 12) +#define STATUSB_IP5 13 +#define STATUSF_IP5 (_ULCAST_(1) << 13) +#define STATUSB_IP6 14 +#define STATUSF_IP6 (_ULCAST_(1) << 14) +#define STATUSB_IP7 15 +#define STATUSF_IP7 (_ULCAST_(1) << 15) +#define STATUSB_IP8 0 +#define STATUSF_IP8 (_ULCAST_(1) << 0) +#define STATUSB_IP9 1 +#define STATUSF_IP9 (_ULCAST_(1) << 1) +#define STATUSB_IP10 2 +#define STATUSF_IP10 (_ULCAST_(1) << 2) +#define STATUSB_IP11 3 +#define STATUSF_IP11 (_ULCAST_(1) << 3) +#define STATUSB_IP12 4 +#define STATUSF_IP12 (_ULCAST_(1) << 4) +#define STATUSB_IP13 5 +#define STATUSF_IP13 (_ULCAST_(1) << 5) +#define STATUSB_IP14 6 +#define STATUSF_IP14 (_ULCAST_(1) << 6) +#define STATUSB_IP15 7 +#define STATUSF_IP15 (_ULCAST_(1) << 7) +#define ST0_CH 0x00040000 +#define ST0_SR 0x00100000 +#define ST0_TS 0x00200000 +#define ST0_BEV 0x00400000 +#define ST0_RE 0x02000000 +#define ST0_FR 0x04000000 +#define ST0_CU 0xf0000000 +#define ST0_CU0 0x10000000 +#define ST0_CU1 0x20000000 +#define ST0_CU1_SHIFT 29 +#define ST0_CU2 0x40000000 +#define ST0_CU3 0x80000000 +#define ST0_XX 0x80000000 /* MIPS IV naming */ /* * Bitfields and bit numbers in the coprocessor 0 cause register. * * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. */ -#define CAUSEB_EXCCODE 2 -#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) -#define CAUSEB_IP 8 -#define CAUSEF_IP (_ULCAST_(255) << 8) -#define CAUSEB_IP0 8 -#define CAUSEF_IP0 (_ULCAST_(1) << 8) -#define CAUSEB_IP1 9 -#define CAUSEF_IP1 (_ULCAST_(1) << 9) -#define CAUSEB_IP2 10 -#define CAUSEF_IP2 (_ULCAST_(1) << 10) -#define CAUSEB_IP3 11 -#define CAUSEF_IP3 (_ULCAST_(1) << 11) -#define CAUSEB_IP4 12 -#define CAUSEF_IP4 (_ULCAST_(1) << 12) -#define CAUSEB_IP5 13 -#define CAUSEF_IP5 (_ULCAST_(1) << 13) -#define CAUSEB_IP6 14 -#define CAUSEF_IP6 (_ULCAST_(1) << 14) -#define CAUSEB_IP7 15 -#define CAUSEF_IP7 (_ULCAST_(1) << 15) -#define CAUSEB_IV 23 -#define CAUSEF_IV (_ULCAST_(1) << 23) -#define CAUSEB_CE 28 -#define CAUSEF_CE (_ULCAST_(3) << 28) -#define CAUSEB_BD 31 -#define CAUSEF_BD (_ULCAST_(1) << 31) +#define CAUSEB_EXCCODE 2 +#define CAUSEF_EXCCODE (_ULCAST_(31) << 2) +#define CAUSEB_IP 8 +#define CAUSEF_IP (_ULCAST_(255) << 8) +#define CAUSEB_IP0 8 +#define CAUSEF_IP0 (_ULCAST_(1) << 8) +#define CAUSEB_IP1 9 +#define CAUSEF_IP1 (_ULCAST_(1) << 9) +#define CAUSEB_IP2 10 +#define CAUSEF_IP2 (_ULCAST_(1) << 10) +#define CAUSEB_IP3 11 +#define CAUSEF_IP3 (_ULCAST_(1) << 11) +#define CAUSEB_IP4 12 +#define CAUSEF_IP4 (_ULCAST_(1) << 12) +#define CAUSEB_IP5 13 +#define CAUSEF_IP5 (_ULCAST_(1) << 13) +#define CAUSEB_IP6 14 +#define CAUSEF_IP6 (_ULCAST_(1) << 14) +#define CAUSEB_IP7 15 +#define CAUSEF_IP7 (_ULCAST_(1) << 15) +#define CAUSEB_IV 23 +#define CAUSEF_IV (_ULCAST_(1) << 23) +#define CAUSEB_CE 28 +#define CAUSEF_CE (_ULCAST_(3) << 28) +#define CAUSEB_BD 31 +#define CAUSEF_BD (_ULCAST_(1) << 31) /* * Bits in the coprocessor 0 config register. */ /* Generic bits. */ -#define CONF_CM_CACHABLE_NO_WA 0 -#define CONF_CM_CACHABLE_WA 1 -#define CONF_CM_UNCACHED 2 -#define CONF_CM_CACHABLE_NONCOHERENT 3 -#define CONF_CM_CACHABLE_CE 4 -#define CONF_CM_CACHABLE_COW 5 -#define CONF_CM_CACHABLE_CUW 6 -#define CONF_CM_CACHABLE_ACCELERATED 7 -#define CONF_CM_CMASK 7 -#define CONF_BE (_ULCAST_(1) << 15) +#define CONF_CM_CACHABLE_NO_WA 0 +#define CONF_CM_CACHABLE_WA 1 +#define CONF_CM_UNCACHED 2 +#define CONF_CM_CACHABLE_NONCOHERENT 3 +#define CONF_CM_CACHABLE_CE 4 +#define CONF_CM_CACHABLE_COW 5 +#define CONF_CM_CACHABLE_CUW 6 +#define CONF_CM_CACHABLE_ACCELERATED 7 +#define CONF_CM_CMASK 7 +#define CONF_BE (_ULCAST_(1) << 15) /* Bits common to various processors. */ -#define CONF_CU (_ULCAST_(1) << 3) -#define CONF_DB (_ULCAST_(1) << 4) -#define CONF_IB (_ULCAST_(1) << 5) -#define CONF_DC (_ULCAST_(7) << 6) -#define CONF_IC (_ULCAST_(7) << 9) -#define CONF_EB (_ULCAST_(1) << 13) -#define CONF_EM (_ULCAST_(1) << 14) -#define CONF_SM (_ULCAST_(1) << 16) -#define CONF_SC (_ULCAST_(1) << 17) -#define CONF_EW (_ULCAST_(3) << 18) -#define CONF_EP (_ULCAST_(15)<< 24) -#define CONF_EC (_ULCAST_(7) << 28) -#define CONF_CM (_ULCAST_(1) << 31) +#define CONF_CU (_ULCAST_(1) << 3) +#define CONF_DB (_ULCAST_(1) << 4) +#define CONF_IB (_ULCAST_(1) << 5) +#define CONF_DC (_ULCAST_(7) << 6) +#define CONF_IC (_ULCAST_(7) << 9) +#define CONF_EB (_ULCAST_(1) << 13) +#define CONF_EM (_ULCAST_(1) << 14) +#define CONF_SM (_ULCAST_(1) << 16) +#define CONF_SC (_ULCAST_(1) << 17) +#define CONF_EW (_ULCAST_(3) << 18) +#define CONF_EP (_ULCAST_(15)<< 24) +#define CONF_EC (_ULCAST_(7) << 28) +#define CONF_CM (_ULCAST_(1) << 31) /* Bits specific to the R4xx0. */ -#define R4K_CONF_SW (_ULCAST_(1) << 20) -#define R4K_CONF_SS (_ULCAST_(1) << 21) -#define R4K_CONF_SB (_ULCAST_(3) << 22) +#define R4K_CONF_SW (_ULCAST_(1) << 20) +#define R4K_CONF_SS (_ULCAST_(1) << 21) +#define R4K_CONF_SB (_ULCAST_(3) << 22) /* Bits specific to the R5000. */ -#define R5K_CONF_SE (_ULCAST_(1) << 12) -#define R5K_CONF_SS (_ULCAST_(3) << 20) +#define R5K_CONF_SE (_ULCAST_(1) << 12) +#define R5K_CONF_SS (_ULCAST_(3) << 20) /* Bits specific to the R10000. */ -#define R10K_CONF_DN (_ULCAST_(3) << 3) -#define R10K_CONF_CT (_ULCAST_(1) << 5) -#define R10K_CONF_PE (_ULCAST_(1) << 6) -#define R10K_CONF_PM (_ULCAST_(3) << 7) -#define R10K_CONF_EC (_ULCAST_(15)<< 9) -#define R10K_CONF_SB (_ULCAST_(1) << 13) -#define R10K_CONF_SK (_ULCAST_(1) << 14) -#define R10K_CONF_SS (_ULCAST_(7) << 16) -#define R10K_CONF_SC (_ULCAST_(7) << 19) -#define R10K_CONF_DC (_ULCAST_(7) << 26) -#define R10K_CONF_IC (_ULCAST_(7) << 29) +#define R10K_CONF_DN (_ULCAST_(3) << 3) +#define R10K_CONF_CT (_ULCAST_(1) << 5) +#define R10K_CONF_PE (_ULCAST_(1) << 6) +#define R10K_CONF_PM (_ULCAST_(3) << 7) +#define R10K_CONF_EC (_ULCAST_(15)<< 9) +#define R10K_CONF_SB (_ULCAST_(1) << 13) +#define R10K_CONF_SK (_ULCAST_(1) << 14) +#define R10K_CONF_SS (_ULCAST_(7) << 16) +#define R10K_CONF_SC (_ULCAST_(7) << 19) +#define R10K_CONF_DC (_ULCAST_(7) << 26) +#define R10K_CONF_IC (_ULCAST_(7) << 29) /* Bits specific to the VR41xx. */ -#define VR41_CONF_CS (_ULCAST_(1) << 12) -#define VR41_CONF_M16 (_ULCAST_(1) << 20) -#define VR41_CONF_AD (_ULCAST_(1) << 23) +#define VR41_CONF_CS (_ULCAST_(1) << 12) +#define VR41_CONF_M16 (_ULCAST_(1) << 20) +#define VR41_CONF_AD (_ULCAST_(1) << 23) /* Bits specific to the R30xx. */ -#define R30XX_CONF_FDM (_ULCAST_(1) << 19) -#define R30XX_CONF_REV (_ULCAST_(1) << 22) -#define R30XX_CONF_AC (_ULCAST_(1) << 23) -#define R30XX_CONF_RF (_ULCAST_(1) << 24) -#define R30XX_CONF_HALT (_ULCAST_(1) << 25) -#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) -#define R30XX_CONF_DBR (_ULCAST_(1) << 29) -#define R30XX_CONF_SB (_ULCAST_(1) << 30) -#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) +#define R30XX_CONF_FDM (_ULCAST_(1) << 19) +#define R30XX_CONF_REV (_ULCAST_(1) << 22) +#define R30XX_CONF_AC (_ULCAST_(1) << 23) +#define R30XX_CONF_RF (_ULCAST_(1) << 24) +#define R30XX_CONF_HALT (_ULCAST_(1) << 25) +#define R30XX_CONF_FPINT (_ULCAST_(7) << 26) +#define R30XX_CONF_DBR (_ULCAST_(1) << 29) +#define R30XX_CONF_SB (_ULCAST_(1) << 30) +#define R30XX_CONF_LOCK (_ULCAST_(1) << 31) /* Bits specific to the TX49. */ -#define TX49_CONF_DC (_ULCAST_(1) << 16) -#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ -#define TX49_CONF_HALT (_ULCAST_(1) << 18) -#define TX49_CONF_CWFON (_ULCAST_(1) << 27) +#define TX49_CONF_DC (_ULCAST_(1) << 16) +#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ +#define TX49_CONF_HALT (_ULCAST_(1) << 18) +#define TX49_CONF_CWFON (_ULCAST_(1) << 27) /* Bits specific to the MIPS32/64 PRA. */ -#define MIPS_CONF_MT (_ULCAST_(7) << 7) -#define MIPS_CONF_AR (_ULCAST_(7) << 10) -#define MIPS_CONF_AT (_ULCAST_(3) << 13) -#define MIPS_CONF_M (_ULCAST_(1) << 31) +#define MIPS_CONF_MT (_ULCAST_(7) << 7) +#define MIPS_CONF_AR (_ULCAST_(7) << 10) +#define MIPS_CONF_AT (_ULCAST_(3) << 13) +#define MIPS_CONF_M (_ULCAST_(1) << 31) /* * R10000 performance counter definitions. @@ -604,50 +604,50 @@ /* * Events counted by counter #0 */ -#define CE0_CYCLES 0 -#define CE0_INSN_ISSUED 1 -#define CE0_LPSC_ISSUED 2 -#define CE0_S_ISSUED 3 -#define CE0_SC_ISSUED 4 -#define CE0_SC_FAILED 5 -#define CE0_BRANCH_DECODED 6 -#define CE0_QW_WB_SECONDARY 7 -#define CE0_CORRECTED_ECC_ERRORS 8 -#define CE0_ICACHE_MISSES 9 -#define CE0_SCACHE_I_MISSES 10 -#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 -#define CE0_EXT_INTERVENTIONS_REQ 12 -#define CE0_EXT_INVALIDATE_REQ 13 -#define CE0_VIRTUAL_COHERENCY_COND 14 -#define CE0_INSN_GRADUATED 15 +#define CE0_CYCLES 0 +#define CE0_INSN_ISSUED 1 +#define CE0_LPSC_ISSUED 2 +#define CE0_S_ISSUED 3 +#define CE0_SC_ISSUED 4 +#define CE0_SC_FAILED 5 +#define CE0_BRANCH_DECODED 6 +#define CE0_QW_WB_SECONDARY 7 +#define CE0_CORRECTED_ECC_ERRORS 8 +#define CE0_ICACHE_MISSES 9 +#define CE0_SCACHE_I_MISSES 10 +#define CE0_SCACHE_I_WAY_MISSPREDICTED 11 +#define CE0_EXT_INTERVENTIONS_REQ 12 +#define CE0_EXT_INVALIDATE_REQ 13 +#define CE0_VIRTUAL_COHERENCY_COND 14 +#define CE0_INSN_GRADUATED 15 /* * Events counted by counter #1 */ -#define CE1_CYCLES 0 -#define CE1_INSN_GRADUATED 1 -#define CE1_LPSC_GRADUATED 2 -#define CE1_S_GRADUATED 3 -#define CE1_SC_GRADUATED 4 -#define CE1_FP_INSN_GRADUATED 5 -#define CE1_QW_WB_PRIMARY 6 -#define CE1_TLB_REFILL 7 -#define CE1_BRANCH_MISSPREDICTED 8 -#define CE1_DCACHE_MISS 9 -#define CE1_SCACHE_D_MISSES 10 -#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 -#define CE1_EXT_INTERVENTION_HITS 12 -#define CE1_EXT_INVALIDATE_REQ 13 -#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 -#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 +#define CE1_CYCLES 0 +#define CE1_INSN_GRADUATED 1 +#define CE1_LPSC_GRADUATED 2 +#define CE1_S_GRADUATED 3 +#define CE1_SC_GRADUATED 4 +#define CE1_FP_INSN_GRADUATED 5 +#define CE1_QW_WB_PRIMARY 6 +#define CE1_TLB_REFILL 7 +#define CE1_BRANCH_MISSPREDICTED 8 +#define CE1_DCACHE_MISS 9 +#define CE1_SCACHE_D_MISSES 10 +#define CE1_SCACHE_D_WAY_MISSPREDICTED 11 +#define CE1_EXT_INTERVENTION_HITS 12 +#define CE1_EXT_INVALIDATE_REQ 13 +#define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14 +#define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15 /* * These flags define in which priviledge mode the counters count events */ -#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ -#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ -#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ -#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ +#define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */ +#define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */ +#define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */ +#define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */ #ifndef __ASSEMBLY__ @@ -685,275 +685,275 @@ * Macros to access the system control coprocessor */ -#define __read_32bit_c0_register(source, sel) \ -({ int __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mfc0\t%0, " #source "\n\t" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0\n\t" \ - : "=r" (__res)); \ - __res; \ +#define __read_32bit_c0_register(source, sel) \ +({ int __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0\n\t" \ + : "=r" (__res)); \ + __res; \ }) -#define __read_64bit_c0_register(source, sel) \ -({ unsigned long __res; \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmfc0\t%0, " #source "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : "=r" (__res)); \ - __res; \ +#define __read_64bit_c0_register(source, sel) \ +({ unsigned long __res; \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmfc0\t%0, " #source "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : "=r" (__res)); \ + __res; \ }) -#define __write_32bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - "mtc0\t%z0, " #register "\n\t" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips32\n\t" \ - "mtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ +#define __write_32bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + "mtc0\t%z0, " #register "\n\t" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips32\n\t" \ + "mtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ } while (0) -#define __write_64bit_c0_register(register, sel, value) \ -do { \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips3\n\t" \ - "dmtc0\t%z0, " #register "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmtc0\t%z0, " #register ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "Jr" (value)); \ +#define __write_64bit_c0_register(register, sel, value) \ +do { \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips3\n\t" \ + "dmtc0\t%z0, " #register "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmtc0\t%z0, " #register ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "Jr" (value)); \ } while (0) -#define __read_ulong_c0_register(reg, sel) \ - ((sizeof(unsigned long) == 4) ? \ - __read_32bit_c0_register(reg, sel) : \ +#define __read_ulong_c0_register(reg, sel) \ + ((sizeof(unsigned long) == 4) ? \ + __read_32bit_c0_register(reg, sel) : \ __read_64bit_c0_register(reg, sel)) -#define __write_ulong_c0_register(reg, sel, val) \ -do { \ - if (sizeof(unsigned long) == 4) \ - __write_32bit_c0_register(reg, sel, val); \ - else \ - __write_64bit_c0_register(reg, sel, val); \ +#define __write_ulong_c0_register(reg, sel, val) \ +do { \ + if (sizeof(unsigned long) == 4) \ + __write_32bit_c0_register(reg, sel, val); \ + else \ + __write_64bit_c0_register(reg, sel, val); \ } while (0) /* * These versions are only needed for systems with more than 38 bits of * physical address space running the 32-bit kernel. That's none atm :-) */ -#define __read_64bit_c0_split(source, sel) \ -({ \ - unsigned long long val; \ - unsigned long flags; \ +#define __read_64bit_c0_split(source, sel) \ +({ \ + unsigned long long val; \ + unsigned long flags; \ \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dmfc0\t%M0, " #source ", " #sel "\n\t" \ - "dsll\t%L0, %M0, 32\n\t" \ - "dsrl\t%M0, %M0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - ".set\tmips0" \ - : "=r" (val)); \ - local_irq_restore(flags); \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dmfc0\t%M0, " #source ", " #sel "\n\t" \ + "dsll\t%L0, %M0, 32\n\t" \ + "dsrl\t%M0, %M0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + ".set\tmips0" \ + : "=r" (val)); \ + local_irq_restore(flags); \ \ - val; \ + val; \ }) -#define __write_64bit_c0_split(source, sel, val) \ -do { \ - unsigned long flags; \ +#define __write_64bit_c0_split(source, sel, val) \ +do { \ + unsigned long flags; \ \ - local_irq_save(flags); \ - if (sel == 0) \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - else \ - __asm__ __volatile__( \ - ".set\tmips64\n\t" \ - "dsll\t%L0, %L0, 32\n\t" \ - "dsrl\t%L0, %L0, 32\n\t" \ - "dsll\t%M0, %M0, 32\n\t" \ - "or\t%L0, %L0, %M0\n\t" \ - "dmtc0\t%L0, " #source ", " #sel "\n\t" \ - ".set\tmips0" \ - : : "r" (val)); \ - local_irq_restore(flags); \ + local_irq_save(flags); \ + if (sel == 0) \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + else \ + __asm__ __volatile__( \ + ".set\tmips64\n\t" \ + "dsll\t%L0, %L0, 32\n\t" \ + "dsrl\t%L0, %L0, 32\n\t" \ + "dsll\t%M0, %M0, 32\n\t" \ + "or\t%L0, %L0, %M0\n\t" \ + "dmtc0\t%L0, " #source ", " #sel "\n\t" \ + ".set\tmips0" \ + : : "r" (val)); \ + local_irq_restore(flags); \ } while (0) -#define read_c0_index() __read_32bit_c0_register($0, 0) -#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) +#define read_c0_index() __read_32bit_c0_register($0, 0) +#define write_c0_index(val) __write_32bit_c0_register($0, 0, val) -#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) -#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) +#define read_c0_entrylo0() __read_ulong_c0_register($2, 0) +#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) -#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) -#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) +#define read_c0_entrylo1() __read_ulong_c0_register($3, 0) +#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) -#define read_c0_conf() __read_32bit_c0_register($3, 0) -#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) +#define read_c0_conf() __read_32bit_c0_register($3, 0) +#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) -#define read_c0_context() __read_ulong_c0_register($4, 0) -#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) +#define read_c0_context() __read_ulong_c0_register($4, 0) +#define write_c0_context(val) __write_ulong_c0_register($4, 0, val) -#define read_c0_pagemask() __read_32bit_c0_register($5, 0) -#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) +#define read_c0_pagemask() __read_32bit_c0_register($5, 0) +#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) -#define read_c0_wired() __read_32bit_c0_register($6, 0) -#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) +#define read_c0_wired() __read_32bit_c0_register($6, 0) +#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) -#define read_c0_info() __read_32bit_c0_register($7, 0) +#define read_c0_info() __read_32bit_c0_register($7, 0) -#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ -#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) +#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ +#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) -#define read_c0_count() __read_32bit_c0_register($9, 0) -#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) +#define read_c0_count() __read_32bit_c0_register($9, 0) +#define write_c0_count(val) __write_32bit_c0_register($9, 0, val) -#define read_c0_entryhi() __read_ulong_c0_register($10, 0) -#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) +#define read_c0_entryhi() __read_ulong_c0_register($10, 0) +#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) -#define read_c0_compare() __read_32bit_c0_register($11, 0) -#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) +#define read_c0_compare() __read_32bit_c0_register($11, 0) +#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) -#define read_c0_status() __read_32bit_c0_register($12, 0) -#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) +#define read_c0_status() __read_32bit_c0_register($12, 0) +#define write_c0_status(val) __write_32bit_c0_register($12, 0, val) -#define read_c0_cause() __read_32bit_c0_register($13, 0) -#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) +#define read_c0_cause() __read_32bit_c0_register($13, 0) +#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) -#define read_c0_prid() __read_32bit_c0_register($15, 0) +#define read_c0_prid() __read_32bit_c0_register($15, 0) -#define read_c0_ebase() __read_32bit_c0_register($15, 1) -#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) +#define read_c0_ebase() __read_32bit_c0_register($15, 1) +#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) -#define read_c0_config() __read_32bit_c0_register($16, 0) -#define read_c0_config1() __read_32bit_c0_register($16, 1) -#define read_c0_config2() __read_32bit_c0_register($16, 2) -#define read_c0_config3() __read_32bit_c0_register($16, 3) -#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) -#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) -#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) -#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) +#define read_c0_config() __read_32bit_c0_register($16, 0) +#define read_c0_config1() __read_32bit_c0_register($16, 1) +#define read_c0_config2() __read_32bit_c0_register($16, 2) +#define read_c0_config3() __read_32bit_c0_register($16, 3) +#define write_c0_config(val) __write_32bit_c0_register($16, 0, val) +#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) +#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) +#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) /* * The WatchLo register. There may be upto 8 of them. */ -#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) -#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) -#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) -#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) -#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) -#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) -#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) -#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) -#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) -#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) -#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) -#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) -#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) -#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) -#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) -#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) +#define read_c0_watchlo0() __read_ulong_c0_register($18, 0) +#define read_c0_watchlo1() __read_ulong_c0_register($18, 1) +#define read_c0_watchlo2() __read_ulong_c0_register($18, 2) +#define read_c0_watchlo3() __read_ulong_c0_register($18, 3) +#define read_c0_watchlo4() __read_ulong_c0_register($18, 4) +#define read_c0_watchlo5() __read_ulong_c0_register($18, 5) +#define read_c0_watchlo6() __read_ulong_c0_register($18, 6) +#define read_c0_watchlo7() __read_ulong_c0_register($18, 7) +#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) +#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) +#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) +#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) +#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) +#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) +#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) +#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) /* * The WatchHi register. There may be upto 8 of them. */ -#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) -#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) -#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) -#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) -#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) -#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) -#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) -#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) +#define read_c0_watchhi0() __read_32bit_c0_register($19, 0) +#define read_c0_watchhi1() __read_32bit_c0_register($19, 1) +#define read_c0_watchhi2() __read_32bit_c0_register($19, 2) +#define read_c0_watchhi3() __read_32bit_c0_register($19, 3) +#define read_c0_watchhi4() __read_32bit_c0_register($19, 4) +#define read_c0_watchhi5() __read_32bit_c0_register($19, 5) +#define read_c0_watchhi6() __read_32bit_c0_register($19, 6) +#define read_c0_watchhi7() __read_32bit_c0_register($19, 7) -#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) -#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) -#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) -#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) -#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) -#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) -#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) -#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) +#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) +#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) +#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) +#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) +#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) +#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) +#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) +#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) -#define read_c0_xcontext() __read_ulong_c0_register($20, 0) -#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) +#define read_c0_xcontext() __read_ulong_c0_register($20, 0) +#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) -#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) +#define read_c0_intcontrol() __read_32bit_c0_register($20, 1) #define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val) -#define read_c0_framemask() __read_32bit_c0_register($21, 0) -#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) +#define read_c0_framemask() __read_32bit_c0_register($21, 0) +#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) -#define read_c0_debug() __read_32bit_c0_register($23, 0) -#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) +#define read_c0_debug() __read_32bit_c0_register($23, 0) +#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) -#define read_c0_depc() __read_ulong_c0_register($24, 0) -#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) +#define read_c0_depc() __read_ulong_c0_register($24, 0) +#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) -#define read_c0_ecc() __read_32bit_c0_register($26, 0) -#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) +#define read_c0_ecc() __read_32bit_c0_register($26, 0) +#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) -#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) -#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) +#define read_c0_derraddr0() __read_ulong_c0_register($26, 1) +#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) -#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) +#define read_c0_cacheerr() __read_32bit_c0_register($27, 0) -#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) -#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) +#define read_c0_derraddr1() __read_ulong_c0_register($27, 1) +#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) -#define read_c0_taglo() __read_32bit_c0_register($28, 0) -#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) +#define read_c0_taglo() __read_32bit_c0_register($28, 0) +#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) -#define read_c0_taghi() __read_32bit_c0_register($29, 0) -#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) +#define read_c0_taghi() __read_32bit_c0_register($29, 0) +#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) -#define read_c0_errorepc() __read_ulong_c0_register($30, 0) -#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) +#define read_c0_errorepc() __read_ulong_c0_register($30, 0) +#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) -#define read_c0_epc() __read_ulong_c0_register($14, 0) -#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) +#define read_c0_epc() __read_ulong_c0_register($14, 0) +#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) #if 1 /* @@ -962,20 +962,20 @@ do { \ #define read_32bit_cp0_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "mfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) #define read_32bit_cp0_set1_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "cfc0\t%0,"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) @@ -993,14 +993,14 @@ do { \ #define write_32bit_cp0_register(register,value) \ __asm__ __volatile__( \ - "mtc0\t%0,"STR(register)"\n\t" \ - "nop" \ + "mtc0\t%0,"STR(register)"\n\t" \ + "nop" \ : : "r" (value)); #define write_32bit_cp0_set1_register(register,value) \ __asm__ __volatile__( \ - "ctc0\t%0,$"STR(register)"\n\t" \ - "nop" \ + "ctc0\t%0,$"STR(register)"\n\t" \ + "nop" \ : : "r" (value)); #define write_64bit_cp0_register(register,value) \ @@ -1018,9 +1018,9 @@ do { \ __asm__ __volatile__( \ ".set\tnoreorder\n\t" \ ".set\tnoat\n\t" \ - "#.set\tmips64\n\t" \ - "#mfc0\t$1, $16, 1\n\t" \ - "#.set\tmips0\n\t" \ + "#.set\tmips64\n\t" \ + "#mfc0\t$1, $16, 1\n\t" \ + "#.set\tmips0\n\t" \ ".word\t0x40018001\n\t" \ "move\t%0,$1\n\t" \ ".set\tat\n\t" \ @@ -1035,17 +1035,17 @@ do { \ #define read_32bit_cp1_register(source) \ ({ int __res; \ __asm__ __volatile__( \ - ".set\tpush\n\t" \ - ".set\treorder\n\t" \ + ".set\tpush\n\t" \ + ".set\treorder\n\t" \ "cfc1\t%0,$"STR(source)"\n\t" \ - ".set\tpop" \ + ".set\tpop" \ : "=r" (__res)); \ __res;}) #define write_32bit_cp1_register(register,value) \ __asm__ __volatile__( \ - "ctc1\t%0,$"STR(register)"\n\t" \ - "nop" \ + "ctc1\t%0,$"STR(register)"\n\t" \ + "nop" \ : : "r" (value)); /* TLB operations. */ @@ -1084,62 +1084,62 @@ static inline void tlb_write_random(void) /* * Manipulate bits in a c0 register. */ -#define __BUILD_SET_C0(name,register) \ -static inline unsigned int \ -set_c0_##name(unsigned int set) \ -{ \ - unsigned int res; \ +#define __BUILD_SET_C0(name,register) \ +static inline unsigned int \ +set_c0_##name(unsigned int set) \ +{ \ + unsigned int res; \ \ - res = read_c0_##name(); \ - res |= set; \ - write_c0_##name(res); \ + res = read_c0_##name(); \ + res |= set; \ + write_c0_##name(res); \ \ - return res; \ -} \ + return res; \ +} \ \ -static inline unsigned int \ -clear_c0_##name(unsigned int clear) \ -{ \ - unsigned int res; \ +static inline unsigned int \ +clear_c0_##name(unsigned int clear) \ +{ \ + unsigned int res; \ \ - res = read_c0_##name(); \ - res &= ~clear; \ - write_c0_##name(res); \ + res = read_c0_##name(); \ + res &= ~clear; \ + write_c0_##name(res); \ \ - return res; \ -} \ + return res; \ +} \ \ -static inline unsigned int \ -change_c0_##name(unsigned int change, unsigned int new) \ -{ \ - unsigned int res; \ +static inline unsigned int \ +change_c0_##name(unsigned int change, unsigned int new) \ +{ \ + unsigned int res; \ \ - res = read_c0_##name(); \ - res &= ~change; \ - res |= (new & change); \ - write_c0_##name(res); \ + res = read_c0_##name(); \ + res &= ~change; \ + res |= (new & change); \ + write_c0_##name(res); \ \ - return res; \ + return res; \ } __BUILD_SET_C0(status,CP0_STATUS) __BUILD_SET_C0(cause,CP0_CAUSE) __BUILD_SET_C0(config,CP0_CONFIG) -#define set_cp0_status(x) set_c0_status(x) -#define set_cp0_cause(x) set_c0_cause(x) -#define set_cp0_config(x) set_c0_config(x) +#define set_cp0_status(x) set_c0_status(x) +#define set_cp0_cause(x) set_c0_cause(x) +#define set_cp0_config(x) set_c0_config(x) -#define read_c1_status() read_32bit_cp1_register(31) -#define write_c1_status(x) write_32bit_cp1_register(31, x) +#define read_c1_status() read_32bit_cp1_register(31) +#define write_c1_status(x) write_32bit_cp1_register(31, x) -#define readb(reg) (*((volatile unsigned char *) (reg))) -#define readw(reg) (*((volatile unsigned short *) (reg))) -#define readl(reg) (*((volatile unsigned int *) (reg))) +#define readb(reg) (*((volatile unsigned char *) (reg))) +#define readw(reg) (*((volatile unsigned short *) (reg))) +#define readl(reg) (*((volatile unsigned int *) (reg))) -#define writeb(data, reg) ((*((volatile unsigned char *)(reg))) = (unsigned char)(data)) -#define writew(data, reg) ((*((volatile unsigned short *)(reg))) = (unsigned short)(data)) -#define writel(data, reg) ((*((volatile unsigned int *)(reg))) = (unsigned int)(data)) +#define writeb(data, reg) ((*((volatile unsigned char *)(reg))) = (unsigned char)(data)) +#define writew(data, reg) ((*((volatile unsigned short *)(reg))) = (unsigned short)(data)) +#define writel(data, reg) ((*((volatile unsigned int *)(reg))) = (unsigned int)(data)) #endif /* !__ASSEMBLY__ */ diff --git a/libcpu/mips/common/mips_types.h b/libcpu/mips/common/mips_types.h index cc12d44391..466a39a40b 100644 --- a/libcpu/mips/common/mips_types.h +++ b/libcpu/mips/common/mips_types.h @@ -1,21 +1,7 @@ /* - * File : mips_types.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/libcpu/mips/common/ptrace.h b/libcpu/mips/common/ptrace.h index 00ce58a085..8b82cca5d6 100644 --- a/libcpu/mips/common/ptrace.h +++ b/libcpu/mips/common/ptrace.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -23,9 +23,9 @@ #include <rtthread.h> struct mips_fpu_struct { - rt_uint64_t fpr[NUM_FPU_REGS]; - rt_uint32_t fcr31; - rt_uint32_t pad; + rt_uint64_t fpr[NUM_FPU_REGS]; + rt_uint32_t fcr31; + rt_uint32_t pad; }; struct pt_regs { @@ -68,53 +68,53 @@ struct pt_regs { /* Note: For call stack o32 ABI has 0x8 shadowsoace Here */ #ifdef ARCH_MIPS64 -#define PT_R0 (0x0 * LONGSIZE) /* 0 */ +#define PT_R0 (0x0 * LONGSIZE) /* 0 */ #else -#define PT_R0 (0x8 * LONGSIZE) /* 0 */ +#define PT_R0 (0x8 * LONGSIZE) /* 0 */ #endif -#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ -#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ -#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ -#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */ -#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */ -#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */ -#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */ -#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */ -#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */ -#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */ -#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */ -#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */ -#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */ -#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */ -#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */ -#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */ -#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */ -#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */ -#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */ -#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */ -#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */ -#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */ -#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */ -#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */ -#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */ -#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */ -#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */ -#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */ -#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */ -#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */ -#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */ +#define PT_R1 ((PT_R0) + LONGSIZE) /* 1 */ +#define PT_R2 ((PT_R1) + LONGSIZE) /* 2 */ +#define PT_R3 ((PT_R2) + LONGSIZE) /* 3 */ +#define PT_R4 ((PT_R3) + LONGSIZE) /* 4 */ +#define PT_R5 ((PT_R4) + LONGSIZE) /* 5 */ +#define PT_R6 ((PT_R5) + LONGSIZE) /* 6 */ +#define PT_R7 ((PT_R6) + LONGSIZE) /* 7 */ +#define PT_R8 ((PT_R7) + LONGSIZE) /* 8 */ +#define PT_R9 ((PT_R8) + LONGSIZE) /* 9 */ +#define PT_R10 ((PT_R9) + LONGSIZE) /* 10 */ +#define PT_R11 ((PT_R10) + LONGSIZE) /* 11 */ +#define PT_R12 ((PT_R11) + LONGSIZE) /* 12 */ +#define PT_R13 ((PT_R12) + LONGSIZE) /* 13 */ +#define PT_R14 ((PT_R13) + LONGSIZE) /* 14 */ +#define PT_R15 ((PT_R14) + LONGSIZE) /* 15 */ +#define PT_R16 ((PT_R15) + LONGSIZE) /* 16 */ +#define PT_R17 ((PT_R16) + LONGSIZE) /* 17 */ +#define PT_R18 ((PT_R17) + LONGSIZE) /* 18 */ +#define PT_R19 ((PT_R18) + LONGSIZE) /* 19 */ +#define PT_R20 ((PT_R19) + LONGSIZE) /* 20 */ +#define PT_R21 ((PT_R20) + LONGSIZE) /* 21 */ +#define PT_R22 ((PT_R21) + LONGSIZE) /* 22 */ +#define PT_R23 ((PT_R22) + LONGSIZE) /* 23 */ +#define PT_R24 ((PT_R23) + LONGSIZE) /* 24 */ +#define PT_R25 ((PT_R24) + LONGSIZE) /* 25 */ +#define PT_R26 ((PT_R25) + LONGSIZE) /* 26 */ +#define PT_R27 ((PT_R26) + LONGSIZE) /* 27 */ +#define PT_R28 ((PT_R27) + LONGSIZE) /* 28 */ +#define PT_R29 ((PT_R28) + LONGSIZE) /* 29 */ +#define PT_R30 ((PT_R29) + LONGSIZE) /* 30 */ +#define PT_R31 ((PT_R30) + LONGSIZE) /* 31 */ /* * Saved special registers */ -#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ -#define PT_HI ((PT_STATUS) + HI_LO_SIZE) /* 33 */ -#define PT_LO ((PT_HI) + HI_LO_SIZE) /* 34 */ -#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ -#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ -#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ +#define PT_STATUS ((PT_R31) + LONGSIZE) /* 32 */ +#define PT_HI ((PT_STATUS) + HI_LO_SIZE) /* 33 */ +#define PT_LO ((PT_HI) + HI_LO_SIZE) /* 34 */ +#define PT_BADVADDR ((PT_LO) + LONGSIZE) /* 35 */ +#define PT_CAUSE ((PT_BADVADDR) + LONGSIZE) /* 36 */ +#define PT_EPC ((PT_CAUSE) + LONGSIZE) /* 37 */ -#define PT_REG_END ((PT_EPC) + LONGSIZE) /* Align already ensured manually */ +#define PT_REG_END ((PT_EPC) + LONGSIZE) /* Align already ensured manually */ #ifdef RT_USING_FPU #define PT_FPU_R0 (PT_REG_END) @@ -136,10 +136,10 @@ struct pt_regs { #define PT_FPU_FCSR31 ((PT_FPU_R30) + FP_REG_SIZE) #define PT_FPU_PAD0 ((PT_FPU_FCSR31) + 4) -#define PT_FPU_END ((PT_FPU_PAD0) + 4) -#define PT_SIZE PT_FPU_END +#define PT_FPU_END ((PT_FPU_PAD0) + 4) +#define PT_SIZE PT_FPU_END #else -#define PT_SIZE PT_REG_END +#define PT_SIZE PT_REG_END #endif -#endif
\ No newline at end of file +#endif diff --git a/libcpu/mips/common/stack.c b/libcpu/mips/common/stack.c index b933b184e7..3f9010837a 100644 --- a/libcpu/mips/common/stack.c +++ b/libcpu/mips/common/stack.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -47,15 +47,15 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad pt->regs[REG_FP] = (rt_ubase_t)0x0; pt->regs[REG_RA] = (rt_ubase_t)texit; - pt->hi = 0x0; - pt->lo = 0x0; + pt->hi = 0x0; + pt->lo = 0x0; pt->cp0_status = (ST0_IE | ST0_CU0 | ST0_IM); #ifdef RT_USING_FPU pt->cp0_status |= (ST0_CU1 | ST0_FR); #endif - pt->cp0_cause = read_c0_cause(); - pt->cp0_epc = (rt_ubase_t)tentry; - pt->cp0_badvaddr = 0x0; + pt->cp0_cause = read_c0_cause(); + pt->cp0_epc = (rt_ubase_t)tentry; + pt->cp0_badvaddr = 0x0; return stk; } diff --git a/libcpu/mips/common/stackframe.h b/libcpu/mips/common/stackframe.h index bb92a18c9c..ba361acd99 100644 --- a/libcpu/mips/common/stackframe.h +++ b/libcpu/mips/common/stackframe.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -51,69 +51,69 @@ .set pop .endm - .macro SAVE_AT - .set push - .set noat - LONG_S $1, PT_R1(sp) - .set pop + .macro SAVE_AT + .set push + .set noat + LONG_S $1, PT_R1(sp) + .set pop .endm - .macro SAVE_TEMP - mfhi v1 - LONG_S $8, PT_R8(sp) - LONG_S $9, PT_R9(sp) - sw v1, PT_HI(sp) - mflo v1 - LONG_S $10, PT_R10(sp) - LONG_S $11, PT_R11(sp) - sw v1, PT_LO(sp) - LONG_S $12, PT_R12(sp) - LONG_S $13, PT_R13(sp) - LONG_S $14, PT_R14(sp) - LONG_S $15, PT_R15(sp) - LONG_S $24, PT_R24(sp) + .macro SAVE_TEMP + mfhi v1 + LONG_S $8, PT_R8(sp) + LONG_S $9, PT_R9(sp) + sw v1, PT_HI(sp) + mflo v1 + LONG_S $10, PT_R10(sp) + LONG_S $11, PT_R11(sp) + sw v1, PT_LO(sp) + LONG_S $12, PT_R12(sp) + LONG_S $13, PT_R13(sp) + LONG_S $14, PT_R14(sp) + LONG_S $15, PT_R15(sp) + LONG_S $24, PT_R24(sp) .endm - .macro SAVE_STATIC - LONG_S $16, PT_R16(sp) - LONG_S $17, PT_R17(sp) - LONG_S $18, PT_R18(sp) - LONG_S $19, PT_R19(sp) - LONG_S $20, PT_R20(sp) - LONG_S $21, PT_R21(sp) - LONG_S $22, PT_R22(sp) - LONG_S $23, PT_R23(sp) - LONG_S $30, PT_R30(sp) + .macro SAVE_STATIC + LONG_S $16, PT_R16(sp) + LONG_S $17, PT_R17(sp) + LONG_S $18, PT_R18(sp) + LONG_S $19, PT_R19(sp) + LONG_S $20, PT_R20(sp) + LONG_S $21, PT_R21(sp) + LONG_S $22, PT_R22(sp) + LONG_S $23, PT_R23(sp) + LONG_S $30, PT_R30(sp) .endm - .macro SAVE_SOME - .set push - .set noat - .set reorder - move k1, sp - move k0, sp + .macro SAVE_SOME + .set push + .set noat + .set reorder + move k1, sp + move k0, sp PTR_SUBU sp, k1, PT_SIZE - LONG_S k0, PT_R29(sp) - LONG_S $3, PT_R3(sp) - LONG_S $0, PT_R0(sp) - MFC0 v1, CP0_STATUS - LONG_S $2, PT_R2(sp) - LONG_S v1, PT_STATUS(sp) - LONG_S $4, PT_R4(sp) - MFC0 v1, CP0_CAUSE - LONG_S $5, PT_R5(sp) - LONG_S v1, PT_CAUSE(sp) - LONG_S $6, PT_R6(sp) - MFC0 v1, CP0_EPC - LONG_S $7, PT_R7(sp) - LONG_S v1, PT_EPC(sp) - LONG_S $25, PT_R25(sp) - LONG_S $28, PT_R28(sp) - LONG_S $31, PT_R31(sp) - .set pop + LONG_S k0, PT_R29(sp) + LONG_S $3, PT_R3(sp) + LONG_S $0, PT_R0(sp) + MFC0 v1, CP0_STATUS + LONG_S $2, PT_R2(sp) + LONG_S v1, PT_STATUS(sp) + LONG_S $4, PT_R4(sp) + MFC0 v1, CP0_CAUSE + LONG_S $5, PT_R5(sp) + LONG_S v1, PT_CAUSE(sp) + LONG_S $6, PT_R6(sp) + MFC0 v1, CP0_EPC + LONG_S $7, PT_R7(sp) + LONG_S v1, PT_EPC(sp) + LONG_S $25, PT_R25(sp) + LONG_S $28, PT_R28(sp) + LONG_S $31, PT_R31(sp) + .set pop .endm - .macro SAVE_ALL + .macro SAVE_ALL SAVE_SOME SAVE_AT SAVE_TEMP @@ -155,86 +155,86 @@ .set pop .endm - .macro RESTORE_AT - .set push - .set noat - LONG_L $1, PT_R1(sp) - .set pop + .macro RESTORE_AT + .set push + .set noat + LONG_L $1, PT_R1(sp) + .set pop .endm - .macro RESTORE_TEMP - lw $24, PT_LO(sp) - LONG_L $8, PT_R8(sp) - LONG_L $9, PT_R9(sp) - mtlo $24 - lw $24, PT_HI(sp) - LONG_L $10, PT_R10(sp) - LONG_L $11, PT_R11(sp) - mthi $24 - LONG_L $12, PT_R12(sp) - LONG_L $13, PT_R13(sp) - LONG_L $14, PT_R14(sp) - LONG_L $15, PT_R15(sp) - LONG_L $24, PT_R24(sp) + .macro RESTORE_TEMP + lw $24, PT_LO(sp) + LONG_L $8, PT_R8(sp) + LONG_L $9, PT_R9(sp) + mtlo $24 + lw $24, PT_HI(sp) + LONG_L $10, PT_R10(sp) + LONG_L $11, PT_R11(sp) + mthi $24 + LONG_L $12, PT_R12(sp) + LONG_L $13, PT_R13(sp) + LONG_L $14, PT_R14(sp) + LONG_L $15, PT_R15(sp) + LONG_L $24, PT_R24(sp) .endm - .macro RESTORE_STATIC - LONG_L $16, PT_R16(sp) - LONG_L $17, PT_R17(sp) - LONG_L $18, PT_R18(sp) - LONG_L $19, PT_R19(sp) - LONG_L $20, PT_R20(sp) - LONG_L $21, PT_R21(sp) - LONG_L $22, PT_R22(sp) - LONG_L $23, PT_R23(sp) - LONG_L $30, PT_R30(sp) + .macro RESTORE_STATIC + LONG_L $16, PT_R16(sp) + LONG_L $17, PT_R17(sp) + LONG_L $18, PT_R18(sp) + LONG_L $19, PT_R19(sp) + LONG_L $20, PT_R20(sp) + LONG_L $21, PT_R21(sp) + LONG_L $22, PT_R22(sp) + LONG_L $23, PT_R23(sp) + LONG_L $30, PT_R30(sp) .endm #define STATMASK 0x1f - .macro RESTORE_SOME - .set push - .set reorder - .set noat - mfc0 a0, CP0_STATUS - ori a0, STATMASK - xori a0, STATMASK - mtc0 a0, CP0_STATUS - li v1, (ST0_CU1 | ST0_FR | ST0_IM) - and a0, v1, a0 - LONG_L v0, PT_STATUS(sp) - li v1, ~(ST0_CU1 | ST0_FR | ST0_IM) - and v0, v1 - or v0, a0 + .macro RESTORE_SOME + .set push + .set reorder + .set noat + mfc0 a0, CP0_STATUS + ori a0, STATMASK + xori a0, STATMASK + mtc0 a0, CP0_STATUS + li v1, (ST0_CU1 | ST0_FR | ST0_IM) + and a0, v1, a0 + LONG_L v0, PT_STATUS(sp) + li v1, ~(ST0_CU1 | ST0_FR | ST0_IM) + and v0, v1 + or v0, a0 li v1, (ST0_KX | ST0_SX | ST0_UX) or v0, v1 - mtc0 v0, CP0_STATUS - LONG_L v1, PT_EPC(sp) - MTC0 v1, CP0_EPC - LONG_L $31, PT_R31(sp) - LONG_L $28, PT_R28(sp) - LONG_L $25, PT_R25(sp) - LONG_L $7, PT_R7(sp) - LONG_L $6, PT_R6(sp) - LONG_L $5, PT_R5(sp) - LONG_L $4, PT_R4(sp) - LONG_L $3, PT_R3(sp) - LONG_L $2, PT_R2(sp) - .set pop + mtc0 v0, CP0_STATUS + LONG_L v1, PT_EPC(sp) + MTC0 v1, CP0_EPC + LONG_L $31, PT_R31(sp) + LONG_L $28, PT_R28(sp) + LONG_L $25, PT_R25(sp) + LONG_L $7, PT_R7(sp) + LONG_L $6, PT_R6(sp) + LONG_L $5, PT_R5(sp) + LONG_L $4, PT_R4(sp) + LONG_L $3, PT_R3(sp) + LONG_L $2, PT_R2(sp) + .set pop .endm - .macro RESTORE_SP_AND_RET - LONG_L sp, PT_R29(sp) + .macro RESTORE_SP_AND_RET + LONG_L sp, PT_R29(sp) eret nop .endm - .macro RESTORE_SP - LONG_L sp, PT_R29(sp) + .macro RESTORE_SP + LONG_L sp, PT_R29(sp) .endm - .macro RESTORE_ALL + .macro RESTORE_ALL RESTORE_TEMP RESTORE_FPU RESTORE_STATIC @@ -243,7 +243,7 @@ RESTORE_SP .endm - .macro RESTORE_ALL_AND_RET + .macro RESTORE_ALL_AND_RET RESTORE_TEMP RESTORE_FPU RESTORE_STATIC diff --git a/libcpu/mips/gs232/cache.c b/libcpu/mips/gs232/cache.c index 484d3816f4..bcbf2aba49 100644 --- a/libcpu/mips/gs232/cache.c +++ b/libcpu/mips/gs232/cache.c @@ -1,7 +1,7 @@ /* * Cache Ops For Loongson GS232 * - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -15,8 +15,8 @@ #include <rtthread.h> #include <mips.h> -#define K0BASE 0x80000000 -#define PRID_LS1C 0x4220 +#define K0BASE 0x80000000 +#define PRID_LS1C 0x4220 extern void Clear_TagLo (void); extern void Invalidate_Icache_Ls1c(unsigned int); @@ -27,10 +27,10 @@ extern void enable_cpu_cache(void); typedef struct cacheinfo_t { - unsigned int icache_size; - unsigned int dcache_size; - unsigned int icacheline_size; - unsigned int dcacheline_size; + unsigned int icache_size; + unsigned int dcache_size; + unsigned int icacheline_size; + unsigned int dcacheline_size; } cacheinfo_t ; typedef struct cacheop_t @@ -183,12 +183,12 @@ void rt_hw_cache_init(void) end = (start + pcacheinfo->icache_size); /* - * 2. clear CP0 taglo/taghi register; + * 2. clear CP0 taglo/taghi register; */ pcacheop->Clear_TagLo(); /* - * 3. invalidate instruction cache; + * 3. invalidate instruction cache; */ while (start < end) { @@ -197,7 +197,7 @@ void rt_hw_cache_init(void) } /* - * 4. invalidate data cache; + * 4. invalidate data cache; */ start = K0BASE; end = (start + pcacheinfo->dcache_size); diff --git a/libcpu/mips/gs232/cache.h b/libcpu/mips/gs232/cache.h index 381298e4df..b47db90814 100644 --- a/libcpu/mips/gs232/cache.h +++ b/libcpu/mips/gs232/cache.h @@ -1,8 +1,8 @@ /* * Cache Ops For Loongson GS232 - * - * Copyright (c) 2006-2019, RT-Thread Development Team - * + * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -12,8 +12,8 @@ * 2015-07-08 chinesebear modified for loongson 1c */ -#ifndef __CACHE_H__ -#define __CACHE_H__ +#ifndef __CACHE_H__ +#define __CACHE_H__ /* * Cache Operations */ @@ -21,31 +21,31 @@ #define Index_Writeback_Inv_D 0x01 #define Index_Invalidate_SI 0x02 #define Index_Writeback_Inv_SD 0x03 -#define Index_Load_Tag_I 0x04 -#define Index_Load_Tag_D 0x05 -#define Index_Load_Tag_SI 0x06 -#define Index_Load_Tag_SD 0x07 -#define Index_Store_Tag_I 0x08 -#define Index_Store_Tag_D 0x09 -#define Index_Store_Tag_SI 0x0A -#define Index_Store_Tag_SD 0x0B -#define Create_Dirty_Excl_D 0x0d -#define Create_Dirty_Excl_SD 0x0f -#define Hit_Invalidate_I 0x10 -#define Hit_Invalidate_D 0x11 -#define Hit_Invalidate_SI 0x12 -#define Hit_Invalidate_SD 0x13 -#define Fill 0x14 -#define Hit_Writeback_Inv_D 0x15 +#define Index_Load_Tag_I 0x04 +#define Index_Load_Tag_D 0x05 +#define Index_Load_Tag_SI 0x06 +#define Index_Load_Tag_SD 0x07 +#define Index_Store_Tag_I 0x08 +#define Index_Store_Tag_D 0x09 +#define Index_Store_Tag_SI 0x0A +#define Index_Store_Tag_SD 0x0B +#define Create_Dirty_Excl_D 0x0d +#define Create_Dirty_Excl_SD 0x0f +#define Hit_Invalidate_I 0x10 +#define Hit_Invalidate_D 0x11 +#define Hit_Invalidate_SI 0x12 +#define Hit_Invalidate_SD 0x13 +#define Fill 0x14 +#define Hit_Writeback_Inv_D 0x15 /* 0x16 is unused */ -#define Hit_Writeback_Inv_SD 0x17 -#define Hit_Writeback_I 0x18 -#define Hit_Writeback_D 0x19 +#define Hit_Writeback_Inv_SD 0x17 +#define Hit_Writeback_I 0x18 +#define Hit_Writeback_D 0x19 /* 0x1a is unused */ -#define Hit_Writeback_SD 0x1b +#define Hit_Writeback_SD 0x1b /* 0x1c is unused */ /* 0x1e is unused */ -#define Hit_Set_Virtual_SI 0x1e -#define Hit_Set_Virtual_SD 0x1f +#define Hit_Set_Virtual_SI 0x1e +#define Hit_Set_Virtual_SD 0x1f #endif diff --git a/libcpu/mips/gs232/cpuport.c b/libcpu/mips/gs232/cpuport.c index e3c078241f..e22d9bc14d 100644 --- a/libcpu/mips/gs232/cpuport.c +++ b/libcpu/mips/gs232/cpuport.c @@ -1,8 +1,8 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 - * + * * Change Logs: * Date Author Notes * 2010-07-09 Bernard first version @@ -26,9 +26,9 @@ RT_WEAK void rt_hw_cpu_reset(void) { /* open the watch-dog */ - WDT_EN = 0x01; /* watch dog enable */ - WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ - WDT_SET = 0x01; /* watch dog start */ + WDT_EN = 0x01; /* watch dog enable */ + WDT_TIMER = 0x01; /* watch dog will be timeout after 1 tick */ + WDT_SET = 0x01; /* watch dog start */ rt_kprintf("reboot system...\n"); while (1); diff --git a/libcpu/mips/gs232/gs232.h b/libcpu/mips/gs232/gs232.h index 95c81cf93e..cbc660c874 100644 --- a/libcpu/mips/gs232/gs232.h +++ b/libcpu/mips/gs232/gs232.h @@ -1,8 +1,8 @@ /* * Misc define for GS232 - * - * Copyright (c) 2006-2019, RT-Thread Development Team - * + * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -15,47 +15,47 @@ #include <mips.h> -#define INTC_BASE 0xBFD01040 +#define INTC_BASE 0xBFD01040 #ifdef SOC_LS1B -#define GS232_INTC_CELLS 4 +#define GS232_INTC_CELLS 4 #endif #ifdef SOC_LS1C300 -#define GS232_INTC_CELLS 5 +#define GS232_INTC_CELLS 5 #endif -#define GS232_NR_IRQS (32 * GS232_INTC_CELLS) +#define GS232_NR_IRQS (32 * GS232_INTC_CELLS) -#define GMAC0_BASE 0xBFE10000 -#define GMAC0_DMA_BASE 0xBFE11000 -#define GMAC1_BASE 0xBFE20000 -#define GMAC1_DMA_BASE 0xBFE21000 -#define I2C0_BASE 0xBFE58000 -#define PWM0_BASE 0xBFE5C000 -#define PWM1_BASE 0xBFE5C010 -#define PWM2_BASE 0xBFE5C020 -#define PWM3_BASE 0xBFE5C030 -#define WDT_BASE 0xBFE5C060 -#define RTC_BASE 0xBFE64000 -#define I2C1_BASE 0xBFE68000 -#define I2C2_BASE 0xBFE70000 -#define AC97_BASE 0xBFE74000 -#define NAND_BASE 0xBFE78000 -#define SPI_BASE 0xBFE80000 -#define CAN1_BASE 0xBF004300 -#define CAN0_BASE 0xBF004400 +#define GMAC0_BASE 0xBFE10000 +#define GMAC0_DMA_BASE 0xBFE11000 +#define GMAC1_BASE 0xBFE20000 +#define GMAC1_DMA_BASE 0xBFE21000 +#define I2C0_BASE 0xBFE58000 +#define PWM0_BASE 0xBFE5C000 +#define PWM1_BASE 0xBFE5C010 +#define PWM2_BASE 0xBFE5C020 +#define PWM3_BASE 0xBFE5C030 +#define WDT_BASE 0xBFE5C060 +#define RTC_BASE 0xBFE64000 +#define I2C1_BASE 0xBFE68000 +#define I2C2_BASE 0xBFE70000 +#define AC97_BASE 0xBFE74000 +#define NAND_BASE 0xBFE78000 +#define SPI_BASE 0xBFE80000 +#define CAN1_BASE 0xBF004300 +#define CAN0_BASE 0xBF004400 #ifndef __ASSEMBLY__ #include <rthw.h> /* Watch Dog registers */ -#define WDT_EN HWREG32(WDT_BASE + 0x00) -#define WDT_SET HWREG32(WDT_BASE + 0x04) -#define WDT_TIMER HWREG32(WDT_BASE + 0x08) +#define WDT_EN HWREG32(WDT_BASE + 0x00) +#define WDT_SET HWREG32(WDT_BASE + 0x04) +#define WDT_TIMER HWREG32(WDT_BASE + 0x08) -#define PLL_FREQ HWREG32(0xbfe78030) -#define PLL_DIV_PARAM HWREG32(0xbfe78034) +#define PLL_FREQ HWREG32(0xbfe78030) +#define PLL_DIV_PARAM HWREG32(0xbfe78034) struct gs232_intc_regs { @@ -65,7 +65,7 @@ struct gs232_intc_regs volatile unsigned int int_clr; /* offset 0x10*/ volatile unsigned int int_pol; volatile unsigned int int_edge; /* offset 0 */ -}; +}; extern void rt_hw_timer_init(void); diff --git a/libcpu/mips/gs232/interrupt.c b/libcpu/mips/gs232/interrupt.c index 66abea379d..fb80a8c1ec 100644 --- a/libcpu/mips/gs232/interrupt.c +++ b/libcpu/mips/gs232/interrupt.c @@ -1,17 +1,17 @@ /* * Interrupt handle for GS232 - * - * Copyright (c) 2006-2019, RT-Thread Development Team - * + * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2010-10-15 Bernard first version - * 2010-10-15 lgnq modified for LS1B + * 2010-10-15 lgnq modified for LS1B * 2013-03-29 aozima Modify the interrupt interface implementations. - * 2015-07-06 chinesebear modified for loongson 1c - * 2019-12-04 Jiaxun Yang Generialize + * 2015-07-06 chinesebear modified for loongson 1c + * 2019-12-04 Jiaxun Yang Generialize */ #include <rtthread.h> @@ -52,7 +52,7 @@ void rt_hw_interrupt_init(void) /* Disable */ (gs232_hw0_icregs+i)->int_en = 0x0; /* Trigger active low */ - (gs232_hw0_icregs+i)->int_pol = -1; /* Must be done here */ + (gs232_hw0_icregs+i)->int_pol = -1; /* Must be done here */ /* Make all interrupts level triggered */ (gs232_hw0_icregs+i)->int_edge = 0x00000000; /* Mask all interrupts */ @@ -113,7 +113,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, /** - * ִ Call ISR + * Call ISR * @IRQn ID of IRQ */ void gs232_do_IRQ(int IRQn) diff --git a/libcpu/mips/gs232/ls1b.h b/libcpu/mips/gs232/ls1b.h index a6f244ef4f..cf32bd5f02 100644 --- a/libcpu/mips/gs232/ls1b.h +++ b/libcpu/mips/gs232/ls1b.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: @@ -13,44 +13,44 @@ #include <gs232.h> -#define LS1B_ACPI_IRQ 0 -#define LS1B_HPET_IRQ 1 -#define LS1B_UART0_IRQ 2 -#define LS1B_UART1_IRQ 3 -#define LS1B_UART2_IRQ 4 -#define LS1B_UART3_IRQ 5 -#define LS1B_UART4_IRQ 29 -#define LS1B_UART5_IRQ 30 -#define LS1B_UART6_IRQ 2 //共享LS1B_UART0_IRQ -#define LS1B_UART7_IRQ 2 -#define LS1B_UART8_IRQ 2 -#define LS1B_UART9_IRQ 3 //共享LS1B_UART1_IRQ -#define LS1B_UART10_IRQ 3 -#define LS1B_UART11_IRQ 3 +#define LS1B_ACPI_IRQ 0 +#define LS1B_HPET_IRQ 1 +#define LS1B_UART0_IRQ 2 +#define LS1B_UART1_IRQ 3 +#define LS1B_UART2_IRQ 4 +#define LS1B_UART3_IRQ 5 +#define LS1B_UART4_IRQ 29 +#define LS1B_UART5_IRQ 30 +#define LS1B_UART6_IRQ 2 //共享LS1B_UART0_IRQ +#define LS1B_UART7_IRQ 2 +#define LS1B_UART8_IRQ 2 +#define LS1B_UART9_IRQ 3 //共享LS1B_UART1_IRQ +#define LS1B_UART10_IRQ 3 +#define LS1B_UART11_IRQ 3 -#define LS1B_CAN0_IRQ 6 -#define LS1B_CAN1_IRQ 7 -#define LS1B_SPI0_IRQ 8 -#define LS1B_SPI1_IRQ 9 -#define LS1B_AC97_IRQ 10 -#define LS1B_MS_IRQ 11 -#define LS1B_KB_IRQ 12 -#define LS1B_DMA0_IRQ 13 -#define LS1B_DMA1_IRQ 14 -#define LS1B_NAND_IRQ 15 -#define LS1B_I2C0_IRQ 16 -#define LS1B_I2C1_IRQ 17 -#define LS1B_PWM0_IRQ 18 -#define LS1B_PWM1_IRQ 19 -#define LS1B_PWM2_IRQ 20 -#define LS1B_PWM3_IRQ 21 -#define LS1B_LPC_IRQ 22 -#define LS1B_EHCI_IRQ 32 -#define LS1B_OHCI_IRQ 33 -#define LS1B_GMAC1_IRQ 34 -#define LS1B_GMAC2_IRQ 35 -#define LS1B_SATA_IRQ 36 -#define LS1B_GPU_IRQ 37 +#define LS1B_CAN0_IRQ 6 +#define LS1B_CAN1_IRQ 7 +#define LS1B_SPI0_IRQ 8 +#define LS1B_SPI1_IRQ 9 +#define LS1B_AC97_IRQ 10 +#define LS1B_MS_IRQ 11 +#define LS1B_KB_IRQ 12 +#define LS1B_DMA0_IRQ 13 +#define LS1B_DMA1_IRQ 14 +#define LS1B_NAND_IRQ 15 +#define LS1B_I2C0_IRQ 16 +#define LS1B_I2C1_IRQ 17 +#define LS1B_PWM0_IRQ 18 +#define LS1B_PWM1_IRQ 19 +#define LS1B_PWM2_IRQ 20 +#define LS1B_PWM3_IRQ 21 +#define LS1B_LPC_IRQ 22 +#define LS1B_EHCI_IRQ 32 +#define LS1B_OHCI_IRQ 33 +#define LS1B_GMAC1_IRQ 34 +#define LS1B_GMAC2_IRQ 35 +#define LS1B_SATA_IRQ 36 +#define LS1B_GPU_IRQ 37 #define LS1B_PCI_INTA_IRQ 38 #define LS1B_PCI_INTB_IRQ 39 #define LS1B_PCI_INTC_IRQ 40 @@ -61,13 +61,13 @@ #define LS1B_GPIO_IRQ_COUNT 64 #define LS1B_GPIO_LAST_IRQ (LS1B_GPIO_FIRST_IRQ + LS1B_GPIO_IRQ_COUNT-1) -#define INT_PCI_INTA (1<<6) -#define INT_PCI_INTB (1<<7) -#define INT_PCI_INTC (1<<8) -#define INT_PCI_INTD (1<<9) +#define INT_PCI_INTA (1<<6) +#define INT_PCI_INTB (1<<7) +#define INT_PCI_INTC (1<<8) +#define INT_PCI_INTD (1<<9) #define LS1B_LAST_IRQ 159 -#define MIPS_CPU_TIMER_IRQ 167 +#define MIPS_CPU_TIMER_IRQ 167 #define LS1B_INTREG_BASE 0xbfd01040 #define LS1B_DMA_IRQ_BASE 168 diff --git a/libcpu/mips/gs232/ls1c.h b/libcpu/mips/gs232/ls1c.h index 54c7e36e99..6b8e3fc512 100644 --- a/libcpu/mips/gs232/ls1c.h +++ b/libcpu/mips/gs232/ls1c.h @@ -1,6 +1,6 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team - * + * Copyright (c) 2006-2021, RT-Thread Development Team + * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: diff --git a/libcpu/mips/gs232/mipscfg.c b/libcpu/mips/gs232/mipscfg.c index 85e0e633ea..6b37abb895 100644 --- a/libcpu/mips/gs232/mipscfg.c +++ b/libcpu/mips/gs232/mipscfg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -12,13 +12,13 @@ mips32_core_cfg_t g_mips_core = { - 16, /* icache_line_size */ - 256, /* icache_lines_per_way */ - 4, /* icache_ways */ - 16, /* dcache_line_size */ - 256, /* dcache_lines_per_way */ - 4, /* dcache_ways */ - 16, /* max_tlb_entries */ + 16, /* icache_line_size */ + 256, /* icache_lines_per_way */ + 4, /* icache_ways */ + 16, /* dcache_line_size */ + 256, /* dcache_lines_per_way */ + 4, /* dcache_ways */ + 16, /* max_tlb_entries */ }; static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n) diff --git a/libcpu/mips/gs232/timer.c b/libcpu/mips/gs232/timer.c index 8879b82ccf..4df02a1b62 100644 --- a/libcpu/mips/gs232/timer.c +++ b/libcpu/mips/gs232/timer.c @@ -1,7 +1,7 @@ /* * Assembly Macros For MIPS * - * Copyright (c) 2006-2019, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -20,14 +20,14 @@ */ void rt_hw_timer_handler(void) { - unsigned int count; + unsigned int count; - count = read_c0_compare(); - write_c0_compare(count); - write_c0_count(0); + count = read_c0_compare(); + write_c0_compare(count); + write_c0_count(0); - /* increase a OS tick */ - rt_tick_increase(); + /* increase a OS tick */ + rt_tick_increase(); } /** @@ -35,7 +35,7 @@ void rt_hw_timer_handler(void) */ void rt_hw_timer_init(void) { - write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND); - write_c0_count(0); - mips_unmask_cpu_irq(7); -}
\ No newline at end of file + write_c0_compare(CPU_HZ/2/RT_TICK_PER_SECOND); + write_c0_count(0); + mips_unmask_cpu_irq(7); +} diff --git a/libcpu/mips/gs264/cache.c b/libcpu/mips/gs264/cache.c index 54d38d0d3f..50976f2e4f 100644 --- a/libcpu/mips/gs264/cache.c +++ b/libcpu/mips/gs264/cache.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/gs264/cache.h b/libcpu/mips/gs264/cache.h index 10a4afd899..1e1bc52737 100644 --- a/libcpu/mips/gs264/cache.h +++ b/libcpu/mips/gs264/cache.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/gs264/mips_mmu.c b/libcpu/mips/gs264/mips_mmu.c index 7bed69596a..eae9b007de 100644 --- a/libcpu/mips/gs264/mips_mmu.c +++ b/libcpu/mips/gs264/mips_mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -19,7 +19,7 @@ void mmu_init() uint32_t status = read_c0_status(); status |= 0x07 << 5;//ux = 1,sx = 1,kx = 1 write_c0_status(status); - + mmu_clear_tlb(); mmu_clear_itlb(); } @@ -154,7 +154,7 @@ void mmu_set_map(uint64_t vpn,uint64_t ppn,page_mask_enum_t page_mask,uint32_t a uint64_t even_vpn = vpn & (~lb); uint32_t index; tlb_item_t tlb_item,tlb2_item; - + mmu_tlb_item_init(&tlb_item); mmu_tlb_item_init(&tlb2_item); tlb_item.page_mask.mask = page_mask; diff --git a/libcpu/mips/gs264/mips_mmu.h b/libcpu/mips/gs264/mips_mmu.h index fcbcef3621..4c7af117d9 100644 --- a/libcpu/mips/gs264/mips_mmu.h +++ b/libcpu/mips/gs264/mips_mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -96,4 +96,4 @@ uint64_t mmu_tlb_get_bad_vaddr(); void tlb_dump(); -#endif
\ No newline at end of file +#endif diff --git a/libcpu/mips/gs264/mipscfg.c b/libcpu/mips/gs264/mipscfg.c index b2aed120ae..0ce7000581 100644 --- a/libcpu/mips/gs264/mipscfg.c +++ b/libcpu/mips/gs264/mipscfg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/gs264/mmu.c b/libcpu/mips/gs264/mmu.c index b5bedace50..cab73f37bd 100644 --- a/libcpu/mips/gs264/mmu.c +++ b/libcpu/mips/gs264/mmu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -387,7 +387,7 @@ static void __rt_hw_mmu_unmap(rt_mmu_info *mmu_info, void* v_addr, size_t npages return; } - if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) + if (*(mmu_l2 + l2_off) & ARCH_MMU_USED_MASK) { *(mmu_l2 + l2_off) = 0; /* cache maintain */ @@ -691,7 +691,7 @@ void *rt_hw_kernel_virt_to_phys(void *v_addr, size_t size) //pa --> va void *rt_hw_kernel_phys_to_virt(void *p_addr, size_t size) -{ +{ void *v_addr = 0; #ifdef RT_USING_USERSPACE diff --git a/libcpu/mips/gs264/mmu.h b/libcpu/mips/gs264/mmu.h index 2472bf975f..22a749af64 100644 --- a/libcpu/mips/gs264/mmu.h +++ b/libcpu/mips/gs264/mmu.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2020, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/mips/pic32/cpuport.c b/libcpu/mips/pic32/cpuport.c index 3f08d57167..089f652bce 100644 --- a/libcpu/mips/pic32/cpuport.c +++ b/libcpu/mips/pic32/cpuport.c @@ -45,51 +45,51 @@ rt_uint32_t __attribute__((nomips16)) _get_gp(void) */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; /** Start at stack top */ stk = (rt_uint32_t *)stack_addr; - *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ - *(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */ - *(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */ - *(--stk) = (rt_uint32_t) 0; /* lo */ - *(--stk) = (rt_uint32_t) 0; /* hi */ - *(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */ - *(--stk) = (rt_uint32_t) texit; /* 31 ra */ - *(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */ - *(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */ - *(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */ - *(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */ - *(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */ - *(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */ - *(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */ - *(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */ - *(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */ - *(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */ - *(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */ - *(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */ - *(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */ - *(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */ - *(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */ - *(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */ - *(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */ - *(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */ - *(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */ - *(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */ - *(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */ - *(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */ - *(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */ - *(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */ - *(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */ - *(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */ - *(--stk) = (rt_uint32_t) parameter; /* 4 a0 */ - *(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */ - *(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */ - *(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */ - *(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */ + *(stk) = (rt_uint32_t) tentry; /* pc: Entry Point */ + *(--stk) = (rt_uint32_t) 0x00800000; /* c0_cause: IV=1, */ + *(--stk) = (rt_uint32_t) 0; /* c0_badvaddr */ + *(--stk) = (rt_uint32_t) 0; /* lo */ + *(--stk) = (rt_uint32_t) 0; /* hi */ + *(--stk) = (rt_uint32_t) 1; /* C0_SR: IE = En, */ + *(--stk) = (rt_uint32_t) texit; /* 31 ra */ + *(--stk) = (rt_uint32_t) 0x0000001e; /* 30 s8 */ + *(--stk) = (rt_uint32_t) stack_addr; /* 29 sp */ + *(--stk) = (rt_uint32_t) _get_gp(); /* 28 gp */ + *(--stk) = (rt_uint32_t) 0x0000001b; /* 27 k1 */ + *(--stk) = (rt_uint32_t) 0x0000001a; /* 26 k0 */ + *(--stk) = (rt_uint32_t) 0x00000019; /* 25 t9 */ + *(--stk) = (rt_uint32_t) 0x00000018; /* 24 t8 */ + *(--stk) = (rt_uint32_t) 0x00000017; /* 23 s7 */ + *(--stk) = (rt_uint32_t) 0x00000016; /* 22 s6 */ + *(--stk) = (rt_uint32_t) 0x00000015; /* 21 s5 */ + *(--stk) = (rt_uint32_t) 0x00000014; /* 20 s4 */ + *(--stk) = (rt_uint32_t) 0x00000013; /* 19 s3 */ + *(--stk) = (rt_uint32_t) 0x00000012; /* 18 s2 */ + *(--stk) = (rt_uint32_t) 0x00000011; /* 17 s1 */ + *(--stk) = (rt_uint32_t) 0x00000010; /* 16 s0 */ + *(--stk) = (rt_uint32_t) 0x0000000f; /* 15 t7 */ + *(--stk) = (rt_uint32_t) 0x0000000e; /* 14 t6 */ + *(--stk) = (rt_uint32_t) 0x0000000d; /* 13 t5 */ + *(--stk) = (rt_uint32_t) 0x0000000c; /* 12 t4 */ + *(--stk) = (rt_uint32_t) 0x0000000b; /* 11 t3 */ + *(--stk) = (rt_uint32_t) 0x0000000a; /* 10 t2 */ + *(--stk) = (rt_uint32_t) 0x00000009; /* 9 t1 */ + *(--stk) = (rt_uint32_t) 0x00000008; /* 8 t0 */ + *(--stk) = (rt_uint32_t) 0x00000007; /* 7 a3 */ + *(--stk) = (rt_uint32_t) 0x00000006; /* 6 a2 */ + *(--stk) = (rt_uint32_t) 0x00000005; /* 5 a1 */ + *(--stk) = (rt_uint32_t) parameter; /* 4 a0 */ + *(--stk) = (rt_uint32_t) 0x00000003; /* 3 v1 */ + *(--stk) = (rt_uint32_t) 0x00000002; /* 2 v0 */ + *(--stk) = (rt_uint32_t) 0x00000001; /* 1 at */ + *(--stk) = (rt_uint32_t) 0x00000000; /* 0 zero */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } diff --git a/libcpu/mips/pic32/exceptions.c b/libcpu/mips/pic32/exceptions.c index de5f70b7e1..d9f457a707 100644 --- a/libcpu/mips/pic32/exceptions.c +++ b/libcpu/mips/pic32/exceptions.c @@ -11,13 +11,13 @@ * Complier: MPLAB C32 * MPLAB IDE * Company: Microchip Technology, Inc. - * Author: Darren Wenn + * Author: Darren Wenn * * Software License Agreement * * The software supplied herewith by Microchip Technology Incorporated - * (the �Company�) for its PIC32/PIC24 Microcontroller is intended - * and supplied to you, the Company�s customer, for use solely and + * (the “Company”) for its PIC32/PIC24 Microcontroller is intended + * and supplied to you, the Company’s customer, for use solely and * exclusively on Microchip PIC32/PIC24 Microcontroller products. * The software is owned by the Company and/or its supplier, and is * protected under applicable copyright laws. All rights are reserved. @@ -26,7 +26,7 @@ * civil liability for the breach of the terms and conditions of this * license. * - * THIS SOFTWARE IS PROVIDED IN AN �AS IS� CONDITION. NO WARRANTIES, + * THIS SOFTWARE IS PROVIDED IN AN “AS IS” CONDITION. NO WARRANTIES, * WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED * TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, @@ -42,20 +42,20 @@ // declared static in case exception condition would prevent // auto variable being created static enum { - EXCEP_IRQ = 0, // interrupt - EXCEP_AdEL = 4, // address error exception (load or ifetch) - EXCEP_AdES, // address error exception (store) - EXCEP_IBE, // bus error (ifetch) - EXCEP_DBE, // bus error (load/store) - EXCEP_Sys, // syscall - EXCEP_Bp, // breakpoint - EXCEP_RI, // reserved instruction - EXCEP_CpU, // coprocessor unusable - EXCEP_Overflow, // arithmetic overflow - EXCEP_Trap, // trap (possible divide by zero) - EXCEP_IS1 = 16, // implementation specfic 1 - EXCEP_CEU, // CorExtend Unuseable - EXCEP_C2E // coprocessor 2 + EXCEP_IRQ = 0, // interrupt + EXCEP_AdEL = 4, // address error exception (load or ifetch) + EXCEP_AdES, // address error exception (store) + EXCEP_IBE, // bus error (ifetch) + EXCEP_DBE, // bus error (load/store) + EXCEP_Sys, // syscall + EXCEP_Bp, // breakpoint + EXCEP_RI, // reserved instruction + EXCEP_CpU, // coprocessor unusable + EXCEP_Overflow, // arithmetic overflow + EXCEP_Trap, // trap (possible divide by zero) + EXCEP_IS1 = 16, // implementation specfic 1 + EXCEP_CEU, // CorExtend Unuseable + EXCEP_C2E // coprocessor 2 } _excep_code; static unsigned int _epc_code; @@ -65,34 +65,34 @@ static unsigned int _excep_addr; // this function overrides the normal _weak_ generic handler void _general_exception_handler(void) { - asm volatile("mfc0 %0,$13" : "=r" (_excep_code)); - asm volatile("mfc0 %0,$14" : "=r" (_excep_addr)); + asm volatile("mfc0 %0,$13" : "=r" (_excep_code)); + asm volatile("mfc0 %0,$14" : "=r" (_excep_addr)); - _excep_code = (_excep_code & 0x0000007C) >> 2; + _excep_code = (_excep_code & 0x0000007C) >> 2; - rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code); - rt_kprintf("_excep_addr : %08X\r\n",_excep_addr); - switch(_excep_code) - { - case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break; - case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break; - case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break; - case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break; - case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break; - case EXCEP_Sys:rt_kprintf("syscall\r\n");break; - case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break; - case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break; - case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break; - case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break; - case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break; - case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break; - case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break; - case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break; - default : rt_kprintf("unkown exception\r\n");break; - } + rt_kprintf("\r\n_excep_code : %08X\r\n",_excep_code); + rt_kprintf("_excep_addr : %08X\r\n",_excep_addr); + switch(_excep_code) + { + case EXCEP_IRQ:rt_kprintf("interrupt\r\n");break; + case EXCEP_AdEL:rt_kprintf("address error exception (load or ifetch)\r\n");break; + case EXCEP_AdES:rt_kprintf("address error exception (store)\r\n");break; + case EXCEP_IBE:rt_kprintf("bus error (ifetch)\r\n");break; + case EXCEP_DBE:rt_kprintf("bus error (load/store)\r\n");break; + case EXCEP_Sys:rt_kprintf("syscall\r\n");break; + case EXCEP_Bp:rt_kprintf("breakpoint\r\n");break; + case EXCEP_RI:rt_kprintf("reserved instruction\r\n");break; + case EXCEP_CpU:rt_kprintf("coprocessor unusable\r\n");break; + case EXCEP_Overflow:rt_kprintf("arithmetic overflow\r\n");break; + case EXCEP_Trap:rt_kprintf("trap (possible divide by zero)\r\n");break; + case EXCEP_IS1:rt_kprintf("implementation specfic 1\r\n");break; + case EXCEP_CEU:rt_kprintf("CorExtend Unuseable\r\n");break; + case EXCEP_C2E:rt_kprintf("coprocessor 2\r\n");break; + default : rt_kprintf("unkown exception\r\n");break; + } - while (1) { - // Examine _excep_code to identify the type of exception - // Examine _excep_addr to find the address that caused the exception - } + while (1) { + // Examine _excep_code to identify the type of exception + // Examine _excep_addr to find the address that caused the exception + } } diff --git a/libcpu/nios/nios_ii/stack.c b/libcpu/nios/nios_ii/stack.c index 125bf2c578..463ba0df96 100644 --- a/libcpu/nios/nios_ii/stack.c +++ b/libcpu/nios/nios_ii/stack.c @@ -1,7 +1,7 @@ /* * File : stack.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -30,43 +30,43 @@ * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - *(stk) = 0x01; /* status */ - *(--stk) = (unsigned long)texit; /* ra */ - *(--stk) = 0xdeadbeef; /* fp */ - *(--stk) = 0xdeadbeef; /* r23 */ - *(--stk) = 0xdeadbeef; /* r22 */ - *(--stk) = 0xdeadbeef; /* r21 */ - *(--stk) = 0xdeadbeef; /* r20 */ - *(--stk) = 0xdeadbeef; /* r19 */ - *(--stk) = 0xdeadbeef; /* r18 */ - *(--stk) = 0xdeadbeef; /* r17 */ - *(--stk) = 0xdeadbeef; /* r16 */ -// *(--stk) = 0xdeadbeef; /* r15 */ -// *(--stk) = 0xdeadbeef; /* r14 */ -// *(--stk) = 0xdeadbeef; /* r13 */ -// *(--stk) = 0xdeadbeef; /* r12 */ -// *(--stk) = 0xdeadbeef; /* r11 */ -// *(--stk) = 0xdeadbeef; /* r10 */ -// *(--stk) = 0xdeadbeef; /* r9 */ -// *(--stk) = 0xdeadbeef; /* r8 */ - *(--stk) = 0xdeadbeef; /* r7 */ - *(--stk) = 0xdeadbeef; /* r6 */ - *(--stk) = 0xdeadbeef; /* r5 */ - *(--stk) = (unsigned long)parameter; /* r4 argument */ - *(--stk) = 0xdeadbeef; /* r3 */ - *(--stk) = 0xdeadbeef; /* r2 */ - *(--stk) = (unsigned long)tentry; /* pc */ + stk = (unsigned long *)stack_addr; + *(stk) = 0x01; /* status */ + *(--stk) = (unsigned long)texit; /* ra */ + *(--stk) = 0xdeadbeef; /* fp */ + *(--stk) = 0xdeadbeef; /* r23 */ + *(--stk) = 0xdeadbeef; /* r22 */ + *(--stk) = 0xdeadbeef; /* r21 */ + *(--stk) = 0xdeadbeef; /* r20 */ + *(--stk) = 0xdeadbeef; /* r19 */ + *(--stk) = 0xdeadbeef; /* r18 */ + *(--stk) = 0xdeadbeef; /* r17 */ + *(--stk) = 0xdeadbeef; /* r16 */ +// *(--stk) = 0xdeadbeef; /* r15 */ +// *(--stk) = 0xdeadbeef; /* r14 */ +// *(--stk) = 0xdeadbeef; /* r13 */ +// *(--stk) = 0xdeadbeef; /* r12 */ +// *(--stk) = 0xdeadbeef; /* r11 */ +// *(--stk) = 0xdeadbeef; /* r10 */ +// *(--stk) = 0xdeadbeef; /* r9 */ +// *(--stk) = 0xdeadbeef; /* r8 */ + *(--stk) = 0xdeadbeef; /* r7 */ + *(--stk) = 0xdeadbeef; /* r6 */ + *(--stk) = 0xdeadbeef; /* r5 */ + *(--stk) = (unsigned long)parameter; /* r4 argument */ + *(--stk) = 0xdeadbeef; /* r3 */ + *(--stk) = 0xdeadbeef; /* r2 */ + *(--stk) = (unsigned long)tentry; /* pc */ -// *(stk) = (unsigned long)tentry; /* thread entry (ra) */ -// *(--stk) = (unsigned long)parameter; /* thread argument, r4 */ +// *(stk) = (unsigned long)tentry; /* thread entry (ra) */ +// *(--stk) = (unsigned long)parameter; /* thread argument, r4 */ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/libcpu/ppc/common/ptrace.h b/libcpu/ppc/common/ptrace.h index 72ef31bfbc..8d06ed00ca 100644 --- a/libcpu/ppc/common/ptrace.h +++ b/libcpu/ppc/common/ptrace.h @@ -24,24 +24,24 @@ struct pt_regs { PPC_REG gpr[32]; PPC_REG nip; PPC_REG msr; - PPC_REG orig_gpr3; /* Used for restarting system calls */ + PPC_REG orig_gpr3; /* Used for restarting system calls */ PPC_REG ctr; PPC_REG link; PPC_REG xer; PPC_REG ccr; - PPC_REG mq; /* 601 only (not used at present) */ + PPC_REG mq; /* 601 only (not used at present) */ /* Used on APUS to hold IPL value. */ - PPC_REG trap; /* Reason for being here */ - PPC_REG dar; /* Fault registers */ + PPC_REG trap; /* Reason for being here */ + PPC_REG dar; /* Fault registers */ PPC_REG dsisr; - PPC_REG result; /* Result of a system call */ + PPC_REG result; /* Result of a system call */ }__attribute__((packed)) CELL_STACK_FRAME_t; #endif -#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ +#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ /* Size of stack frame allocated when calling signal handler. */ -#define __SIGNAL_FRAMESIZE 64 +#define __SIGNAL_FRAMESIZE 64 #define instruction_pointer(regs) ((regs)->nip) #define user_mode(regs) (((regs)->msr & MSR_PR) != 0) @@ -51,49 +51,49 @@ struct pt_regs { * These can't be changed without breaking binary compatibility * with MkLinux, etc. */ -#define PT_R0 0 -#define PT_R1 1 -#define PT_R2 2 -#define PT_R3 3 -#define PT_R4 4 -#define PT_R5 5 -#define PT_R6 6 -#define PT_R7 7 -#define PT_R8 8 -#define PT_R9 9 -#define PT_R10 10 -#define PT_R11 11 -#define PT_R12 12 -#define PT_R13 13 -#define PT_R14 14 -#define PT_R15 15 -#define PT_R16 16 -#define PT_R17 17 -#define PT_R18 18 -#define PT_R19 19 -#define PT_R20 20 -#define PT_R21 21 -#define PT_R22 22 -#define PT_R23 23 -#define PT_R24 24 -#define PT_R25 25 -#define PT_R26 26 -#define PT_R27 27 -#define PT_R28 28 -#define PT_R29 29 -#define PT_R30 30 -#define PT_R31 31 +#define PT_R0 0 +#define PT_R1 1 +#define PT_R2 2 +#define PT_R3 3 +#define PT_R4 4 +#define PT_R5 5 +#define PT_R6 6 +#define PT_R7 7 +#define PT_R8 8 +#define PT_R9 9 +#define PT_R10 10 +#define PT_R11 11 +#define PT_R12 12 +#define PT_R13 13 +#define PT_R14 14 +#define PT_R15 15 +#define PT_R16 16 +#define PT_R17 17 +#define PT_R18 18 +#define PT_R19 19 +#define PT_R20 20 +#define PT_R21 21 +#define PT_R22 22 +#define PT_R23 23 +#define PT_R24 24 +#define PT_R25 25 +#define PT_R26 26 +#define PT_R27 27 +#define PT_R28 28 +#define PT_R29 29 +#define PT_R30 30 +#define PT_R31 31 -#define PT_NIP 32 -#define PT_MSR 33 +#define PT_NIP 32 +#define PT_MSR 33 #define PT_ORIG_R3 34 -#define PT_CTR 35 -#define PT_LNK 36 -#define PT_XER 37 -#define PT_CCR 38 -#define PT_MQ 39 +#define PT_CTR 35 +#define PT_LNK 36 +#define PT_XER 37 +#define PT_CCR 38 +#define PT_MQ 39 -#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ +#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ #define PT_FPR31 (PT_FPR0 + 2*31) #define PT_FPSCR (PT_FPR0 + 2*32 + 1) diff --git a/libcpu/ppc/common/stack.c b/libcpu/ppc/common/stack.c index 570e9ba046..de9d7d2016 100644 --- a/libcpu/ppc/common/stack.c +++ b/libcpu/ppc/common/stack.c @@ -1,7 +1,7 @@ /* * File : stack.c * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006-2011, RT-Thread Development Team + * COPYRIGHT (C) 2006-2021, RT-Thread Development Team * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at @@ -9,7 +9,7 @@ * * Change Logs: * Date Author Notes - * 2011-02-14 Fred first implementation for + * 2011-02-14 Fred first implementation for */ #include <rtthread.h> diff --git a/libcpu/ppc/ppc405/context.h b/libcpu/ppc/ppc405/context.h index 8b4d55d698..cb12df845c 100644 --- a/libcpu/ppc/ppc405/context.h +++ b/libcpu/ppc/ppc405/context.h @@ -1,9 +1,9 @@ #ifndef __CONTEXT_H__ #define __CONTEXT_H__ -#define MSR_ME (1<<12) /* Machine Check Enable */ +#define MSR_ME (1<<12) /* Machine Check Enable */ #define MSR_EE (1<<15) /* External Interrupt Enable */ -#define MSR_CE (1<<17) /* Critical Interrupt Enable */ +#define MSR_CE (1<<17) /* Critical Interrupt Enable */ #define GPR0 0 #define GPR2 4 diff --git a/libcpu/ppc/ppc405/include/asm/ppc405.h b/libcpu/ppc/ppc405/include/asm/ppc405.h index c2562047cb..5e96fa782a 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc405.h +++ b/libcpu/ppc/ppc405/include/asm/ppc405.h @@ -1,30 +1,30 @@ /*----------------------------------------------------------------------------+ | -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. | -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. | -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. | -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M +----------------------------------------------------------------------------*/ -#ifndef __PPC405_H__ +#ifndef __PPC405_H__ #define __PPC405_H__ /* Define bits and masks for real-mode storage attribute control registers */ -#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) -#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) +#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) +#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) /****************************************************************************** * Special for PPC405GP @@ -34,29 +34,29 @@ * DMA ******************************************************************************/ #define DMA_DCR_BASE 0x100 -#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ -#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ -#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ -#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ -#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ -#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ -#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ -#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ -#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ -#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ -#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ -#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ -#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ -#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ -#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ -#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ -#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ -#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ -#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ -#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ -#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ -#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ -#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ +#define dmacr0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ +#define dmact0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ +#define dmada0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ +#define dmasa0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ +#define dmasb0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ +#define dmacr1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ +#define dmact1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ +#define dmada1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ +#define dmasa1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ +#define dmasb1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ +#define dmacr2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ +#define dmact2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ +#define dmada2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ +#define dmasa2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ +#define dmasb2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ +#define dmacr3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ +#define dmact3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ +#define dmada3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ +#define dmasa3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ +#define dmasb3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ +#define dmasr (DMA_DCR_BASE+0x20) /* DMA status register */ +#define dmasgc (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ +#define dmaadr (DMA_DCR_BASE+0x24) /* DMA address decode register */ #ifndef CONFIG_405EP /****************************************************************************** @@ -66,22 +66,22 @@ #define kiar (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ #define kidr (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ /* values for kiar register - indirect addressing of these regs */ - #define kitor0 0x00 /* index table origin register 0 */ - #define kitor1 0x01 /* index table origin register 1 */ - #define kitor2 0x02 /* index table origin register 2 */ - #define kitor3 0x03 /* index table origin register 3 */ + #define kitor0 0x00 /* index table origin register 0 */ + #define kitor1 0x01 /* index table origin register 1 */ + #define kitor2 0x02 /* index table origin register 2 */ + #define kitor3 0x03 /* index table origin register 3 */ #define kaddr0 0x04 /* address decode definition regsiter 0 */ #define kaddr1 0x05 /* address decode definition regsiter 1 */ #define kconf 0x40 /* decompression core config register */ - #define kid 0x41 /* decompression core ID register */ - #define kver 0x42 /* decompression core version # reg */ - #define kpear 0x50 /* bus error addr reg (PLB addr) */ + #define kid 0x41 /* decompression core ID register */ + #define kver 0x42 /* decompression core version # reg */ + #define kpear 0x50 /* bus error addr reg (PLB addr) */ #define kbear 0x51 /* bus error addr reg (DCP to EBIU addr)*/ #define kesr0 0x52 /* bus error status reg 0 (R/clear) */ - #define kesr0s 0x53 /* bus error status reg 0 (set) */ + #define kesr0s 0x53 /* bus error status reg 0 (set) */ /* There are 0x400 of the following registers, from krom0 to krom3ff*/ - /* Only the first one is given here. */ - #define krom0 0x400 /* SRAM/ROM read/write */ + /* Only the first one is given here. */ + #define krom0 0x400 /* SRAM/ROM read/write */ #endif /****************************************************************************** @@ -92,23 +92,23 @@ #else #define POWERMAN_DCR_BASE 0xb8 #endif -#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ -#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ -#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ +#define cpmsr (POWERMAN_DCR_BASE+0x0) /* Power management status */ +#define cpmer (POWERMAN_DCR_BASE+0x1) /* Power management enable */ +#define cpmfr (POWERMAN_DCR_BASE+0x2) /* Power management force */ /****************************************************************************** * Extrnal Bus Controller ******************************************************************************/ /* values for ebccfga register - indirect addressing of these regs */ - #define pb0cr 0x00 /* periph bank 0 config reg */ - #define pb1cr 0x01 /* periph bank 1 config reg */ - #define pb2cr 0x02 /* periph bank 2 config reg */ - #define pb3cr 0x03 /* periph bank 3 config reg */ - #define pb4cr 0x04 /* periph bank 4 config reg */ + #define pb0cr 0x00 /* periph bank 0 config reg */ + #define pb1cr 0x01 /* periph bank 1 config reg */ + #define pb2cr 0x02 /* periph bank 2 config reg */ + #define pb3cr 0x03 /* periph bank 3 config reg */ + #define pb4cr 0x04 /* periph bank 4 config reg */ #ifndef CONFIG_405EP - #define pb5cr 0x05 /* periph bank 5 config reg */ - #define pb6cr 0x06 /* periph bank 6 config reg */ - #define pb7cr 0x07 /* periph bank 7 config reg */ + #define pb5cr 0x05 /* periph bank 5 config reg */ + #define pb6cr 0x06 /* periph bank 6 config reg */ + #define pb7cr 0x07 /* periph bank 7 config reg */ #endif #define pb0ap 0x10 /* periph bank 0 access parameters */ #define pb1ap 0x11 /* periph bank 1 access parameters */ @@ -120,221 +120,221 @@ #define pb6ap 0x16 /* periph bank 6 access parameters */ #define pb7ap 0x17 /* periph bank 7 access parameters */ #endif - #define pbear 0x20 /* periph bus error addr reg */ - #define pbesr0 0x21 /* periph bus error status reg 0 */ - #define pbesr1 0x22 /* periph bus error status reg 1 */ - #define epcr 0x23 /* external periph control reg */ -#define EBC0_CFG 0x23 /* external bus configuration reg */ + #define pbear 0x20 /* periph bus error addr reg */ + #define pbesr0 0x21 /* periph bus error status reg 0 */ + #define pbesr1 0x22 /* periph bus error status reg 1 */ + #define epcr 0x23 /* external periph control reg */ +#define EBC0_CFG 0x23 /* external bus configuration reg */ #ifdef CONFIG_405EP /****************************************************************************** * Control ******************************************************************************/ #define CNTRL_DCR_BASE 0x0f0 -#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ -#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ -#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ -#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ -#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ -#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ +#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ +#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ +#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ +#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ +#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ +#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ #define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ #define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ /* Bit definitions */ -#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ -#define PLLMR0_CPU_DIV_BYPASS 0x00000000 -#define PLLMR0_CPU_DIV_2 0x00100000 -#define PLLMR0_CPU_DIV_3 0x00200000 -#define PLLMR0_CPU_DIV_4 0x00300000 +#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ +#define PLLMR0_CPU_DIV_BYPASS 0x00000000 +#define PLLMR0_CPU_DIV_2 0x00100000 +#define PLLMR0_CPU_DIV_3 0x00200000 +#define PLLMR0_CPU_DIV_4 0x00300000 -#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ -#define PLLMR0_CPU_PLB_DIV_1 0x00000000 -#define PLLMR0_CPU_PLB_DIV_2 0x00010000 -#define PLLMR0_CPU_PLB_DIV_3 0x00020000 -#define PLLMR0_CPU_PLB_DIV_4 0x00030000 +#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ +#define PLLMR0_CPU_PLB_DIV_1 0x00000000 +#define PLLMR0_CPU_PLB_DIV_2 0x00010000 +#define PLLMR0_CPU_PLB_DIV_3 0x00020000 +#define PLLMR0_CPU_PLB_DIV_4 0x00030000 -#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ -#define PLLMR0_OPB_PLB_DIV_1 0x00000000 -#define PLLMR0_OPB_PLB_DIV_2 0x00001000 -#define PLLMR0_OPB_PLB_DIV_3 0x00002000 -#define PLLMR0_OPB_PLB_DIV_4 0x00003000 +#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ +#define PLLMR0_OPB_PLB_DIV_1 0x00000000 +#define PLLMR0_OPB_PLB_DIV_2 0x00001000 +#define PLLMR0_OPB_PLB_DIV_3 0x00002000 +#define PLLMR0_OPB_PLB_DIV_4 0x00003000 -#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ -#define PLLMR0_EXB_PLB_DIV_2 0x00000000 -#define PLLMR0_EXB_PLB_DIV_3 0x00000100 -#define PLLMR0_EXB_PLB_DIV_4 0x00000200 -#define PLLMR0_EXB_PLB_DIV_5 0x00000300 +#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ +#define PLLMR0_EXB_PLB_DIV_2 0x00000000 +#define PLLMR0_EXB_PLB_DIV_3 0x00000100 +#define PLLMR0_EXB_PLB_DIV_4 0x00000200 +#define PLLMR0_EXB_PLB_DIV_5 0x00000300 -#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ -#define PLLMR0_MAL_PLB_DIV_1 0x00000000 -#define PLLMR0_MAL_PLB_DIV_2 0x00000010 -#define PLLMR0_MAL_PLB_DIV_3 0x00000020 -#define PLLMR0_MAL_PLB_DIV_4 0x00000030 +#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ +#define PLLMR0_MAL_PLB_DIV_1 0x00000000 +#define PLLMR0_MAL_PLB_DIV_2 0x00000010 +#define PLLMR0_MAL_PLB_DIV_3 0x00000020 +#define PLLMR0_MAL_PLB_DIV_4 0x00000030 -#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ -#define PLLMR0_PCI_PLB_DIV_1 0x00000000 -#define PLLMR0_PCI_PLB_DIV_2 0x00000001 -#define PLLMR0_PCI_PLB_DIV_3 0x00000002 -#define PLLMR0_PCI_PLB_DIV_4 0x00000003 +#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ +#define PLLMR0_PCI_PLB_DIV_1 0x00000000 +#define PLLMR0_PCI_PLB_DIV_2 0x00000001 +#define PLLMR0_PCI_PLB_DIV_3 0x00000002 +#define PLLMR0_PCI_PLB_DIV_4 0x00000003 -#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ -#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ -#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ -#define PLLMR1_FBMUL_DIV_16 0x00000000 -#define PLLMR1_FBMUL_DIV_1 0x00100000 -#define PLLMR1_FBMUL_DIV_2 0x00200000 -#define PLLMR1_FBMUL_DIV_3 0x00300000 -#define PLLMR1_FBMUL_DIV_4 0x00400000 -#define PLLMR1_FBMUL_DIV_5 0x00500000 -#define PLLMR1_FBMUL_DIV_6 0x00600000 -#define PLLMR1_FBMUL_DIV_7 0x00700000 -#define PLLMR1_FBMUL_DIV_8 0x00800000 -#define PLLMR1_FBMUL_DIV_9 0x00900000 -#define PLLMR1_FBMUL_DIV_10 0x00A00000 -#define PLLMR1_FBMUL_DIV_11 0x00B00000 -#define PLLMR1_FBMUL_DIV_12 0x00C00000 -#define PLLMR1_FBMUL_DIV_13 0x00D00000 -#define PLLMR1_FBMUL_DIV_14 0x00E00000 -#define PLLMR1_FBMUL_DIV_15 0x00F00000 +#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ +#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ +#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ +#define PLLMR1_FBMUL_DIV_16 0x00000000 +#define PLLMR1_FBMUL_DIV_1 0x00100000 +#define PLLMR1_FBMUL_DIV_2 0x00200000 +#define PLLMR1_FBMUL_DIV_3 0x00300000 +#define PLLMR1_FBMUL_DIV_4 0x00400000 +#define PLLMR1_FBMUL_DIV_5 0x00500000 +#define PLLMR1_FBMUL_DIV_6 0x00600000 +#define PLLMR1_FBMUL_DIV_7 0x00700000 +#define PLLMR1_FBMUL_DIV_8 0x00800000 +#define PLLMR1_FBMUL_DIV_9 0x00900000 +#define PLLMR1_FBMUL_DIV_10 0x00A00000 +#define PLLMR1_FBMUL_DIV_11 0x00B00000 +#define PLLMR1_FBMUL_DIV_12 0x00C00000 +#define PLLMR1_FBMUL_DIV_13 0x00D00000 +#define PLLMR1_FBMUL_DIV_14 0x00E00000 +#define PLLMR1_FBMUL_DIV_15 0x00F00000 -#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ -#define PLLMR1_FWDVA_DIV_8 0x00000000 -#define PLLMR1_FWDVA_DIV_7 0x00010000 -#define PLLMR1_FWDVA_DIV_6 0x00020000 -#define PLLMR1_FWDVA_DIV_5 0x00030000 -#define PLLMR1_FWDVA_DIV_4 0x00040000 -#define PLLMR1_FWDVA_DIV_3 0x00050000 -#define PLLMR1_FWDVA_DIV_2 0x00060000 -#define PLLMR1_FWDVA_DIV_1 0x00070000 -#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ -#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ +#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ +#define PLLMR1_FWDVA_DIV_8 0x00000000 +#define PLLMR1_FWDVA_DIV_7 0x00010000 +#define PLLMR1_FWDVA_DIV_6 0x00020000 +#define PLLMR1_FWDVA_DIV_5 0x00030000 +#define PLLMR1_FWDVA_DIV_4 0x00040000 +#define PLLMR1_FWDVA_DIV_3 0x00050000 +#define PLLMR1_FWDVA_DIV_2 0x00060000 +#define PLLMR1_FWDVA_DIV_1 0x00070000 +#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ +#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ /* Defines for CPC0_EPRCSR register */ -#define CPC0_EPRCSR_E0NFE 0x80000000 -#define CPC0_EPRCSR_E1NFE 0x40000000 -#define CPC0_EPRCSR_E1RPP 0x00000080 -#define CPC0_EPRCSR_E0RPP 0x00000040 -#define CPC0_EPRCSR_E1ERP 0x00000020 -#define CPC0_EPRCSR_E0ERP 0x00000010 -#define CPC0_EPRCSR_E1PCI 0x00000002 -#define CPC0_EPRCSR_E0PCI 0x00000001 +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 /* Defines for CPC0_PCI Register */ -#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ -#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ -#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ +#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ +#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ +#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ /* Defines for CPC0_BOOR Register */ -#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ +#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ /* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ +#define PLL_TUNE_MASK 0x000003FF +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ /* Defines for CPC0_PLLMR0 Register fields */ /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 /* *------------------------------------------------------------------------------- @@ -343,48 +343,48 @@ *------------------------------------------------------------------------------- */ #define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) #define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) #define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) #define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) #define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) #define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) #define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_3) -#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) #define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_1) + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_1) #define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) /* * PLL Voltage Controlled Oscillator (VCO) definitions @@ -393,57 +393,57 @@ #define VCO_MIN 500 #define VCO_MAX 1000 #elif defined(CONFIG_405EZ) -#define sdrnand0 0x4000 -#define sdrultra0 0x4040 -#define sdrultra1 0x4050 -#define sdricintstat 0x4510 +#define sdrnand0 0x4000 +#define sdrultra0 0x4040 +#define sdrultra1 0x4050 +#define sdricintstat 0x4510 -#define SDR_NAND0_NDEN 0x80000000 -#define SDR_NAND0_NDBTEN 0x40000000 -#define SDR_NAND0_NDBADR_MASK 0x30000000 -#define SDR_NAND0_NDBPG_MASK 0x0f000000 -#define SDR_NAND0_NDAREN 0x00800000 -#define SDR_NAND0_NDRBEN 0x00400000 +#define SDR_NAND0_NDEN 0x80000000 +#define SDR_NAND0_NDBTEN 0x40000000 +#define SDR_NAND0_NDBADR_MASK 0x30000000 +#define SDR_NAND0_NDBPG_MASK 0x0f000000 +#define SDR_NAND0_NDAREN 0x00800000 +#define SDR_NAND0_NDRBEN 0x00400000 -#define SDR_ULTRA0_NDGPIOBP 0x80000000 -#define SDR_ULTRA0_CSN_MASK 0x78000000 -#define SDR_ULTRA0_CSNSEL0 0x40000000 -#define SDR_ULTRA0_CSNSEL1 0x20000000 -#define SDR_ULTRA0_CSNSEL2 0x10000000 -#define SDR_ULTRA0_CSNSEL3 0x08000000 -#define SDR_ULTRA0_EBCRDYEN 0x04000000 -#define SDR_ULTRA0_SPISSINEN 0x02000000 -#define SDR_ULTRA0_NFSRSTEN 0x01000000 +#define SDR_ULTRA0_NDGPIOBP 0x80000000 +#define SDR_ULTRA0_CSN_MASK 0x78000000 +#define SDR_ULTRA0_CSNSEL0 0x40000000 +#define SDR_ULTRA0_CSNSEL1 0x20000000 +#define SDR_ULTRA0_CSNSEL2 0x10000000 +#define SDR_ULTRA0_CSNSEL3 0x08000000 +#define SDR_ULTRA0_EBCRDYEN 0x04000000 +#define SDR_ULTRA0_SPISSINEN 0x02000000 +#define SDR_ULTRA0_NFSRSTEN 0x01000000 -#define SDR_ULTRA1_LEDNENABLE 0x40000000 +#define SDR_ULTRA1_LEDNENABLE 0x40000000 -#define SDR_ICRX_STAT 0x80000000 -#define SDR_ICTX0_STAT 0x40000000 -#define SDR_ICTX1_STAT 0x20000000 +#define SDR_ICRX_STAT 0x80000000 +#define SDR_ICTX0_STAT 0x40000000 +#define SDR_ICTX1_STAT 0x20000000 -#define SDR_PINSTP 0x40 +#define SDR_PINSTP 0x40 /****************************************************************************** * Control ******************************************************************************/ /* CPR Registers */ -#define cprclkupd 0x020 /* CPR_CLKUPD */ -#define cprpllc 0x040 /* CPR_PLLC */ -#define cprplld 0x060 /* CPR_PLLD */ -#define cprprimad 0x080 /* CPR_PRIMAD */ -#define cprperd0 0x0e0 /* CPR_PERD0 */ -#define cprperd1 0x0e1 /* CPR_PERD1 */ -#define cprperc0 0x180 /* CPR_PERC0 */ -#define cprmisc0 0x181 /* CPR_MISC0 */ -#define cprmisc1 0x182 /* CPR_MISC1 */ +#define cprclkupd 0x020 /* CPR_CLKUPD */ +#define cprpllc 0x040 /* CPR_PLLC */ +#define cprplld 0x060 /* CPR_PLLD */ +#define cprprimad 0x080 /* CPR_PRIMAD */ +#define cprperd0 0x0e0 /* CPR_PERD0 */ +#define cprperd1 0x0e1 /* CPR_PERD1 */ +#define cprperc0 0x180 /* CPR_PERC0 */ +#define cprmisc0 0x181 /* CPR_MISC0 */ +#define cprmisc1 0x182 /* CPR_MISC1 */ #define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ #define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ #define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ -#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ -#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ +#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ #define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ #define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ @@ -462,77 +462,77 @@ * Control ******************************************************************************/ #define CNTRL_DCR_BASE 0x0b0 -#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ -#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ -#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ -#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ -#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ +#define pllmd (CNTRL_DCR_BASE+0x0) /* PLL mode register */ +#define cntrl0 (CNTRL_DCR_BASE+0x1) /* Control 0 register */ +#define cntrl1 (CNTRL_DCR_BASE+0x2) /* Control 1 register */ +#define reset (CNTRL_DCR_BASE+0x3) /* reset register */ +#define strap (CNTRL_DCR_BASE+0x4) /* strap register */ -#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ -#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ +#define CPC0_CR0 (CNTRL_DCR_BASE+0x1) /* chip control register 0 */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* chip control register 1 */ +#define CPC0_PSR (CNTRL_DCR_BASE+0x4) /* chip pin strapping register */ /* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ -#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ -#define CPC0_ECR (0xaa) /* edge conditioner register */ +#define CPC0_EIRR (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ +#define CPC0_ECR (0xaa) /* edge conditioner register */ -#define ecr (0xaa) /* edge conditioner register (405gpr) */ +#define ecr (0xaa) /* edge conditioner register (405gpr) */ /* Bit definitions */ -#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ -#define PLLMR_FWD_DIV_BYPASS 0xE0000000 -#define PLLMR_FWD_DIV_3 0xA0000000 -#define PLLMR_FWD_DIV_4 0x80000000 -#define PLLMR_FWD_DIV_6 0x40000000 +#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ +#define PLLMR_FWD_DIV_BYPASS 0xE0000000 +#define PLLMR_FWD_DIV_3 0xA0000000 +#define PLLMR_FWD_DIV_4 0x80000000 +#define PLLMR_FWD_DIV_6 0x40000000 -#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ -#define PLLMR_FB_DIV_1 0x02000000 -#define PLLMR_FB_DIV_2 0x04000000 -#define PLLMR_FB_DIV_3 0x06000000 -#define PLLMR_FB_DIV_4 0x08000000 +#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ +#define PLLMR_FB_DIV_1 0x02000000 +#define PLLMR_FB_DIV_2 0x04000000 +#define PLLMR_FB_DIV_3 0x06000000 +#define PLLMR_FB_DIV_4 0x08000000 -#define PLLMR_TUNING_MASK 0x01F80000 +#define PLLMR_TUNING_MASK 0x01F80000 -#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ -#define PLLMR_CPU_PLB_DIV_1 0x00000000 -#define PLLMR_CPU_PLB_DIV_2 0x00020000 -#define PLLMR_CPU_PLB_DIV_3 0x00040000 -#define PLLMR_CPU_PLB_DIV_4 0x00060000 +#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ +#define PLLMR_CPU_PLB_DIV_1 0x00000000 +#define PLLMR_CPU_PLB_DIV_2 0x00020000 +#define PLLMR_CPU_PLB_DIV_3 0x00040000 +#define PLLMR_CPU_PLB_DIV_4 0x00060000 -#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ -#define PLLMR_OPB_PLB_DIV_1 0x00000000 -#define PLLMR_OPB_PLB_DIV_2 0x00008000 -#define PLLMR_OPB_PLB_DIV_3 0x00010000 -#define PLLMR_OPB_PLB_DIV_4 0x00018000 +#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ +#define PLLMR_OPB_PLB_DIV_1 0x00000000 +#define PLLMR_OPB_PLB_DIV_2 0x00008000 +#define PLLMR_OPB_PLB_DIV_3 0x00010000 +#define PLLMR_OPB_PLB_DIV_4 0x00018000 -#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ -#define PLLMR_PCI_PLB_DIV_1 0x00000000 -#define PLLMR_PCI_PLB_DIV_2 0x00002000 -#define PLLMR_PCI_PLB_DIV_3 0x00004000 -#define PLLMR_PCI_PLB_DIV_4 0x00006000 +#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ +#define PLLMR_PCI_PLB_DIV_1 0x00000000 +#define PLLMR_PCI_PLB_DIV_2 0x00002000 +#define PLLMR_PCI_PLB_DIV_3 0x00004000 +#define PLLMR_PCI_PLB_DIV_4 0x00006000 -#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ -#define PLLMR_EXB_PLB_DIV_2 0x00000000 -#define PLLMR_EXB_PLB_DIV_3 0x00000800 -#define PLLMR_EXB_PLB_DIV_4 0x00001000 -#define PLLMR_EXB_PLB_DIV_5 0x00001800 +#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ +#define PLLMR_EXB_PLB_DIV_2 0x00000000 +#define PLLMR_EXB_PLB_DIV_3 0x00000800 +#define PLLMR_EXB_PLB_DIV_4 0x00001000 +#define PLLMR_EXB_PLB_DIV_5 0x00001800 /* definitions for PPC405GPr (new mode strapping) */ -#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ +#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ -#define PSR_PLL_FWD_MASK 0xC0000000 -#define PSR_PLL_FDBACK_MASK 0x30000000 -#define PSR_PLL_TUNING_MASK 0x0E000000 -#define PSR_PLB_CPU_MASK 0x01800000 -#define PSR_OPB_PLB_MASK 0x00600000 -#define PSR_PCI_PLB_MASK 0x00180000 -#define PSR_EB_PLB_MASK 0x00060000 -#define PSR_ROM_WIDTH_MASK 0x00018000 -#define PSR_ROM_LOC 0x00004000 -#define PSR_PCI_ASYNC_EN 0x00001000 +#define PSR_PLL_FWD_MASK 0xC0000000 +#define PSR_PLL_FDBACK_MASK 0x30000000 +#define PSR_PLL_TUNING_MASK 0x0E000000 +#define PSR_PLB_CPU_MASK 0x01800000 +#define PSR_OPB_PLB_MASK 0x00600000 +#define PSR_PCI_PLB_MASK 0x00180000 +#define PSR_EB_PLB_MASK 0x00060000 +#define PSR_ROM_WIDTH_MASK 0x00018000 +#define PSR_ROM_LOC 0x00004000 +#define PSR_PCI_ASYNC_EN 0x00001000 #define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ -#define PSR_PCI_ARBIT_EN 0x00000400 -#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ +#define PSR_PCI_ARBIT_EN 0x00000400 +#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ #ifndef CONFIG_IOP480 /* @@ -548,201 +548,201 @@ * Memory Access Layer ******************************************************************************/ #if defined(CONFIG_405EZ) -#define MAL_DCR_BASE 0x380 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ -#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -/* 0x08-0x0F Reserved */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ -#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -/* 0x14-0x1F Reserved */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ -#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ -#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ -#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ -#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ -#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ -#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ -#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ -#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ -#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ -#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ -#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ -#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ -#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ -#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ -#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ -#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ -#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ -#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ -#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ -#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ -#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ -#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ -#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ -#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ -#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ -#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ -#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ -#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ -#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ -#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ -#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ -#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ -#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ -#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ -#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ -#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ -#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ -#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ -#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ -#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ -#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ -#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ -#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ -#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ -#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ -#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ -#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ -#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ -#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ -#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ -#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ -#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ -#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ -#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ -#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ -#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ -#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ -#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ -#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ -#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ -#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ -#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ -#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ -#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ -#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ -#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ -#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ -#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ -#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ -#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ -#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ -#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ -#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ -#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ -#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ -#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ -#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ -#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ -#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ -#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ -#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ -#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ -#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ -#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ -#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ -#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ -#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ -#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ -#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ +#define MAL_DCR_BASE 0x380 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +/* 0x08-0x0F Reserved */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +/* 0x14-0x1F Reserved */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ +#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ +#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ +#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ +#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ +#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ +#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ +#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ +#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ +#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ +#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ +#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ +#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ +#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ +#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ +#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ +#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ +#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ +#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ +#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ +#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ +#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ +#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ +#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ +#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ +#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ +#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ +#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ +#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ +#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ +#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ +#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ +#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ +#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ +#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ +#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ +#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ +#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ +#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ +#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ +#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ +#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ +#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ +#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ +#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ +#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ +#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ +#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ +#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ +#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ +#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ +#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ +#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ +#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ +#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ +#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ +#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ +#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ +#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ +#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ +#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ +#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ +#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ +#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ +#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ +#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ +#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ +#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ +#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ +#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ +#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ +#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ +#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ +#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ +#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ +#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ +#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ +#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ +#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ +#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ +#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ +#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ +#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ +#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ +#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ +#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ +#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ #else /* !defined(CONFIG_405EZ) */ #define MAL_DCR_BASE 0x180 -#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ -#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ -#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ -#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ -#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ -#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set) */ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ #define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ -#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ -#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ -#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set) */ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ #define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ -#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ -#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ -#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ -#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ -#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ -#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ -#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ -#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table pointer reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table pointer reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table pointer reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table pointer reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ #endif /* defined(CONFIG_405EZ) */ /*----------------------------------------------------------------------------- | IIC Register Offsets '----------------------------------------------------------------------------*/ -#define IICMDBUF 0x00 -#define IICSDBUF 0x02 -#define IICLMADR 0x04 -#define IICHMADR 0x05 -#define IICCNTL 0x06 -#define IICMDCNTL 0x07 -#define IICSTS 0x08 -#define IICEXTSTS 0x09 -#define IICLSADR 0x0A -#define IICHSADR 0x0B -#define IICCLKDIV 0x0C -#define IICINTRMSK 0x0D -#define IICXFRCNT 0x0E -#define IICXTCNTLSS 0x0F +#define IICMDBUF 0x00 +#define IICSDBUF 0x02 +#define IICLMADR 0x04 +#define IICHMADR 0x05 +#define IICCNTL 0x06 +#define IICMDCNTL 0x07 +#define IICSTS 0x08 +#define IICEXTSTS 0x09 +#define IICLSADR 0x0A +#define IICHSADR 0x0B +#define IICCLKDIV 0x0C +#define IICINTRMSK 0x0D +#define IICXFRCNT 0x0E +#define IICXTCNTLSS 0x0F #define IICDIRECTCNTL 0x10 /*----------------------------------------------------------------------------- | UART Register Offsets '----------------------------------------------------------------------------*/ -#define DATA_REG 0x00 -#define DL_LSB 0x00 -#define DL_MSB 0x01 -#define INT_ENABLE 0x01 -#define FIFO_CONTROL 0x02 -#define LINE_CONTROL 0x03 -#define MODEM_CONTROL 0x04 -#define LINE_STATUS 0x05 -#define MODEM_STATUS 0x06 -#define SCRATCH 0x07 +#define DATA_REG 0x00 +#define DL_LSB 0x00 +#define DL_MSB 0x01 +#define INT_ENABLE 0x01 +#define FIFO_CONTROL 0x02 +#define LINE_CONTROL 0x03 +#define MODEM_CONTROL 0x04 +#define LINE_STATUS 0x05 +#define MODEM_STATUS 0x06 +#define SCRATCH 0x07 /****************************************************************************** * On Chip Memory ******************************************************************************/ #if defined(CONFIG_405EZ) #define OCM_DCR_BASE 0x020 -#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ -#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ -#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ -#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ -#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ -#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ -#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ -#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ -#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ -#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ -#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ -#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ -#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ -#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ -#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ +#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ +#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ +#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ +#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ +#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ +#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ +#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ +#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ +#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ +#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ +#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ +#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ +#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ +#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ +#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ #else #define OCM_DCR_BASE 0x018 -#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ -#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ -#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ -#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ +#define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ +#define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ +#define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ +#define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ #endif /* CONFIG_405EZ */ /****************************************************************************** @@ -751,154 +751,154 @@ #if defined(CONFIG_405EZ) /* Only the 405EZ has 2 GPIOs */ #define GPIO_BASE 0xEF600700 -#define GPIO0_OR (GPIO_BASE+0x0) -#define GPIO0_TCR (GPIO_BASE+0x4) -#define GPIO0_OSRL (GPIO_BASE+0x8) -#define GPIO0_OSRH (GPIO_BASE+0xC) -#define GPIO0_TSRL (GPIO_BASE+0x10) -#define GPIO0_TSRH (GPIO_BASE+0x14) -#define GPIO0_ODR (GPIO_BASE+0x18) -#define GPIO0_IR (GPIO_BASE+0x1C) -#define GPIO0_RR1 (GPIO_BASE+0x20) -#define GPIO0_RR2 (GPIO_BASE+0x24) -#define GPIO0_RR3 (GPIO_BASE+0x28) -#define GPIO0_ISR1L (GPIO_BASE+0x30) -#define GPIO0_ISR1H (GPIO_BASE+0x34) -#define GPIO0_ISR2L (GPIO_BASE+0x38) -#define GPIO0_ISR2H (GPIO_BASE+0x3C) -#define GPIO0_ISR3L (GPIO_BASE+0x40) -#define GPIO0_ISR3H (GPIO_BASE+0x44) +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_RR3 (GPIO_BASE+0x28) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) #define GPIO1_BASE 0xEF600800 -#define GPIO1_OR (GPIO1_BASE+0x0) -#define GPIO1_TCR (GPIO1_BASE+0x4) -#define GPIO1_OSRL (GPIO1_BASE+0x8) -#define GPIO1_OSRH (GPIO1_BASE+0xC) -#define GPIO1_TSRL (GPIO1_BASE+0x10) -#define GPIO1_TSRH (GPIO1_BASE+0x14) -#define GPIO1_ODR (GPIO1_BASE+0x18) -#define GPIO1_IR (GPIO1_BASE+0x1C) -#define GPIO1_RR1 (GPIO1_BASE+0x20) -#define GPIO1_RR2 (GPIO1_BASE+0x24) -#define GPIO1_RR3 (GPIO1_BASE+0x28) -#define GPIO1_ISR1L (GPIO1_BASE+0x30) -#define GPIO1_ISR1H (GPIO1_BASE+0x34) -#define GPIO1_ISR2L (GPIO1_BASE+0x38) -#define GPIO1_ISR2H (GPIO1_BASE+0x3C) -#define GPIO1_ISR3L (GPIO1_BASE+0x40) -#define GPIO1_ISR3H (GPIO1_BASE+0x44) +#define GPIO1_OR (GPIO1_BASE+0x0) +#define GPIO1_TCR (GPIO1_BASE+0x4) +#define GPIO1_OSRL (GPIO1_BASE+0x8) +#define GPIO1_OSRH (GPIO1_BASE+0xC) +#define GPIO1_TSRL (GPIO1_BASE+0x10) +#define GPIO1_TSRH (GPIO1_BASE+0x14) +#define GPIO1_ODR (GPIO1_BASE+0x18) +#define GPIO1_IR (GPIO1_BASE+0x1C) +#define GPIO1_RR1 (GPIO1_BASE+0x20) +#define GPIO1_RR2 (GPIO1_BASE+0x24) +#define GPIO1_RR3 (GPIO1_BASE+0x28) +#define GPIO1_ISR1L (GPIO1_BASE+0x30) +#define GPIO1_ISR1H (GPIO1_BASE+0x34) +#define GPIO1_ISR2L (GPIO1_BASE+0x38) +#define GPIO1_ISR2H (GPIO1_BASE+0x3C) +#define GPIO1_ISR3L (GPIO1_BASE+0x40) +#define GPIO1_ISR3H (GPIO1_BASE+0x44) #elif defined(CONFIG_405EX) #define GPIO_BASE 0xEF600800 -#define GPIO0_OR (GPIO_BASE+0x0) -#define GPIO0_TCR (GPIO_BASE+0x4) -#define GPIO0_OSRL (GPIO_BASE+0x8) -#define GPIO0_OSRH (GPIO_BASE+0xC) -#define GPIO0_TSRL (GPIO_BASE+0x10) -#define GPIO0_TSRH (GPIO_BASE+0x14) -#define GPIO0_ODR (GPIO_BASE+0x18) -#define GPIO0_IR (GPIO_BASE+0x1C) -#define GPIO0_RR1 (GPIO_BASE+0x20) -#define GPIO0_RR2 (GPIO_BASE+0x24) -#define GPIO0_ISR1L (GPIO_BASE+0x30) -#define GPIO0_ISR1H (GPIO_BASE+0x34) -#define GPIO0_ISR2L (GPIO_BASE+0x38) -#define GPIO0_ISR2H (GPIO_BASE+0x3C) -#define GPIO0_ISR3L (GPIO_BASE+0x40) -#define GPIO0_ISR3H (GPIO_BASE+0x44) +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) -#else /* !405EZ */ +#else /* !405EZ */ #define GPIO_BASE 0xEF600700 -#define GPIO0_OR (GPIO_BASE+0x0) -#define GPIO0_TCR (GPIO_BASE+0x4) -#define GPIO0_OSRH (GPIO_BASE+0x8) -#define GPIO0_OSRL (GPIO_BASE+0xC) -#define GPIO0_TSRH (GPIO_BASE+0x10) -#define GPIO0_TSRL (GPIO_BASE+0x14) -#define GPIO0_ODR (GPIO_BASE+0x18) -#define GPIO0_IR (GPIO_BASE+0x1C) -#define GPIO0_RR1 (GPIO_BASE+0x20) -#define GPIO0_RR2 (GPIO_BASE+0x24) -#define GPIO0_ISR1H (GPIO_BASE+0x30) -#define GPIO0_ISR1L (GPIO_BASE+0x34) -#define GPIO0_ISR2H (GPIO_BASE+0x38) -#define GPIO0_ISR2L (GPIO_BASE+0x3C) +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRH (GPIO_BASE+0x8) +#define GPIO0_OSRL (GPIO_BASE+0xC) +#define GPIO0_TSRH (GPIO_BASE+0x10) +#define GPIO0_TSRL (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_ISR1H (GPIO_BASE+0x30) +#define GPIO0_ISR1L (GPIO_BASE+0x34) +#define GPIO0_ISR2H (GPIO_BASE+0x38) +#define GPIO0_ISR2L (GPIO_BASE+0x3C) #endif /* CONFIG_405EZ */ -#define GPIO0_BASE GPIO_BASE +#define GPIO0_BASE GPIO_BASE #if defined(CONFIG_405EX) -#define SDR0_SRST 0x0200 +#define SDR0_SRST 0x0200 /* * Software Reset Register */ -#define SDR0_SRST_BGO PPC_REG_VAL(0, 1) -#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1) -#define SDR0_SRST_EBC PPC_REG_VAL(2, 1) -#define SDR0_SRST_OPB PPC_REG_VAL(3, 1) -#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1) -#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1) -#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1) -#define SDR0_SRST_BGI PPC_REG_VAL(7, 1) -#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1) -#define SDR0_SRST_GPT PPC_REG_VAL(9, 1) -#define SDR0_SRST_DMC PPC_REG_VAL(10, 1) -#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1) -#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1) -#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1) -#define SDR0_SRST_CPM PPC_REG_VAL(14, 1) -#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1) -#define SDR0_SRST_UIC PPC_REG_VAL(16, 1) -#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1) -#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1) -#define SDR0_SRST_SCP PPC_REG_VAL(19, 1) -#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1) -#define SDR0_SRST_DMA PPC_REG_VAL(21, 1) -#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1) -#define SDR0_SRST_MAL PPC_REG_VAL(23, 1) -#define SDR0_SRST_EBM PPC_REG_VAL(24, 1) -#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1) -#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1) -#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1) -#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1) -#define SDR0_SRST_PKP PPC_REG_VAL(29, 1) -#define SDR0_SRST_AHB PPC_REG_VAL(30, 1) -#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) +#define SDR0_SRST_BGO PPC_REG_VAL(0, 1) +#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1) +#define SDR0_SRST_EBC PPC_REG_VAL(2, 1) +#define SDR0_SRST_OPB PPC_REG_VAL(3, 1) +#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1) +#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1) +#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1) +#define SDR0_SRST_BGI PPC_REG_VAL(7, 1) +#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1) +#define SDR0_SRST_GPT PPC_REG_VAL(9, 1) +#define SDR0_SRST_DMC PPC_REG_VAL(10, 1) +#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1) +#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1) +#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1) +#define SDR0_SRST_CPM PPC_REG_VAL(14, 1) +#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1) +#define SDR0_SRST_UIC PPC_REG_VAL(16, 1) +#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1) +#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1) +#define SDR0_SRST_SCP PPC_REG_VAL(19, 1) +#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1) +#define SDR0_SRST_DMA PPC_REG_VAL(21, 1) +#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1) +#define SDR0_SRST_MAL PPC_REG_VAL(23, 1) +#define SDR0_SRST_EBM PPC_REG_VAL(24, 1) +#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1) +#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1) +#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1) +#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1) +#define SDR0_SRST_PKP PPC_REG_VAL(29, 1) +#define SDR0_SRST_AHB PPC_REG_VAL(30, 1) +#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) -#define sdr_uart0 0x0120 /* UART0 Config */ -#define sdr_uart1 0x0121 /* UART1 Config */ -#define sdr_mfr 0x4300 /* SDR0_MFR reg */ +#define sdr_uart0 0x0120 /* UART0 Config */ +#define sdr_uart1 0x0121 /* UART1 Config */ +#define sdr_mfr 0x4300 /* SDR0_MFR reg */ /* Defines for CPC0_EPRCSR register */ -#define CPC0_EPRCSR_E0NFE 0x80000000 -#define CPC0_EPRCSR_E1NFE 0x40000000 -#define CPC0_EPRCSR_E1RPP 0x00000080 -#define CPC0_EPRCSR_E0RPP 0x00000040 -#define CPC0_EPRCSR_E1ERP 0x00000020 -#define CPC0_EPRCSR_E0ERP 0x00000010 -#define CPC0_EPRCSR_E1PCI 0x00000002 -#define CPC0_EPRCSR_E0PCI 0x00000001 +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 -#define cpr0_clkupd 0x020 -#define cpr0_pllc 0x040 -#define cpr0_plld 0x060 -#define cpr0_cpud 0x080 -#define cpr0_plbd 0x0a0 -#define cpr0_opbd 0x0c0 -#define cpr0_perd 0x0e0 -#define cpr0_ahbd 0x100 -#define cpr0_icfg 0x140 +#define cpr0_clkupd 0x020 +#define cpr0_pllc 0x040 +#define cpr0_plld 0x060 +#define cpr0_cpud 0x080 +#define cpr0_plbd 0x0a0 +#define cpr0_opbd 0x0c0 +#define cpr0_perd 0x0e0 +#define cpr0_ahbd 0x100 +#define cpr0_icfg 0x140 -#define SDR_PINSTP 0x0040 -#define sdr_sdcs 0x0060 +#define SDR_PINSTP 0x0040 +#define sdr_sdcs 0x0060 -#define SDR0_SDCS_SDD (0x80000000 >> 31) +#define SDR0_SDCS_SDD (0x80000000 >> 31) /* CUST0 Customer Configuration Register0 */ -#define SDR0_CUST0 0x4000 +#define SDR0_CUST0 0x4000 #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ @@ -924,9 +924,9 @@ #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ -#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ -#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ -#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ #define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) @@ -940,41 +940,41 @@ #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ -#define SDR0_PFC0 0x4100 -#define SDR0_PFC1 0x4101 -#define SDR0_PFC1_U1ME 0x02000000 -#define SDR0_PFC1_U0ME 0x00080000 -#define SDR0_PFC1_U0IM 0x00040000 -#define SDR0_PFC1_SIS 0x00020000 -#define SDR0_PFC1_DMAAEN 0x00010000 -#define SDR0_PFC1_DMADEN 0x00008000 -#define SDR0_PFC1_USBEN 0x00004000 -#define SDR0_PFC1_AHBSWAP 0x00000020 -#define SDR0_PFC1_USBBIGEN 0x00000010 -#define SDR0_PFC1_GPT_FREQ 0x0000000f +#define SDR0_PFC0 0x4100 +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME 0x02000000 +#define SDR0_PFC1_U0ME 0x00080000 +#define SDR0_PFC1_U0IM 0x00040000 +#define SDR0_PFC1_SIS 0x00020000 +#define SDR0_PFC1_DMAAEN 0x00010000 +#define SDR0_PFC1_DMADEN 0x00008000 +#define SDR0_PFC1_USBEN 0x00004000 +#define SDR0_PFC1_AHBSWAP 0x00000020 +#define SDR0_PFC1_USBBIGEN 0x00000010 +#define SDR0_PFC1_GPT_FREQ 0x0000000f #endif /* General Purpose Timer (GPT) Register Offsets */ -#define GPT0_TBC 0x00000000 -#define GPT0_IM 0x00000018 -#define GPT0_ISS 0x0000001C -#define GPT0_ISC 0x00000020 -#define GPT0_IE 0x00000024 -#define GPT0_COMP0 0x00000080 -#define GPT0_COMP1 0x00000084 -#define GPT0_COMP2 0x00000088 -#define GPT0_COMP3 0x0000008C -#define GPT0_COMP4 0x00000090 -#define GPT0_COMP5 0x00000094 -#define GPT0_COMP6 0x00000098 -#define GPT0_MASK0 0x000000C0 -#define GPT0_MASK1 0x000000C4 -#define GPT0_MASK2 0x000000C8 -#define GPT0_MASK3 0x000000CC -#define GPT0_MASK4 0x000000D0 -#define GPT0_MASK5 0x000000D4 -#define GPT0_MASK6 0x000000D8 -#define GPT0_DCT0 0x00000110 -#define GPT0_DCIS 0x0000011C +#define GPT0_TBC 0x00000000 +#define GPT0_IM 0x00000018 +#define GPT0_ISS 0x0000001C +#define GPT0_ISC 0x00000020 +#define GPT0_IE 0x00000024 +#define GPT0_COMP0 0x00000080 +#define GPT0_COMP1 0x00000084 +#define GPT0_COMP2 0x00000088 +#define GPT0_COMP3 0x0000008C +#define GPT0_COMP4 0x00000090 +#define GPT0_COMP5 0x00000094 +#define GPT0_COMP6 0x00000098 +#define GPT0_MASK0 0x000000C0 +#define GPT0_MASK1 0x000000C4 +#define GPT0_MASK2 0x000000C8 +#define GPT0_MASK3 0x000000CC +#define GPT0_MASK4 0x000000D0 +#define GPT0_MASK5 0x000000D4 +#define GPT0_MASK6 0x000000D8 +#define GPT0_DCT0 0x00000110 +#define GPT0_DCIS 0x0000011C -#endif /* __PPC405_H__ */ +#endif /* __PPC405_H__ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h b/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h index cdb542c2da..83b55e5e64 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h +++ b/libcpu/ppc/ppc405/include/asm/ppc4xx-uic.h @@ -4,8 +4,8 @@ /* * Define the number of UIC's */ -#define UIC_MAX 1 -#define IRQ_MAX UIC_MAX * 32 +#define UIC_MAX 1 +#define IRQ_MAX UIC_MAX * 32 /* UIC0 dcr base address */ #define UIC0_DCR_BASE 0xc0 @@ -13,49 +13,49 @@ /* * UIC register */ -#define UIC_SR 0x0 /* UIC status */ -#define UIC_ER 0x2 /* UIC enable */ -#define UIC_CR 0x3 /* UIC critical */ -#define UIC_PR 0x4 /* UIC polarity */ -#define UIC_TR 0x5 /* UIC triggering */ -#define UIC_MSR 0x6 /* UIC masked status */ -#define UIC_VR 0x7 /* UIC vector */ -#define UIC_VCR 0x8 /* UIC vector configuration */ +#define UIC_SR 0x0 /* UIC status */ +#define UIC_ER 0x2 /* UIC enable */ +#define UIC_CR 0x3 /* UIC critical */ +#define UIC_PR 0x4 /* UIC polarity */ +#define UIC_TR 0x5 /* UIC triggering */ +#define UIC_MSR 0x6 /* UIC masked status */ +#define UIC_VR 0x7 /* UIC vector */ +#define UIC_VCR 0x8 /* UIC vector configuration */ -#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ -#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ -#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ -#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ -#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ -#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ -#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ -#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ +#define uic0sr (UIC0_DCR_BASE+0x0) /* UIC0 status */ +#define uic0er (UIC0_DCR_BASE+0x2) /* UIC0 enable */ +#define uic0cr (UIC0_DCR_BASE+0x3) /* UIC0 critical */ +#define uic0pr (UIC0_DCR_BASE+0x4) /* UIC0 polarity */ +#define uic0tr (UIC0_DCR_BASE+0x5) /* UIC0 triggering */ +#define uic0msr (UIC0_DCR_BASE+0x6) /* UIC0 masked status */ +#define uic0vr (UIC0_DCR_BASE+0x7) /* UIC0 vector */ +#define uic0vcr (UIC0_DCR_BASE+0x8) /* UIC0 vector configuration */ /* The following is for compatibility with 405 code */ -#define uicsr uic0sr -#define uicer uic0er -#define uiccr uic0cr -#define uicpr uic0pr -#define uictr uic0tr -#define uicmsr uic0msr -#define uicvr uic0vr -#define uicvcr uic0vcr +#define uicsr uic0sr +#define uicer uic0er +#define uiccr uic0cr +#define uicpr uic0pr +#define uictr uic0tr +#define uicmsr uic0msr +#define uicvr uic0vr +#define uicvcr uic0vcr /* the interrupt vector definitions */ -#define VECNUM_MAL_SERR 10 -#define VECNUM_MAL_TXEOB 11 -#define VECNUM_MAL_RXEOB 12 -#define VECNUM_MAL_TXDE 13 -#define VECNUM_MAL_RXDE 14 -#define VECNUM_ETH0 15 -#define VECNUM_ETH1_OFFS 2 -#define VECNUM_EIRQ6 29 +#define VECNUM_MAL_SERR 10 +#define VECNUM_MAL_TXEOB 11 +#define VECNUM_MAL_RXEOB 12 +#define VECNUM_MAL_TXDE 13 +#define VECNUM_MAL_RXDE 14 +#define VECNUM_ETH0 15 +#define VECNUM_ETH1_OFFS 2 +#define VECNUM_EIRQ6 29 /* * Mask definitions (used for example in 4xx_enet.c) */ -#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) +#define UIC_MASK(vec) (0x80000000 >> ((vec) & 0x1f)) /* UIC_NR won't work for 440GX because of its specific UIC DCR addresses */ -#define UIC_NR(vec) ((vec) >> 5) +#define UIC_NR(vec) ((vec) >> 5) #endif /* _PPC4xx_UIC_H_ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc4xx.h b/libcpu/ppc/ppc405/include/asm/ppc4xx.h index 57fe7ab221..2bfef123d6 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc4xx.h +++ b/libcpu/ppc/ppc405/include/asm/ppc4xx.h @@ -19,13 +19,13 @@ | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M +----------------------------------------------------------------------------*/ -#ifndef __PPC4XX_H__ +#ifndef __PPC4XX_H__ #define __PPC4XX_H__ /* * Configure which SDRAM/DDR/DDR2 controller is equipped */ -#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ +#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ #include <asm/ppc405.h> #include <asm/ppc4xx-uic.h> @@ -33,102 +33,102 @@ /* * Macro for generating register field mnemonics */ -#define PPC_REG_BITS 32 -#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) +#define PPC_REG_BITS 32 +#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) /* * Elide casts when assembling register mnemonics */ #ifndef __ASSEMBLY__ -#define static_cast(type, val) (type)(val) +#define static_cast(type, val) (type)(val) #else -#define static_cast(type, val) (val) +#define static_cast(type, val) (val) #endif /* * Common stuff for 4xx (405 and 440) */ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) -#define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache - line aligned data. */ +#define RESET_VECTOR 0xfffffffc +#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache + line aligned data. */ -#define CPR0_DCR_BASE 0x0C -#define cprcfga (CPR0_DCR_BASE+0x0) -#define cprcfgd (CPR0_DCR_BASE+0x1) +#define CPR0_DCR_BASE 0x0C +#define cprcfga (CPR0_DCR_BASE+0x0) +#define cprcfgd (CPR0_DCR_BASE+0x1) -#define SDR_DCR_BASE 0x0E -#define sdrcfga (SDR_DCR_BASE+0x0) -#define sdrcfgd (SDR_DCR_BASE+0x1) +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) +#define sdrcfgd (SDR_DCR_BASE+0x1) -#define SDRAM_DCR_BASE 0x10 -#define memcfga (SDRAM_DCR_BASE+0x0) -#define memcfgd (SDRAM_DCR_BASE+0x1) +#define SDRAM_DCR_BASE 0x10 +#define memcfga (SDRAM_DCR_BASE+0x0) +#define memcfgd (SDRAM_DCR_BASE+0x1) -#define EBC_DCR_BASE 0x12 -#define ebccfga (EBC_DCR_BASE+0x0) -#define ebccfgd (EBC_DCR_BASE+0x1) +#define EBC_DCR_BASE 0x12 +#define ebccfga (EBC_DCR_BASE+0x0) +#define ebccfgd (EBC_DCR_BASE+0x1) /* * Macros for indirect DCR access */ -#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) -#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) +#define mtcpr(reg, d) do { mtdcr(cprcfga,reg);mtdcr(cprcfgd,d); } while (0) +#define mfcpr(reg, d) do { mtdcr(cprcfga,reg);d = mfdcr(cprcfgd); } while (0) -#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) -#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) +#define mtebc(reg, d) do { mtdcr(ebccfga,reg);mtdcr(ebccfgd,d); } while (0) +#define mfebc(reg, d) do { mtdcr(ebccfga,reg);d = mfdcr(ebccfgd); } while (0) -#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) -#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) +#define mtsdram(reg, d) do { mtdcr(memcfga,reg);mtdcr(memcfgd,d); } while (0) +#define mfsdram(reg, d) do { mtdcr(memcfga,reg);d = mfdcr(memcfgd); } while (0) -#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) -#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) +#define mtsdr(reg, d) do { mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,d); } while (0) +#define mfsdr(reg, d) do { mtdcr(sdrcfga,reg);d = mfdcr(sdrcfgd); } while (0) #ifndef __ASSEMBLY__ typedef struct { - unsigned long freqDDR; - unsigned long freqEBC; - unsigned long freqOPB; - unsigned long freqPCI; - unsigned long freqPLB; - unsigned long freqTmrClk; - unsigned long freqUART; - unsigned long freqProcessor; - unsigned long freqVCOHz; - unsigned long freqVCOMhz; /* in MHz */ - unsigned long pciClkSync; /* PCI clock is synchronous */ - unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ - unsigned long pllExtBusDiv; - unsigned long pllFbkDiv; - unsigned long pllFwdDiv; - unsigned long pllFwdDivA; - unsigned long pllFwdDivB; - unsigned long pllOpbDiv; - unsigned long pllPciDiv; - unsigned long pllPlbDiv; + unsigned long freqDDR; + unsigned long freqEBC; + unsigned long freqOPB; + unsigned long freqPCI; + unsigned long freqPLB; + unsigned long freqTmrClk; + unsigned long freqUART; + unsigned long freqProcessor; + unsigned long freqVCOHz; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long pciClkSync; /* PCI clock is synchronous */ + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pllExtBusDiv; + unsigned long pllFbkDiv; + unsigned long pllFwdDiv; + unsigned long pllFwdDivA; + unsigned long pllFwdDivB; + unsigned long pllOpbDiv; + unsigned long pllPciDiv; + unsigned long pllPlbDiv; } PPC4xx_SYS_INFO; static inline rt_uint32_t get_mcsr(void) { - rt_uint32_t val; + rt_uint32_t val; - asm volatile("mfspr %0, 0x23c" : "=r" (val) :); - return val; + asm volatile("mfspr %0, 0x23c" : "=r" (val) :); + return val; } static inline void set_mcsr(rt_uint32_t val) { - asm volatile("mtspr 0x23c, %0" : "=r" (val) :); + asm volatile("mtspr 0x23c, %0" : "=r" (val) :); } -#endif /* __ASSEMBLY__ */ +#endif /* __ASSEMBLY__ */ /* for multi-cpu support */ -#define NA_OR_UNKNOWN_CPU -1 +#define NA_OR_UNKNOWN_CPU -1 -#endif /* __PPC4XX_H__ */ +#endif /* __PPC4XX_H__ */ diff --git a/libcpu/ppc/ppc405/include/asm/ppc_defs.h b/libcpu/ppc/ppc405/include/asm/ppc_defs.h index 88aed26009..0b6d06deae 100644 --- a/libcpu/ppc/ppc405/include/asm/ppc_defs.h +++ b/libcpu/ppc/ppc405/include/asm/ppc_defs.h @@ -24,50 +24,50 @@ /* * WARNING! This file is automatically generated - DO NOT EDIT! */ -#define STACK_FRAME_OVERHEAD 16 -#define INT_FRAME_SIZE 192 -#define GPR0 16 -#define GPR1 20 -#define GPR2 24 -#define GPR3 28 -#define GPR4 32 -#define GPR5 36 -#define GPR6 40 -#define GPR7 44 -#define GPR8 48 -#define GPR9 52 -#define GPR10 56 -#define GPR11 60 -#define GPR12 64 -#define GPR13 68 -#define GPR14 72 -#define GPR15 76 -#define GPR16 80 -#define GPR17 84 -#define GPR18 88 -#define GPR19 92 -#define GPR20 96 -#define GPR21 100 -#define GPR22 104 -#define GPR23 108 -#define GPR24 112 -#define GPR25 116 -#define GPR26 120 -#define GPR27 124 -#define GPR28 128 -#define GPR29 132 -#define GPR30 136 -#define GPR31 140 -#define _NIP 144 -#define _MSR 148 -#define ORIG_GPR3 152 -#define _CTR 156 -#define _LINK 160 -#define _XER 164 -#define _CCR 168 -#define _MQ 172 -#define TRAP 176 -#define _DAR 180 -#define _DSISR 184 -#define RESULT 188 +#define STACK_FRAME_OVERHEAD 16 +#define INT_FRAME_SIZE 192 +#define GPR0 16 +#define GPR1 20 +#define GPR2 24 +#define GPR3 28 +#define GPR4 32 +#define GPR5 36 +#define GPR6 40 +#define GPR7 44 +#define GPR8 48 +#define GPR9 52 +#define GPR10 56 +#define GPR11 60 +#define GPR12 64 +#define GPR13 68 +#define GPR14 72 +#define GPR15 76 +#define GPR16 80 +#define GPR17 84 +#define GPR18 88 +#define GPR19 92 +#define GPR20 96 +#define GPR21 100 +#define GPR22 104 +#define GPR23 108 +#define GPR24 112 +#define GPR25 116 +#define GPR26 120 +#define GPR27 124 +#define GPR28 128 +#define GPR29 132 +#define GPR30 136 +#define GPR31 140 +#define _NIP 144 +#define _MSR 148 +#define ORIG_GPR3 152 +#define _CTR 156 +#define _LINK 160 +#define _XER 164 +#define _CCR 168 +#define _MQ 172 +#define TRAP 176 +#define _DAR 180 +#define _DSISR 184 +#define RESULT 188 diff --git a/libcpu/ppc/ppc405/include/asm/processor.h b/libcpu/ppc/ppc405/include/asm/processor.h index 7aeeb01dc5..827de2186b 100644 --- a/libcpu/ppc/ppc405/include/asm/processor.h +++ b/libcpu/ppc/ppc405/include/asm/processor.h @@ -15,80 +15,80 @@ /* Machine State Register (MSR) Fields */ #ifdef CONFIG_PPC64BRIDGE -#define MSR_SF (1<<63) -#define MSR_ISF (1<<61) +#define MSR_SF (1<<63) +#define MSR_ISF (1<<61) #endif /* CONFIG_PPC64BRIDGE */ -#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ -#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ -#define MSR_SPE (1<<25) /* Enable SPE(e500) */ -#define MSR_POW (1<<18) /* Enable Power Management */ -#define MSR_WE (1<<18) /* Wait State Enable */ -#define MSR_TGPR (1<<17) /* TLB Update registers in use */ -#define MSR_CE (1<<17) /* Critical Interrupt Enable */ -#define MSR_ILE (1<<16) /* Interrupt Little Endian */ -#define MSR_EE (1<<15) /* External Interrupt Enable */ -#define MSR_PR (1<<14) /* Problem State / Privilege Level */ -#define MSR_FP (1<<13) /* Floating Point enable */ -#define MSR_ME (1<<12) /* Machine Check Enable */ -#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ -#define MSR_SE (1<<10) /* Single Step */ -#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ -#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ -#define MSR_BE (1<<9) /* Branch Trace */ -#define MSR_DE (1<<9) /* Debug Exception Enable */ -#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ -#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ -#define MSR_IR (1<<5) /* Instruction Relocate */ -#define MSR_IS (1<<5) /* Book E Instruction space */ -#define MSR_DR (1<<4) /* Data Relocate */ -#define MSR_DS (1<<4) /* Book E Data space */ -#define MSR_PE (1<<3) /* Protection Enable */ -#define MSR_PX (1<<2) /* Protection Exclusive Mode */ -#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ -#define MSR_RI (1<<1) /* Recoverable Exception */ -#define MSR_LE (1<<0) /* Little Endian */ +#define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */ +#define MSR_VEC (1<<25) /* Enable AltiVec(74xx) */ +#define MSR_SPE (1<<25) /* Enable SPE(e500) */ +#define MSR_POW (1<<18) /* Enable Power Management */ +#define MSR_WE (1<<18) /* Wait State Enable */ +#define MSR_TGPR (1<<17) /* TLB Update registers in use */ +#define MSR_CE (1<<17) /* Critical Interrupt Enable */ +#define MSR_ILE (1<<16) /* Interrupt Little Endian */ +#define MSR_EE (1<<15) /* External Interrupt Enable */ +#define MSR_PR (1<<14) /* Problem State / Privilege Level */ +#define MSR_FP (1<<13) /* Floating Point enable */ +#define MSR_ME (1<<12) /* Machine Check Enable */ +#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */ +#define MSR_SE (1<<10) /* Single Step */ +#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */ +#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ +#define MSR_BE (1<<9) /* Branch Trace */ +#define MSR_DE (1<<9) /* Debug Exception Enable */ +#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */ +#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */ +#define MSR_IR (1<<5) /* Instruction Relocate */ +#define MSR_IS (1<<5) /* Book E Instruction space */ +#define MSR_DR (1<<4) /* Data Relocate */ +#define MSR_DS (1<<4) /* Book E Data space */ +#define MSR_PE (1<<3) /* Protection Enable */ +#define MSR_PX (1<<2) /* Protection Exclusive Mode */ +#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */ +#define MSR_RI (1<<1) /* Recoverable Exception */ +#define MSR_LE (1<<0) /* Little Endian */ #ifdef CONFIG_APUS_FAST_EXCEPT -#define MSR_ MSR_ME|MSR_IP|MSR_RI +#define MSR_ MSR_ME|MSR_IP|MSR_RI #else -#define MSR_ MSR_ME|MSR_RI +#define MSR_ MSR_ME|MSR_RI #endif #ifndef CONFIG_E500 -#define MSR_KERNEL MSR_|MSR_IR|MSR_DR +#define MSR_KERNEL MSR_|MSR_IR|MSR_DR #else -#define MSR_KERNEL MSR_ME +#define MSR_KERNEL MSR_ME #endif /* Floating Point Status and Control Register (FPSCR) Fields */ -#define FPSCR_FX 0x80000000 /* FPU exception summary */ -#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ -#define FPSCR_VX 0x20000000 /* Invalid operation summary */ -#define FPSCR_OX 0x10000000 /* Overflow exception summary */ -#define FPSCR_UX 0x08000000 /* Underflow exception summary */ -#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ -#define FPSCR_XX 0x02000000 /* Inexact exception summary */ -#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ -#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ -#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ -#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ -#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ -#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ -#define FPSCR_FR 0x00040000 /* Fraction rounded */ -#define FPSCR_FI 0x00020000 /* Fraction inexact */ -#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ -#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ -#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ -#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ -#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ -#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ -#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ -#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ -#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ -#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ -#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ -#define FPSCR_RN 0x00000003 /* FPU rounding control */ +#define FPSCR_FX 0x80000000 /* FPU exception summary */ +#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */ +#define FPSCR_VX 0x20000000 /* Invalid operation summary */ +#define FPSCR_OX 0x10000000 /* Overflow exception summary */ +#define FPSCR_UX 0x08000000 /* Underflow exception summary */ +#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */ +#define FPSCR_XX 0x02000000 /* Inexact exception summary */ +#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */ +#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */ +#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */ +#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */ +#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */ +#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */ +#define FPSCR_FR 0x00040000 /* Fraction rounded */ +#define FPSCR_FI 0x00020000 /* Fraction inexact */ +#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */ +#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */ +#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */ +#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */ +#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */ +#define FPSCR_VE 0x00000080 /* Invalid op exception enable */ +#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */ +#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */ +#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */ +#define FPSCR_XE 0x00000008 /* FP inexact exception enable */ +#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */ +#define FPSCR_RN 0x00000003 /* FPU rounding control */ /* Special Purpose Registers (SPRNs)*/ @@ -97,618 +97,618 @@ #define CONFIG_BOOKE #endif -#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ +#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ #ifdef CONFIG_BOOKE -#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ +#define SPRN_CCR1 0x378 /* Core Configuration Register for 440 only */ #endif -#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ -#define SPRN_CTR 0x009 /* Count Register */ -#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ +#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ +#define SPRN_CTR 0x009 /* Count Register */ +#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ #ifndef CONFIG_BOOKE -#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ -#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ +#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ +#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ #else -#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ -#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ -#endif /* CONFIG_BOOKE */ -#define SPRN_DAR 0x013 /* Data Address Register */ -#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ -#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ -#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ -#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ -#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ -#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ -#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ -#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ -#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ -#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ -#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ -#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ -#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ -#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ -#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ -#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ -#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ -#define DBCR_EDM 0x80000000 -#define DBCR_IDM 0x40000000 -#define DBCR_RST(x) (((x) & 0x3) << 28) -#define DBCR_RST_NONE 0 -#define DBCR_RST_CORE 1 -#define DBCR_RST_CHIP 2 -#define DBCR_RST_SYSTEM 3 -#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ -#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ -#define DBCR_EDE 0x02000000 /* Exception Debug Event */ -#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ -#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ -#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ -#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ -#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ -#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ -#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ -#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ -#define DAC_BYTE 0 -#define DAC_HALF 1 -#define DAC_WORD 2 -#define DAC_QUAD 3 -#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ -#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ -#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ -#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ -#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ -#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ -#define DBCR_SIA 0x00000008 /* Second IAC Enable */ -#define DBCR_SDA 0x00000004 /* Second DAC Enable */ -#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ -#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ +#define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */ +#define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */ +#endif /* CONFIG_BOOKE */ +#define SPRN_DAR 0x013 /* Data Address Register */ +#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */ +#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */ +#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */ +#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */ +#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */ +#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */ +#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */ +#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */ +#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */ +#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */ +#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */ +#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */ +#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */ +#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */ +#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */ +#define SPRN_DBAT7U 0x23E /* Data BAT 7 Lower Register */ +#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ +#define DBCR_EDM 0x80000000 +#define DBCR_IDM 0x40000000 +#define DBCR_RST(x) (((x) & 0x3) << 28) +#define DBCR_RST_NONE 0 +#define DBCR_RST_CORE 1 +#define DBCR_RST_CHIP 2 +#define DBCR_RST_SYSTEM 3 +#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */ +#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */ +#define DBCR_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ +#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ +#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ +#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ +#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ +#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ +#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ +#define DAC_BYTE 0 +#define DAC_HALF 1 +#define DAC_WORD 2 +#define DAC_QUAD 3 +#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ +#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ +#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ +#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ +#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ +#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ +#define DBCR_SIA 0x00000008 /* Second IAC Enable */ +#define DBCR_SDA 0x00000004 /* Second DAC Enable */ +#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ +#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ #ifndef CONFIG_BOOKE -#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ +#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ #else -#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ +#define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */ #endif /* CONFIG_BOOKE */ #ifndef CONFIG_BOOKE -#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ -#define SPRN_DBSR 0x3F0 /* Debug Status Register */ +#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ +#define SPRN_DBSR 0x3F0 /* Debug Status Register */ #else -#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ +#define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */ #ifdef CONFIG_BOOKE -#define SPRN_DBDR 0x3f3 /* Debug Data Register */ +#define SPRN_DBDR 0x3f3 /* Debug Data Register */ #endif -#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ -#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ -#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ +#define SPRN_DBSR 0x130 /* Book E Debug Status Register */ +#define DBSR_IC 0x08000000 /* Book E Instruction Completion */ +#define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */ #endif /* CONFIG_BOOKE */ -#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ -#define DCCR_NOCACHE 0 /* Noncacheable */ -#define DCCR_CACHE 1 /* Cacheable */ +#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ +#define DCCR_NOCACHE 0 /* Noncacheable */ +#define DCCR_CACHE 1 /* Cacheable */ #ifndef CONFIG_BOOKE -#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ -#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ +#define SPRN_DCDBTRL 0x39c /* Data Cache Debug Tag Register Low */ +#define SPRN_DCDBTRH 0x39d /* Data Cache Debug Tag Register High */ #endif -#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ -#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ -#define DCWR_COPY 0 /* Copy-back */ -#define DCWR_WRITE 1 /* Write-through */ +#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ +#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ +#define DCWR_COPY 0 /* Copy-back */ +#define DCWR_WRITE 1 /* Write-through */ #ifndef CONFIG_BOOKE -#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ +#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ #else -#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ +#define SPRN_DEAR 0x03D /* Book E Data Error Address Register */ #endif /* CONFIG_BOOKE */ -#define SPRN_DEC 0x016 /* Decrement Register */ -#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ +#define SPRN_DEC 0x016 /* Decrement Register */ +#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */ #ifdef CONFIG_BOOKE -#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ -#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ -#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ -#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ +#define SPRN_DNV0 0x390 /* Data Cache Normal Victim 0 */ +#define SPRN_DNV1 0x391 /* Data Cache Normal Victim 1 */ +#define SPRN_DNV2 0x392 /* Data Cache Normal Victim 2 */ +#define SPRN_DNV3 0x393 /* Data Cache Normal Victim 3 */ #endif -#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ +#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ #ifdef CONFIG_BOOKE -#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ -#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ -#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ -#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ -#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ +#define SPRN_DTV0 0x394 /* Data Cache Transient Victim 0 */ +#define SPRN_DTV1 0x395 /* Data Cache Transient Victim 1 */ +#define SPRN_DTV2 0x396 /* Data Cache Transient Victim 2 */ +#define SPRN_DTV3 0x397 /* Data Cache Transient Victim 3 */ +#define SPRN_DVLIM 0x398 /* Data Cache Victim Limit */ #endif -#define SPRN_EAR 0x11A /* External Address Register */ +#define SPRN_EAR 0x11A /* External Address Register */ #ifndef CONFIG_BOOKE -#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ +#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ #else -#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ +#define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */ #endif /* CONFIG_BOOKE */ -#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ -#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ -#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ -#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ -#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ -#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ -#define ESR_PTR 0x02000000 /* Program Exception - Trap */ -#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ -#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ -#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ -#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ -#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ -#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ +#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ +#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ +#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ +#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ +#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ +#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ +#define ESR_PTR 0x02000000 /* Program Exception - Trap */ +#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ +#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ +#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ +#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */ +#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */ +#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */ -#define HID0_ICE_SHIFT 15 -#define HID0_DCE_SHIFT 14 -#define HID0_DLOCK_SHIFT 12 +#define HID0_ICE_SHIFT 15 +#define HID0_DCE_SHIFT 14 +#define HID0_DLOCK_SHIFT 12 -#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ -#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ -#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ -#define HID0_SBCLK (1<<27) -#define HID0_EICE (1<<26) -#define HID0_ECLK (1<<25) -#define HID0_PAR (1<<24) -#define HID0_DOZE (1<<23) -#define HID0_NAP (1<<22) -#define HID0_SLEEP (1<<21) -#define HID0_DPM (1<<20) -#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */ -#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */ -#define HID0_TBEN (1<<14) /* Time Base Enable */ -#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ -#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */ -#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ -#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ -#define HID0_DCI HID0_DCFI -#define HID0_SPD (1<<9) /* Speculative disable */ -#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */ -#define HID0_SGE (1<<7) /* Store Gathering Enable */ -#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ -#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ -#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ -#define HID0_ABE (1<<3) /* Address Broadcast Enable */ -#define HID0_BHTE (1<<2) /* Branch History Table Enable */ -#define HID0_BTCD (1<<1) /* Branch target cache disable */ -#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ -#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ -#define HID1_ASTME (1<<13) /* Address bus streaming mode */ -#define HID1_ABE (1<<12) /* Address broadcast enable */ -#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ +#define HID0_EMCP (1<<31) /* Enable Machine Check pin */ +#define HID0_EBA (1<<29) /* Enable Bus Address Parity */ +#define HID0_EBD (1<<28) /* Enable Bus Data Parity */ +#define HID0_SBCLK (1<<27) +#define HID0_EICE (1<<26) +#define HID0_ECLK (1<<25) +#define HID0_PAR (1<<24) +#define HID0_DOZE (1<<23) +#define HID0_NAP (1<<22) +#define HID0_SLEEP (1<<21) +#define HID0_DPM (1<<20) +#define HID0_ICE (1<<HID0_ICE_SHIFT) /* Instruction Cache Enable */ +#define HID0_DCE (1<<HID0_DCE_SHIFT) /* Data Cache Enable */ +#define HID0_TBEN (1<<14) /* Time Base Enable */ +#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ +#define HID0_DLOCK (1<<HID0_DLOCK_SHIFT) /* Data Cache Lock */ +#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ +#define HID0_DCFI (1<<10) /* Data Cache Flash Invalidate */ +#define HID0_DCI HID0_DCFI +#define HID0_SPD (1<<9) /* Speculative disable */ +#define HID0_ENMAS7 (1<<7) /* Enable MAS7 Update for 36-bit phys */ +#define HID0_SGE (1<<7) /* Store Gathering Enable */ +#define HID0_SIED HID_SGE /* Serial Instr. Execution [Disable] */ +#define HID0_DCFA (1<<6) /* Data Cache Flush Assist */ +#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ +#define HID0_ABE (1<<3) /* Address Broadcast Enable */ +#define HID0_BHTE (1<<2) /* Branch History Table Enable */ +#define HID0_BTCD (1<<1) /* Branch target cache disable */ +#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#define HID1_RFXE (1<<17) /* Read Fault Exception Enable */ +#define HID1_ASTME (1<<13) /* Address bus streaming mode */ +#define HID1_ABE (1<<12) /* Address broadcast enable */ +#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #ifndef CONFIG_BOOKE -#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ -#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ +#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ +#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ #else -#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ -#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ +#define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */ +#define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */ #endif /* CONFIG_BOOKE */ -#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ -#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ -#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ -#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ -#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ -#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ -#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ -#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ -#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ -#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ -#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ -#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ -#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ -#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ -#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ -#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ -#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ -#define ICCR_NOCACHE 0 /* Noncacheable */ -#define ICCR_CACHE 1 /* Cacheable */ -#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ +#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */ +#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */ +#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */ +#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */ +#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */ +#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */ +#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */ +#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */ +#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */ +#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */ +#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */ +#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */ +#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */ +#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */ +#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */ +#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */ +#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ +#define ICCR_NOCACHE 0 /* Noncacheable */ +#define ICCR_CACHE 1 /* Cacheable */ +#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ #ifdef CONFIG_BOOKE -#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */ -#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */ +#define SPRN_ICDBTRL 0x39e /* instruction cache debug tag register low */ +#define SPRN_ICDBTRH 0x39f /* instruction cache debug tag register high */ #endif -#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ -#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ -#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ -#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ +#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ +#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ +#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ +#define SPRN_IMMR 0x27E /* Internal Memory Map Register */ #ifdef CONFIG_BOOKE -#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */ -#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */ -#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */ -#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */ -#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */ -#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */ -#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */ -#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */ -#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */ +#define SPRN_INV0 0x370 /* Instruction Cache Normal Victim 0 */ +#define SPRN_INV1 0x371 /* Instruction Cache Normal Victim 1 */ +#define SPRN_INV2 0x372 /* Instruction Cache Normal Victim 2 */ +#define SPRN_INV3 0x373 /* Instruction Cache Normal Victim 3 */ +#define SPRN_ITV0 0x374 /* Instruction Cache Transient Victim 0 */ +#define SPRN_ITV1 0x375 /* Instruction Cache Transient Victim 1 */ +#define SPRN_ITV2 0x376 /* Instruction Cache Transient Victim 2 */ +#define SPRN_ITV3 0x377 /* Instruction Cache Transient Victim 3 */ +#define SPRN_IVLIM 0x399 /* Instruction Cache Victim Limit */ #endif -#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ -#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ -#define SPRN_LR 0x008 /* Link Register */ -#define SPRN_MBAR 0x137 /* System memory base address */ -#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ -#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ +#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */ +#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ +#define SPRN_LR 0x008 /* Link Register */ +#define SPRN_MBAR 0x137 /* System memory base address */ +#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ +#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ #ifdef CONFIG_BOOKE -#define SPRN_MMUCR 0x3b2 /* MMU Control Register */ +#define SPRN_MMUCR 0x3b2 /* MMU Control Register */ #endif -#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ -#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ -#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ -#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ +#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ +#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ +#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ +#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ #ifndef CONFIG_BOOKE -#define SPRN_PID 0x3B1 /* Process ID */ -#define SPRN_PIR 0x3FF /* Processor Identification Register */ +#define SPRN_PID 0x3B1 /* Process ID */ +#define SPRN_PIR 0x3FF /* Processor Identification Register */ #else -#define SPRN_PID 0x030 /* Book E Process ID */ -#define SPRN_PIR 0x11E /* Book E Processor Identification Register */ +#define SPRN_PID 0x030 /* Book E Process ID */ +#define SPRN_PIR 0x11E /* Book E Processor Identification Register */ #endif /* CONFIG_BOOKE */ -#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ -#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ -#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ -#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ -#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ -#define SPRN_PVR 0x11F /* Processor Version Register */ -#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ +#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ +#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */ +#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ +#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ +#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ +#define SPRN_PVR 0x11F /* Processor Version Register */ +#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ #ifdef CONFIG_BOOKE -#define SPRN_RSTCFG 0x39b /* Reset Configuration */ +#define SPRN_RSTCFG 0x39b /* Reset Configuration */ #endif -#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ -#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ -#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ -#define SGR_NORMAL 0 -#define SGR_GUARDED 1 -#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ -#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ -#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ -#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ -#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ -#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ -#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ -#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ -#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ -#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ -#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ -#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ -#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ +#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ +#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ +#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ +#define SGR_NORMAL 0 +#define SGR_GUARDED 1 +#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ +#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ +#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ +#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ +#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ +#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ +#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ +#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ +#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ +#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ +#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ +#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ +#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ #ifdef CONFIG_BOOKE -#define SPRN_SVR 0x3FF /* System Version Register */ +#define SPRN_SVR 0x3FF /* System Version Register */ #else -#define SPRN_SVR 0x11E /* System Version Register */ +#define SPRN_SVR 0x11E /* System Version Register */ #endif -#define SPRN_TBHI 0x3DC /* Time Base High */ -#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ -#define SPRN_TBLO 0x3DD /* Time Base Low */ -#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ -#define SPRN_TBRL 0x10C /* Time Base Read Lower Register */ -#define SPRN_TBRU 0x10D /* Time Base Read Upper Register */ -#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */ -#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */ +#define SPRN_TBHI 0x3DC /* Time Base High */ +#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ +#define SPRN_TBLO 0x3DD /* Time Base Low */ +#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ +#define SPRN_TBRL 0x10C /* Time Base Read Lower Register */ +#define SPRN_TBRU 0x10D /* Time Base Read Upper Register */ +#define SPRN_TBWL 0x11C /* Time Base Write Lower Register */ +#define SPRN_TBWU 0x11D /* Time Base Write Upper Register */ #ifndef CONFIG_BOOKE -#define SPRN_TCR 0x3DA /* Timer Control Register */ +#define SPRN_TCR 0x3DA /* Timer Control Register */ #else -#define SPRN_TCR 0x154 /* Book E Timer Control Register */ +#define SPRN_TCR 0x154 /* Book E Timer Control Register */ #endif /* CONFIG_BOOKE */ -#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ -#define WP_2_17 0 /* 2^17 clocks */ -#define WP_2_21 1 /* 2^21 clocks */ -#define WP_2_25 2 /* 2^25 clocks */ -#define WP_2_29 3 /* 2^29 clocks */ -#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ -#define WRC_NONE 0 /* No reset will occur */ -#define WRC_CORE 1 /* Core reset will occur */ -#define WRC_CHIP 2 /* Chip reset will occur */ -#define WRC_SYSTEM 3 /* System reset will occur */ -#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ -#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ -#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ -#define FP_2_9 0 /* 2^9 clocks */ -#define FP_2_13 1 /* 2^13 clocks */ -#define FP_2_17 2 /* 2^17 clocks */ -#define FP_2_21 3 /* 2^21 clocks */ -#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ -#define TCR_ARE 0x00400000 /* Auto Reload Enable */ -#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ -#define THRM1_TIN (1<<0) -#define THRM1_TIV (1<<1) -#define THRM1_THRES (0x7f<<2) -#define THRM1_TID (1<<29) -#define THRM1_TIE (1<<30) -#define THRM1_V (1<<31) -#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ -#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ -#define THRM3_E (1<<31) -#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ +#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ +#define WP_2_17 0 /* 2^17 clocks */ +#define WP_2_21 1 /* 2^21 clocks */ +#define WP_2_25 2 /* 2^25 clocks */ +#define WP_2_29 3 /* 2^29 clocks */ +#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ +#define WRC_NONE 0 /* No reset will occur */ +#define WRC_CORE 1 /* Core reset will occur */ +#define WRC_CHIP 2 /* Chip reset will occur */ +#define WRC_SYSTEM 3 /* System reset will occur */ +#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ +#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ +#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ +#define FP_2_9 0 /* 2^9 clocks */ +#define FP_2_13 1 /* 2^13 clocks */ +#define FP_2_17 2 /* 2^17 clocks */ +#define FP_2_21 3 /* 2^21 clocks */ +#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ +#define TCR_ARE 0x00400000 /* Auto Reload Enable */ +#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */ +#define THRM1_TIN (1<<0) +#define THRM1_TIV (1<<1) +#define THRM1_THRES (0x7f<<2) +#define THRM1_TID (1<<29) +#define THRM1_TIE (1<<30) +#define THRM1_V (1<<31) +#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ +#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ +#define THRM3_E (1<<31) +#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ #ifndef CONFIG_BOOKE -#define SPRN_TSR 0x3D8 /* Timer Status Register */ +#define SPRN_TSR 0x3D8 /* Timer Status Register */ #else -#define SPRN_TSR 0x150 /* Book E Timer Status Register */ +#define SPRN_TSR 0x150 /* Book E Timer Status Register */ #endif /* CONFIG_BOOKE */ -#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ -#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ -#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ -#define WRS_NONE 0 /* No WDT reset occurred */ -#define WRS_CORE 1 /* WDT forced core reset */ -#define WRS_CHIP 2 /* WDT forced chip reset */ -#define WRS_SYSTEM 3 /* WDT forced system reset */ -#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ -#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ -#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ -#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ -#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ -#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ -#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ -#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ -#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ -#define SPRN_XER 0x001 /* Fixed Point Exception Register */ -#define SPRN_ZPR 0x3B0 /* Zone Protection Register */ +#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ +#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ +#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ +#define WRS_NONE 0 /* No WDT reset occurred */ +#define WRS_CORE 1 /* WDT forced core reset */ +#define WRS_CHIP 2 /* WDT forced chip reset */ +#define WRS_SYSTEM 3 /* WDT forced system reset */ +#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ +#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ +#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */ +#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */ +#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */ +#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */ +#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */ +#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */ +#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */ +#define SPRN_XER 0x001 /* Fixed Point Exception Register */ +#define SPRN_ZPR 0x3B0 /* Zone Protection Register */ /* Book E definitions */ -#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ -#define SPRN_CSRR0 0x03A /* Critical SRR0 */ -#define SPRN_CSRR1 0x03B /* Critical SRR0 */ -#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ -#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ -#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ -#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ -#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ -#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ -#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ -#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ -#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ -#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ -#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ -#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ -#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ -#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ -#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ -#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ -#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ -#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ -#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ -#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ -#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ -#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ -#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ -#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ -#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ -#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */ -#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */ -#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */ -#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */ -#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */ -#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ +#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ +#define SPRN_CSRR0 0x03A /* Critical SRR0 */ +#define SPRN_CSRR1 0x03B /* Critical SRR0 */ +#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ +#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ +#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ +#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ +#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ +#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ +#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ +#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ +#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ +#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ +#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ +#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ +#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ +#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ +#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ +#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ +#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ +#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ +#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ +#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ +#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ +#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ +#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ +#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ +#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ +#define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */ +#define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */ +#define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */ +#define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */ +#define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */ +#define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */ /* e500 definitions */ -#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ -#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */ -#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */ -#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ -#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ -#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ -#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ -#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ -#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ -#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ -#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ -#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ -#define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ -#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ -#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ -#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */ -#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */ -#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ -#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ -#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ -#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ -#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ -#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ -#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ -#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ -#define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ +#define SPRN_L1CFG0 0x203 /* L1 Cache Configuration Register 0 */ +#define SPRN_L1CFG1 0x204 /* L1 Cache Configuration Register 1 */ +#define SPRN_L2CFG0 0x207 /* L2 Cache Configuration Register 0 */ +#define SPRN_L1CSR0 0x3f2 /* L1 Data Cache Control and Status Register 0 */ +#define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */ +#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ +#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ +#define SPRN_L1CSR1 0x3f3 /* L1 Instruction Cache Control and Status Register 1 */ +#define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */ +#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ +#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ +#define SPRN_L1CSR2 0x25e /* L1 Data Cache Control and Status Register 2 */ +#define SPRN_L2CSR0 0x3f9 /* L2 Data Cache Control and Status Register 0 */ +#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ +#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity/ECC Enable */ +#define L2CSR0_L2WP 0x1c000000 /* L2 I/D Way Partioning */ +#define L2CSR0_L2CM 0x03000000 /* L2 Cache Coherency Mode */ +#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ +#define L2CSR0_L2IO 0x00100000 /* L2 Cache Instruction Only */ +#define L2CSR0_L2DO 0x00010000 /* L2 Cache Data Only */ +#define L2CSR0_L2REP 0x00003000 /* L2 Line Replacement Algo */ +#define L2CSR0_L2FL 0x00000800 /* L2 Cache Flush */ +#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flash Clear */ +#define L2CSR0_L2LOA 0x00000080 /* L2 Cache Lock Overflow Allocate */ +#define L2CSR0_L2LO 0x00000020 /* L2 Cache Lock Overflow */ +#define SPRN_L2CSR1 0x3fa /* L2 Data Cache Control and Status Register 1 */ -#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ -#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ -#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ -#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ -#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ -#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ -#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ -#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ -#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ -#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ -#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ +#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ +#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ +#define SPRN_MMUCSR0 0x3f4 /* MMU control and status register 0 */ +#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ +#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ +#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ +#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ +#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ +#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ +#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ +#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */ -#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ -#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ -#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ -#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ -#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ +#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ +#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ +#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ +#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ +#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ -#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ -#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ -#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ -#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ -#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ -#define SPRN_PID1 0x279 /* Process ID Register 1 */ -#define SPRN_PID2 0x27a /* Process ID Register 2 */ -#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ -#define SPRN_MCAR 0x23d /* Machine Check Address register */ -#define MCSR_MCS 0x80000000 /* Machine Check Summary */ -#define MCSR_IB 0x40000000 /* Instruction PLB Error */ +#define SPRN_MCSRR0 0x23a /* Machine Check Save and Restore Register 0 */ +#define SPRN_MCSRR1 0x23b /* Machine Check Save and Restore Register 1 */ +#define SPRN_BUCSR 0x3f5 /* Branch Control and Status Register */ +#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ +#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ +#define SPRN_PID1 0x279 /* Process ID Register 1 */ +#define SPRN_PID2 0x27a /* Process ID Register 2 */ +#define SPRN_MCSR 0x23c /* Machine Check Syndrome register */ +#define SPRN_MCAR 0x23d /* Machine Check Address register */ +#define MCSR_MCS 0x80000000 /* Machine Check Summary */ +#define MCSR_IB 0x40000000 /* Instruction PLB Error */ #if defined(CONFIG_440) -#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ -#define MCSR_DWB 0x10000000 /* Data Write PLB Error */ +#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ +#define MCSR_DWB 0x10000000 /* Data Write PLB Error */ #else -#define MCSR_DB 0x20000000 /* Data PLB Error */ +#define MCSR_DB 0x20000000 /* Data PLB Error */ #endif /* defined(CONFIG_440) */ -#define MCSR_TLBP 0x08000000 /* TLB Parity Error */ -#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ -#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ -#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ -#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ -#define ESR_ST 0x00800000 /* Store Operation */ +#define MCSR_TLBP 0x08000000 /* TLB Parity Error */ +#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ +#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ +#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ +#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ +#define ESR_ST 0x00800000 /* Store Operation */ #if defined(CONFIG_MPC86xx) -#define SPRN_MSSCR0 0x3f6 -#define SPRN_MSSSR0 0x3f7 +#define SPRN_MSSCR0 0x3f6 +#define SPRN_MSSSR0 0x3f7 #endif /* Short-hand versions for a number of the above SPRNs */ -#define CTR SPRN_CTR /* Counter Register */ -#define DAR SPRN_DAR /* Data Address Register */ -#define DABR SPRN_DABR /* Data Address Breakpoint Register */ -#define DAC1 SPRN_DAC1 /* Data Address Register 1 */ -#define DAC2 SPRN_DAC2 /* Data Address Register 2 */ -#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ -#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ -#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ -#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ -#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ -#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ -#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ -#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ -#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ -#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ -#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ -#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ -#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ -#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ -#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ -#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ -#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ -#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ -#define DBSR SPRN_DBSR /* Debug Status Register */ -#define DCMP SPRN_DCMP /* Data TLB Compare Register */ -#define DEC SPRN_DEC /* Decrement Register */ -#define DMISS SPRN_DMISS /* Data TLB Miss Register */ -#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ -#define EAR SPRN_EAR /* External Address Register */ -#define ESR SPRN_ESR /* Exception Syndrome Register */ -#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ -#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ -#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ -#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ -#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ -#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ -#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ -#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ -#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ -#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ -#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ -#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ -#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ -#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ -#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ -#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */ -#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */ -#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */ -#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ -#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ -#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ -#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ -#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ -#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ -#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ -#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ -#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ -#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ -#define LR SPRN_LR -#define MBAR SPRN_MBAR /* System memory base address */ +#define CTR SPRN_CTR /* Counter Register */ +#define DAR SPRN_DAR /* Data Address Register */ +#define DABR SPRN_DABR /* Data Address Breakpoint Register */ +#define DAC1 SPRN_DAC1 /* Data Address Register 1 */ +#define DAC2 SPRN_DAC2 /* Data Address Register 2 */ +#define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */ +#define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */ +#define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */ +#define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */ +#define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */ +#define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */ +#define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */ +#define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */ +#define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */ +#define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */ +#define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */ +#define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */ +#define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */ +#define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */ +#define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */ +#define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */ +#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */ +#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */ +#define DBSR SPRN_DBSR /* Debug Status Register */ +#define DCMP SPRN_DCMP /* Data TLB Compare Register */ +#define DEC SPRN_DEC /* Decrement Register */ +#define DMISS SPRN_DMISS /* Data TLB Miss Register */ +#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */ +#define EAR SPRN_EAR /* External Address Register */ +#define ESR SPRN_ESR /* Exception Syndrome Register */ +#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */ +#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */ +#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */ +#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */ +#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */ +#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */ +#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */ +#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */ +#define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */ +#define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */ +#define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */ +#define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */ +#define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */ +#define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */ +#define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */ +#define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */ +#define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */ +#define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */ +#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */ +#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */ +#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */ +#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */ +#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */ +#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */ +#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ +#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ +#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */ +#define L2CR SPRN_L2CR /* PPC 750 L2 control register */ +#define LR SPRN_LR +#define MBAR SPRN_MBAR /* System memory base address */ #if defined(CONFIG_MPC86xx) -#define MSSCR0 SPRN_MSSCR0 +#define MSSCR0 SPRN_MSSCR0 #endif #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx) -#define PIR SPRN_PIR +#define PIR SPRN_PIR #endif -#define SVR SPRN_SVR /* System-On-Chip Version Register */ -#define PVR SPRN_PVR /* Processor Version */ -#define RPA SPRN_RPA /* Required Physical Address Register */ -#define SDR1 SPRN_SDR1 /* MMU hash base register */ -#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ -#define SPR1 SPRN_SPRG1 -#define SPR2 SPRN_SPRG2 -#define SPR3 SPRN_SPRG3 -#define SPRG0 SPRN_SPRG0 -#define SPRG1 SPRN_SPRG1 -#define SPRG2 SPRN_SPRG2 -#define SPRG3 SPRN_SPRG3 -#define SPRG4 SPRN_SPRG4 -#define SPRG5 SPRN_SPRG5 -#define SPRG6 SPRN_SPRG6 -#define SPRG7 SPRN_SPRG7 -#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ -#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ -#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */ -#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */ -#define SVR SPRN_SVR /* System Version Register */ -#define TBRL SPRN_TBRL /* Time Base Read Lower Register */ -#define TBRU SPRN_TBRU /* Time Base Read Upper Register */ -#define TBWL SPRN_TBWL /* Time Base Write Lower Register */ -#define TBWU SPRN_TBWU /* Time Base Write Upper Register */ -#define TCR SPRN_TCR /* Timer Control Register */ -#define TSR SPRN_TSR /* Timer Status Register */ -#define ICTC 1019 -#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */ -#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */ -#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ -#define XER SPRN_XER +#define SVR SPRN_SVR /* System-On-Chip Version Register */ +#define PVR SPRN_PVR /* Processor Version */ +#define RPA SPRN_RPA /* Required Physical Address Register */ +#define SDR1 SPRN_SDR1 /* MMU hash base register */ +#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */ +#define SPR1 SPRN_SPRG1 +#define SPR2 SPRN_SPRG2 +#define SPR3 SPRN_SPRG3 +#define SPRG0 SPRN_SPRG0 +#define SPRG1 SPRN_SPRG1 +#define SPRG2 SPRN_SPRG2 +#define SPRG3 SPRN_SPRG3 +#define SPRG4 SPRN_SPRG4 +#define SPRG5 SPRN_SPRG5 +#define SPRG6 SPRN_SPRG6 +#define SPRG7 SPRN_SPRG7 +#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ +#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ +#define SRR2 SPRN_SRR2 /* Save and Restore Register 2 */ +#define SRR3 SPRN_SRR3 /* Save and Restore Register 3 */ +#define SVR SPRN_SVR /* System Version Register */ +#define TBRL SPRN_TBRL /* Time Base Read Lower Register */ +#define TBRU SPRN_TBRU /* Time Base Read Upper Register */ +#define TBWL SPRN_TBWL /* Time Base Write Lower Register */ +#define TBWU SPRN_TBWU /* Time Base Write Upper Register */ +#define TCR SPRN_TCR /* Timer Control Register */ +#define TSR SPRN_TSR /* Timer Status Register */ +#define ICTC 1019 +#define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */ +#define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */ +#define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */ +#define XER SPRN_XER -#define DECAR SPRN_DECAR -#define CSRR0 SPRN_CSRR0 -#define CSRR1 SPRN_CSRR1 -#define IVPR SPRN_IVPR -#define USPRG0 SPRN_USPRG -#define SPRG4R SPRN_SPRG4R -#define SPRG5R SPRN_SPRG5R -#define SPRG6R SPRN_SPRG6R -#define SPRG7R SPRN_SPRG7R -#define SPRG4W SPRN_SPRG4W -#define SPRG5W SPRN_SPRG5W -#define SPRG6W SPRN_SPRG6W -#define SPRG7W SPRN_SPRG7W -#define DEAR SPRN_DEAR -#define DBCR2 SPRN_DBCR2 -#define IAC3 SPRN_IAC3 -#define IAC4 SPRN_IAC4 -#define DVC1 SPRN_DVC1 -#define DVC2 SPRN_DVC2 -#define IVOR0 SPRN_IVOR0 -#define IVOR1 SPRN_IVOR1 -#define IVOR2 SPRN_IVOR2 -#define IVOR3 SPRN_IVOR3 -#define IVOR4 SPRN_IVOR4 -#define IVOR5 SPRN_IVOR5 -#define IVOR6 SPRN_IVOR6 -#define IVOR7 SPRN_IVOR7 -#define IVOR8 SPRN_IVOR8 -#define IVOR9 SPRN_IVOR9 -#define IVOR10 SPRN_IVOR10 -#define IVOR11 SPRN_IVOR11 -#define IVOR12 SPRN_IVOR12 -#define IVOR13 SPRN_IVOR13 -#define IVOR14 SPRN_IVOR14 -#define IVOR15 SPRN_IVOR15 -#define IVOR32 SPRN_IVOR32 -#define IVOR33 SPRN_IVOR33 -#define IVOR34 SPRN_IVOR34 -#define IVOR35 SPRN_IVOR35 -#define MCSRR0 SPRN_MCSRR0 -#define MCSRR1 SPRN_MCSRR1 -#define L1CSR0 SPRN_L1CSR0 -#define L1CSR1 SPRN_L1CSR1 -#define L1CSR2 SPRN_L1CSR2 -#define L1CFG0 SPRN_L1CFG0 -#define L1CFG1 SPRN_L1CFG1 -#define L2CFG0 SPRN_L2CFG0 -#define L2CSR0 SPRN_L2CSR0 -#define L2CSR1 SPRN_L2CSR1 -#define MCSR SPRN_MCSR -#define MMUCSR0 SPRN_MMUCSR0 -#define BUCSR SPRN_BUCSR -#define PID0 SPRN_PID -#define PID1 SPRN_PID1 -#define PID2 SPRN_PID2 -#define MAS0 SPRN_MAS0 -#define MAS1 SPRN_MAS1 -#define MAS2 SPRN_MAS2 -#define MAS3 SPRN_MAS3 -#define MAS4 SPRN_MAS4 -#define MAS5 SPRN_MAS5 -#define MAS6 SPRN_MAS6 -#define MAS7 SPRN_MAS7 +#define DECAR SPRN_DECAR +#define CSRR0 SPRN_CSRR0 +#define CSRR1 SPRN_CSRR1 +#define IVPR SPRN_IVPR +#define USPRG0 SPRN_USPRG +#define SPRG4R SPRN_SPRG4R +#define SPRG5R SPRN_SPRG5R +#define SPRG6R SPRN_SPRG6R +#define SPRG7R SPRN_SPRG7R +#define SPRG4W SPRN_SPRG4W +#define SPRG5W SPRN_SPRG5W +#define SPRG6W SPRN_SPRG6W +#define SPRG7W SPRN_SPRG7W +#define DEAR SPRN_DEAR +#define DBCR2 SPRN_DBCR2 +#define IAC3 SPRN_IAC3 +#define IAC4 SPRN_IAC4 +#define DVC1 SPRN_DVC1 +#define DVC2 SPRN_DVC2 +#define IVOR0 SPRN_IVOR0 +#define IVOR1 SPRN_IVOR1 +#define IVOR2 SPRN_IVOR2 +#define IVOR3 SPRN_IVOR3 +#define IVOR4 SPRN_IVOR4 +#define IVOR5 SPRN_IVOR5 +#define IVOR6 SPRN_IVOR6 +#define IVOR7 SPRN_IVOR7 +#define IVOR8 SPRN_IVOR8 +#define IVOR9 SPRN_IVOR9 +#define IVOR10 SPRN_IVOR10 +#define IVOR11 SPRN_IVOR11 +#define IVOR12 SPRN_IVOR12 +#define IVOR13 SPRN_IVOR13 +#define IVOR14 SPRN_IVOR14 +#define IVOR15 SPRN_IVOR15 +#define IVOR32 SPRN_IVOR32 +#define IVOR33 SPRN_IVOR33 +#define IVOR34 SPRN_IVOR34 +#define IVOR35 SPRN_IVOR35 +#define MCSRR0 SPRN_MCSRR0 +#define MCSRR1 SPRN_MCSRR1 +#define L1CSR0 SPRN_L1CSR0 +#define L1CSR1 SPRN_L1CSR1 +#define L1CSR2 SPRN_L1CSR2 +#define L1CFG0 SPRN_L1CFG0 +#define L1CFG1 SPRN_L1CFG1 +#define L2CFG0 SPRN_L2CFG0 +#define L2CSR0 SPRN_L2CSR0 +#define L2CSR1 SPRN_L2CSR1 +#define MCSR SPRN_MCSR +#define MMUCSR0 SPRN_MMUCSR0 +#define BUCSR SPRN_BUCSR +#define PID0 SPRN_PID +#define PID1 SPRN_PID1 +#define PID2 SPRN_PID2 +#define MAS0 SPRN_MAS0 +#define MAS1 SPRN_MAS1 +#define MAS2 SPRN_MAS2 +#define MAS3 SPRN_MAS3 +#define MAS4 SPRN_MAS4 +#define MAS5 SPRN_MAS5 +#define MAS6 SPRN_MAS6 +#define MAS7 SPRN_MAS7 #if defined(CONFIG_4xx) || defined(CONFIG_44x) || defined(CONFIG_MPC85xx) #define DAR_DEAR DEAR @@ -718,201 +718,201 @@ /* Device Control Registers */ -#define DCRN_BEAR 0x090 /* Bus Error Address Register */ -#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ -#define BESR_DMES 0x40000000 /* DMA Error Status */ -#define BESR_RWS 0x20000000 /* Read/Write Status */ -#define BESR_ETMASK 0x1C000000 /* Error Type */ -#define ET_PROT 0 -#define ET_PARITY 1 -#define ET_NCFG 2 -#define ET_BUSERR 4 -#define ET_BUSTO 6 -#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ -#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ -#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ -#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ -#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ -#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ -#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ -#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ -#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ -#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ -#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ -#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ -#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ -#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ -#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ -#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ -#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ -#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ -#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ -#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ -#define DCRN_DMASR 0x0E0 /* DMA Status Register */ -#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ -#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ -#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ -#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ -#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ -#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ -#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ -#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ -#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ -#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ -#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ -#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ -#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ -#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ -#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ -#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ -#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ -#define IOCR_E0TE 0x80000000 -#define IOCR_E0LP 0x40000000 -#define IOCR_E1TE 0x20000000 -#define IOCR_E1LP 0x10000000 -#define IOCR_E2TE 0x08000000 -#define IOCR_E2LP 0x04000000 -#define IOCR_E3TE 0x02000000 -#define IOCR_E3LP 0x01000000 -#define IOCR_E4TE 0x00800000 -#define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 -#define IOCR_EDO 0x00008000 -#define IOCR_2XC 0x00004000 -#define IOCR_ATC 0x00002000 -#define IOCR_SPD 0x00001000 -#define IOCR_BEM 0x00000800 -#define IOCR_PTD 0x00000400 -#define IOCR_ARE 0x00000080 -#define IOCR_DRC 0x00000020 -#define IOCR_RDM(x) (((x) & 0x3) << 3) -#define IOCR_TCS 0x00000004 -#define IOCR_SCS 0x00000002 -#define IOCR_SPC 0x00000001 +#define DCRN_BEAR 0x090 /* Bus Error Address Register */ +#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ +#define BESR_DSES 0x80000000 /* Data-Side Error Status */ +#define BESR_DMES 0x40000000 /* DMA Error Status */ +#define BESR_RWS 0x20000000 /* Read/Write Status */ +#define BESR_ETMASK 0x1C000000 /* Error Type */ +#define ET_PROT 0 +#define ET_PARITY 1 +#define ET_NCFG 2 +#define ET_BUSERR 4 +#define ET_BUSTO 6 +#define DCRN_DMACC0 0x0C4 /* DMA Chained Count Register 0 */ +#define DCRN_DMACC1 0x0CC /* DMA Chained Count Register 1 */ +#define DCRN_DMACC2 0x0D4 /* DMA Chained Count Register 2 */ +#define DCRN_DMACC3 0x0DC /* DMA Chained Count Register 3 */ +#define DCRN_DMACR0 0x0C0 /* DMA Channel Control Register 0 */ +#define DCRN_DMACR1 0x0C8 /* DMA Channel Control Register 1 */ +#define DCRN_DMACR2 0x0D0 /* DMA Channel Control Register 2 */ +#define DCRN_DMACR3 0x0D8 /* DMA Channel Control Register 3 */ +#define DCRN_DMACT0 0x0C1 /* DMA Count Register 0 */ +#define DCRN_DMACT1 0x0C9 /* DMA Count Register 1 */ +#define DCRN_DMACT2 0x0D1 /* DMA Count Register 2 */ +#define DCRN_DMACT3 0x0D9 /* DMA Count Register 3 */ +#define DCRN_DMADA0 0x0C2 /* DMA Destination Address Register 0 */ +#define DCRN_DMADA1 0x0CA /* DMA Destination Address Register 1 */ +#define DCRN_DMADA2 0x0D2 /* DMA Destination Address Register 2 */ +#define DCRN_DMADA3 0x0DA /* DMA Destination Address Register 3 */ +#define DCRN_DMASA0 0x0C3 /* DMA Source Address Register 0 */ +#define DCRN_DMASA1 0x0CB /* DMA Source Address Register 1 */ +#define DCRN_DMASA2 0x0D3 /* DMA Source Address Register 2 */ +#define DCRN_DMASA3 0x0DB /* DMA Source Address Register 3 */ +#define DCRN_DMASR 0x0E0 /* DMA Status Register */ +#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ +#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ +#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ +#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ +#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ +#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ +#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ +#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ +#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ +#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ +#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ +#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ +#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ +#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ +#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ +#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ +#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ +#define IOCR_E0TE 0x80000000 +#define IOCR_E0LP 0x40000000 +#define IOCR_E1TE 0x20000000 +#define IOCR_E1LP 0x10000000 +#define IOCR_E2TE 0x08000000 +#define IOCR_E2LP 0x04000000 +#define IOCR_E3TE 0x02000000 +#define IOCR_E3LP 0x01000000 +#define IOCR_E4TE 0x00800000 +#define IOCR_E4LP 0x00400000 +#define IOCR_EDT 0x00080000 +#define IOCR_SOR 0x00040000 +#define IOCR_EDO 0x00008000 +#define IOCR_2XC 0x00004000 +#define IOCR_ATC 0x00002000 +#define IOCR_SPD 0x00001000 +#define IOCR_BEM 0x00000800 +#define IOCR_PTD 0x00000400 +#define IOCR_ARE 0x00000080 +#define IOCR_DRC 0x00000020 +#define IOCR_RDM(x) (((x) & 0x3) << 3) +#define IOCR_TCS 0x00000004 +#define IOCR_SCS 0x00000002 +#define IOCR_SPC 0x00000001 /* System-On-Chip Version Register */ /* System-On-Chip Version Register (SVR) field extraction */ -#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ +#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revision field */ -#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ -#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ -#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ -#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ -#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ -#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ -#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ +#define SVR_CID(svr) (((svr) >> 28) & 0x0F) /* Company or manufacturer ID */ +#define SVR_SOCOP(svr) (((svr) >> 22) & 0x3F) /* SOC integration options */ +#define SVR_SID(svr) (((svr) >> 16) & 0x3F) /* SOC ID */ +#define SVR_PROC(svr) (((svr) >> 12) & 0x0F) /* Process revision field */ +#define SVR_MFG(svr) (((svr) >> 8) & 0x0F) /* Manufacturing revision */ +#define SVR_MJREV(svr) (((svr) >> 4) & 0x0F) /* Major SOC design revision indicator */ +#define SVR_MNREV(svr) (((svr) >> 0) & 0x0F) /* Minor SOC design revision indicator */ /* Processor Version Register */ /* Processor Version Register (PVR) field extraction */ -#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ -#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ +#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */ +#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */ /* * AMCC has further subdivided the standard PowerPC 16-bit version and * revision subfields of the PVR for the PowerPC 403s into the following: */ -#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ -#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ -#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ -#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ -#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ -#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ +#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */ +#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */ +#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */ +#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */ +#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */ +#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */ /* e600 core PVR fields */ -#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ -#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ -#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ -#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ +#define PVR_E600_VER(pvr) (((pvr) >> 15) & 0xFFFF) /* Version/type */ +#define PVR_E600_TECH(pvr) (((pvr) >> 12) & 0xF) /* Technology */ +#define PVR_E600_MAJ(pvr) (((pvr) >> 8) & 0xF) /* Major revision */ +#define PVR_E600_MIN(pvr) (((pvr) >> 0) & 0xFF) /* Minor revision */ /* Processor Version Numbers */ -#define PVR_403GA 0x00200000 -#define PVR_403GB 0x00200100 -#define PVR_403GC 0x00200200 -#define PVR_403GCX 0x00201400 -#define PVR_405GP 0x40110000 -#define PVR_405GP_RB 0x40110040 -#define PVR_405GP_RC 0x40110082 -#define PVR_405GP_RD 0x401100C4 -#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ -#define PVR_405CR_RA 0x40110041 -#define PVR_405CR_RB 0x401100C5 -#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ -#define PVR_405EP_RA 0x51210950 -#define PVR_405GPR_RB 0x50910951 -#define PVR_405EZ_RA 0x41511460 -#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */ -#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ -#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ -#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */ -#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ -#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ -#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ -#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ -#define PVR_440GP_RB 0x40120440 -#define PVR_440GP_RC 0x40120481 -#define PVR_440EP_RA 0x42221850 -#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ -#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ -#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ -#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ -#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ -#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ -#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ -#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ -#define PVR_440GX_RA 0x51B21850 -#define PVR_440GX_RB 0x51B21851 -#define PVR_440GX_RC 0x51B21892 -#define PVR_440GX_RF 0x51B21894 -#define PVR_405EP_RB 0x51210950 -#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ -#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ -#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ -#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ -#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ -#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ -#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ -#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ -#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ -#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ -#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ -#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ +#define PVR_403GA 0x00200000 +#define PVR_403GB 0x00200100 +#define PVR_403GC 0x00200200 +#define PVR_403GCX 0x00201400 +#define PVR_405GP 0x40110000 +#define PVR_405GP_RB 0x40110040 +#define PVR_405GP_RC 0x40110082 +#define PVR_405GP_RD 0x401100C4 +#define PVR_405GP_RE 0x40110145 /* same as pc405cr rev c */ +#define PVR_405CR_RA 0x40110041 +#define PVR_405CR_RB 0x401100C5 +#define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ +#define PVR_405EP_RA 0x51210950 +#define PVR_405GPR_RB 0x50910951 +#define PVR_405EZ_RA 0x41511460 +#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */ +#define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ +#define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ +#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */ +#define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ +#define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ +#define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ +#define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ +#define PVR_440GP_RB 0x40120440 +#define PVR_440GP_RC 0x40120481 +#define PVR_440EP_RA 0x42221850 +#define PVR_440EP_RB 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440EP_RC 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ +#define PVR_440GR_RA 0x422218D3 /* 440EP rev B and 440GR rev A have same PVR */ +#define PVR_440GR_RB 0x422218D4 /* 440EP rev C and 440GR rev B have same PVR */ +#define PVR_440EPX1_RA 0x216218D0 /* 440EPX rev A with Security / Kasumi */ +#define PVR_440EPX2_RA 0x216218D4 /* 440EPX rev A without Security / Kasumi */ +#define PVR_440GRX1_RA 0x216218D0 /* 440GRX rev A with Security / Kasumi */ +#define PVR_440GRX2_RA 0x216218D4 /* 440GRX rev A without Security / Kasumi */ +#define PVR_440GX_RA 0x51B21850 +#define PVR_440GX_RB 0x51B21851 +#define PVR_440GX_RC 0x51B21892 +#define PVR_440GX_RF 0x51B21894 +#define PVR_405EP_RB 0x51210950 +#define PVR_440SP_6_RAB 0x53221850 /* 440SP rev A&B with RAID 6 support enabled */ +#define PVR_440SP_RAB 0x53321850 /* 440SP rev A&B without RAID 6 support */ +#define PVR_440SP_6_RC 0x53221891 /* 440SP rev C with RAID 6 support enabled */ +#define PVR_440SP_RC 0x53321891 /* 440SP rev C without RAID 6 support */ +#define PVR_440SPe_6_RA 0x53421890 /* 440SPe rev A with RAID 6 support enabled */ +#define PVR_440SPe_RA 0x53521890 /* 440SPe rev A without RAID 6 support */ +#define PVR_440SPe_6_RB 0x53421891 /* 440SPe rev B with RAID 6 support enabled */ +#define PVR_440SPe_RB 0x53521891 /* 440SPe rev B without RAID 6 support */ +#define PVR_460EX_SE_RA 0x130218A2 /* 460EX rev A with Security Engine */ +#define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ +#define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ +#define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ #define PVR_460SX_RA 0x13541800 /* 460SX rev A */ #define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ #define PVR_460GX_RA 0x13541802 /* 460GX rev A */ #define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ -#define PVR_601 0x00010000 -#define PVR_602 0x00050000 -#define PVR_603 0x00030000 -#define PVR_603e 0x00060000 -#define PVR_603ev 0x00070000 -#define PVR_603r 0x00071000 -#define PVR_604 0x00040000 -#define PVR_604e 0x00090000 -#define PVR_604r 0x000A0000 -#define PVR_620 0x00140000 -#define PVR_740 0x00080000 -#define PVR_750 PVR_740 -#define PVR_740P 0x10080000 -#define PVR_750P PVR_740P -#define PVR_7400 0x000C0000 -#define PVR_7410 0x800C0000 -#define PVR_7450 0x80000000 +#define PVR_601 0x00010000 +#define PVR_602 0x00050000 +#define PVR_603 0x00030000 +#define PVR_603e 0x00060000 +#define PVR_603ev 0x00070000 +#define PVR_603r 0x00071000 +#define PVR_604 0x00040000 +#define PVR_604e 0x00090000 +#define PVR_604r 0x000A0000 +#define PVR_620 0x00140000 +#define PVR_740 0x00080000 +#define PVR_750 PVR_740 +#define PVR_740P 0x10080000 +#define PVR_750P PVR_740P +#define PVR_7400 0x000C0000 +#define PVR_7410 0x800C0000 +#define PVR_7450 0x80000000 -#define PVR_85xx 0x80200000 -#define PVR_85xx_REV1 (PVR_85xx | 0x0010) -#define PVR_85xx_REV2 (PVR_85xx | 0x0020) +#define PVR_85xx 0x80200000 +#define PVR_85xx_REV1 (PVR_85xx | 0x0010) +#define PVR_85xx_REV2 (PVR_85xx | 0x0020) -#define PVR_86xx 0x80040000 +#define PVR_86xx 0x80040000 #define PVR_VIRTEX5 0x7ff21912 @@ -922,29 +922,29 @@ * differentiated by the version number in the Communication Processor * Module (CPM). */ -#define PVR_821 0x00500000 -#define PVR_823 PVR_821 -#define PVR_850 PVR_821 -#define PVR_860 PVR_821 -#define PVR_7400 0x000C0000 -#define PVR_8240 0x00810100 +#define PVR_821 0x00500000 +#define PVR_823 PVR_821 +#define PVR_850 PVR_821 +#define PVR_860 PVR_821 +#define PVR_7400 0x000C0000 +#define PVR_8240 0x00810100 /* * PowerQUICC II family processors report different PVR values depending * on silicon process (HiP3, HiP4, HiP7, etc.) */ -#define PVR_8260 PVR_8240 -#define PVR_8260_HIP3 0x00810101 -#define PVR_8260_HIP4 0x80811014 -#define PVR_8260_HIP7 0x80822011 +#define PVR_8260 PVR_8240 +#define PVR_8260_HIP3 0x00810101 +#define PVR_8260_HIP4 0x80811014 +#define PVR_8260_HIP7 0x80822011 #define PVR_8260_HIP7R1 0x80822013 -#define PVR_8260_HIP7RA 0x80822014 +#define PVR_8260_HIP7RA 0x80822014 /* * MPC 52xx */ -#define PVR_5200 0x80822011 -#define PVR_5200B 0x80822014 +#define PVR_5200 0x80822011 +#define PVR_5200B 0x80822014 /* * System Version Register @@ -952,26 +952,26 @@ /* System Version Register (SVR) field extraction */ -#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ -#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ +#define SVR_VER(svr) (((svr) >> 16) & 0xFFFF) /* Version field */ +#define SVR_REV(svr) (((svr) >> 0) & 0xFFFF) /* Revison field */ -#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ +#define SVR_SUBVER(svr) (((svr) >> 8) & 0xFF) /* Process/MFG sub-version */ -#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ -#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ +#define SVR_FAM(svr) (((svr) >> 20) & 0xFFF) /* Family field */ +#define SVR_MEM(svr) (((svr) >> 16) & 0xF) /* Member field */ -#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ -#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ +#define SVR_MAJ(svr) (((svr) >> 4) & 0xF) /* Major revision field*/ +#define SVR_MIN(svr) (((svr) >> 0) & 0xF) /* Minor revision field*/ /* Some parts define SVR[0:23] as the SOC version */ -#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ +#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */ /* whether MPC8xxxE (i.e. has SEC) */ #if defined(CONFIG_MPC85xx) -#define IS_E_PROCESSOR(svr) (svr & 0x80000) +#define IS_E_PROCESSOR(svr) (svr & 0x80000) #else #if defined(CONFIG_MPC83xx) -#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) +#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) #endif #endif @@ -979,98 +979,98 @@ * SVR_SOC_VER() Version Values */ -#define SVR_8533 0x803400 -#define SVR_8533_E 0x803C00 -#define SVR_8535 0x803701 -#define SVR_8535_E 0x803F01 -#define SVR_8536 0x803700 -#define SVR_8536_E 0x803F00 -#define SVR_8540 0x803000 -#define SVR_8541 0x807200 -#define SVR_8541_E 0x807A00 -#define SVR_8543 0x803200 -#define SVR_8543_E 0x803A00 -#define SVR_8544 0x803401 -#define SVR_8544_E 0x803C01 -#define SVR_8545 0x803102 -#define SVR_8545_E 0x803902 -#define SVR_8547_E 0x803901 -#define SVR_8548 0x803100 -#define SVR_8548_E 0x803900 -#define SVR_8555 0x807100 -#define SVR_8555_E 0x807900 -#define SVR_8560 0x807000 -#define SVR_8567 0x807600 -#define SVR_8567_E 0x807E00 -#define SVR_8568 0x807500 -#define SVR_8568_E 0x807D00 -#define SVR_8569 0x808000 -#define SVR_8569_E 0x808800 -#define SVR_8572 0x80E000 -#define SVR_8572_E 0x80E800 -#define SVR_P2020 0x80E200 -#define SVR_P2020_E 0x80EA00 +#define SVR_8533 0x803400 +#define SVR_8533_E 0x803C00 +#define SVR_8535 0x803701 +#define SVR_8535_E 0x803F01 +#define SVR_8536 0x803700 +#define SVR_8536_E 0x803F00 +#define SVR_8540 0x803000 +#define SVR_8541 0x807200 +#define SVR_8541_E 0x807A00 +#define SVR_8543 0x803200 +#define SVR_8543_E 0x803A00 +#define SVR_8544 0x803401 +#define SVR_8544_E 0x803C01 +#define SVR_8545 0x803102 +#define SVR_8545_E 0x803902 +#define SVR_8547_E 0x803901 +#define SVR_8548 0x803100 +#define SVR_8548_E 0x803900 +#define SVR_8555 0x807100 +#define SVR_8555_E 0x807900 +#define SVR_8560 0x807000 +#define SVR_8567 0x807600 +#define SVR_8567_E 0x807E00 +#define SVR_8568 0x807500 +#define SVR_8568_E 0x807D00 +#define SVR_8569 0x808000 +#define SVR_8569_E 0x808800 +#define SVR_8572 0x80E000 +#define SVR_8572_E 0x80E800 +#define SVR_P2020 0x80E200 +#define SVR_P2020_E 0x80EA00 -#define SVR_8610 0x80A000 -#define SVR_8641 0x809000 -#define SVR_8641D 0x809001 +#define SVR_8610 0x80A000 +#define SVR_8641 0x809000 +#define SVR_8641D 0x809001 #define _GLOBAL(n)\ - .globl n;\ + .globl n;\ n: /* Macros for setting and retrieving special purpose registers */ -#define stringify(s) tostring(s) -#define tostring(s) #s +#define stringify(s) tostring(s) +#define tostring(s) #s -#define mfdcr(rn) ({unsigned int rval; \ - asm volatile("mfdcr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) +#define mfdcr(rn) ({unsigned int rval; \ + asm volatile("mfdcr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) -#define mfmsr() ({unsigned int rval; \ - asm volatile("mfmsr %0" : "=r" (rval)); rval;}) -#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) +#define mfmsr() ({unsigned int rval; \ + asm volatile("mfmsr %0" : "=r" (rval)); rval;}) +#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) -#define mfspr(rn) ({unsigned int rval; \ - asm volatile("mfspr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) +#define mfspr(rn) ({unsigned int rval; \ + asm volatile("mfspr %0," stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) -#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) +#define tlbie(v) asm volatile("tlbie %0 \n sync" : : "r" (v)) /* Segment Registers */ -#define SR0 0 -#define SR1 1 -#define SR2 2 -#define SR3 3 -#define SR4 4 -#define SR5 5 -#define SR6 6 -#define SR7 7 -#define SR8 8 -#define SR9 9 -#define SR10 10 -#define SR11 11 -#define SR12 12 -#define SR13 13 -#define SR14 14 -#define SR15 15 +#define SR0 0 +#define SR1 1 +#define SR2 2 +#define SR3 3 +#define SR4 4 +#define SR5 5 +#define SR6 6 +#define SR7 7 +#define SR8 8 +#define SR9 9 +#define SR10 10 +#define SR11 11 +#define SR12 12 +#define SR13 13 +#define SR14 14 +#define SR15 15 #ifndef __ASSEMBLY__ struct cpu_type { - char name[15]; - u32 soc_ver; + char name[15]; + u32 soc_ver; }; struct cpu_type *identify_cpu(u32 ver); #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) #define CPU_TYPE_ENTRY(n, v) \ - { .name = #n, .soc_ver = SVR_##v, } + { .name = #n, .soc_ver = SVR_##v, } #else #if defined(CONFIG_MPC83xx) #define CPU_TYPE_ENTRY(x) {#x, SPR_##x} @@ -1120,65 +1120,65 @@ extern struct task_struct *last_task_used_altivec; * as soon as I get around to remapping the io areas with the BATs * to match the mac we can raise this. -- Cort */ -#define TASK_SIZE (0x80000000UL) +#define TASK_SIZE (0x80000000UL) /* This decides where the kernel will search for a free chunk of vm * space during mmap's. */ -#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) +#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3) typedef struct { - unsigned long seg; + unsigned long seg; } mm_segment_t; struct thread_struct { - unsigned long ksp; /* Kernel stack pointer */ - unsigned long wchan; /* Event task is sleeping on */ - struct pt_regs *regs; /* Pointer to saved register state */ - mm_segment_t fs; /* for get_fs() validation */ - void *pgdir; /* root of page-table tree */ - signed long last_syscall; - double fpr[32]; /* Complete floating point set */ - unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ - unsigned long fpscr; /* Floating point status */ + unsigned long ksp; /* Kernel stack pointer */ + unsigned long wchan; /* Event task is sleeping on */ + struct pt_regs *regs; /* Pointer to saved register state */ + mm_segment_t fs; /* for get_fs() validation */ + void *pgdir; /* root of page-table tree */ + signed long last_syscall; + double fpr[32]; /* Complete floating point set */ + unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ + unsigned long fpscr; /* Floating point status */ #ifdef CONFIG_ALTIVEC - vector128 vr[32]; /* Complete AltiVec set */ - vector128 vscr; /* AltiVec status */ - unsigned long vrsave; + vector128 vr[32]; /* Complete AltiVec set */ + vector128 vscr; /* AltiVec status */ + unsigned long vrsave; #endif /* CONFIG_ALTIVEC */ }; -#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) +#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) #define INIT_THREAD { \ - INIT_SP, /* ksp */ \ - 0, /* wchan */ \ - (struct pt_regs *)INIT_SP - 1, /* regs */ \ - KERNEL_DS, /*fs*/ \ - swapper_pg_dir, /* pgdir */ \ - 0, /* last_syscall */ \ - {0}, 0, 0 \ + INIT_SP, /* ksp */ \ + 0, /* wchan */ \ + (struct pt_regs *)INIT_SP - 1, /* regs */ \ + KERNEL_DS, /*fs*/ \ + swapper_pg_dir, /* pgdir */ \ + 0, /* last_syscall */ \ + {0}, 0, 0 \ } /* * Note: the vm_start and vm_end fields here should *not* - * be in kernel space. (Could vm_end == vm_start perhaps?) + * be in kernel space. (Could vm_end == vm_start perhaps?) */ #define INIT_MMAP { &init_mm, 0, 0x1000, NULL, \ - PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ - 1, NULL, NULL } + PAGE_SHARED, VM_READ | VM_WRITE | VM_EXEC, \ + 1, NULL, NULL } /* * Return saved PC of a blocked thread. For now, this is the "user" PC */ static inline unsigned long thread_saved_pc(struct thread_struct *t) { - return (t->regs) ? t->regs->nip : 0; + return (t->regs) ? t->regs->nip : 0; } -#define copy_segments(tsk, mm) do { } while (0) -#define release_segments(mm) do { } while (0) -#define forget_segments() do { } while (0) +#define copy_segments(tsk, mm) do { } while (0) +#define release_segments(mm) do { } while (0) +#define forget_segments() do { } while (0) unsigned long get_wchan(struct task_struct *p); @@ -1190,16 +1190,16 @@ unsigned long get_wchan(struct task_struct *p); */ #define THREAD_SIZE (2*PAGE_SIZE) #define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define free_task_struct(p) free_pages((unsigned long)(p),1) -#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) + ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) +#define free_task_struct(p) free_pages((unsigned long)(p),1) +#define get_task_struct(tsk) atomic_inc(&mem_map[MAP_NR(tsk)].count) /* in process.c - for early bootup debug -- Cort */ int ll_printk(const char *, ...); void ll_puts(const char *); -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) +#define init_task (init_task_union.task) +#define init_stack (init_task_union.stack) /* In misc.c */ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); @@ -1212,7 +1212,7 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); #define have_of 0 #elif defined(CONFIG_OAK) #define _machine _MACH_oak -#define have_of 0 +#define have_of 0 #elif defined(CONFIG_WALNUT) #define _machine _MACH_walnut #define have_of 0 diff --git a/libcpu/ppc/ppc405/include/asm/ptrace.h b/libcpu/ppc/ppc405/include/asm/ptrace.h index d531de889b..d450803f96 100644 --- a/libcpu/ppc/ppc405/include/asm/ptrace.h +++ b/libcpu/ppc/ppc405/include/asm/ptrace.h @@ -26,27 +26,27 @@ #define PPC_REG unsigned long #endif struct pt_regs { - PPC_REG gpr[32]; - PPC_REG nip; - PPC_REG msr; - PPC_REG orig_gpr3; /* Used for restarting system calls */ - PPC_REG ctr; - PPC_REG link; - PPC_REG xer; - PPC_REG ccr; - PPC_REG mq; /* 601 only (not used at present) */ - /* Used on APUS to hold IPL value. */ - PPC_REG trap; /* Reason for being here */ - PPC_REG dar; /* Fault registers */ - PPC_REG dsisr; - PPC_REG result; /* Result of a system call */ + PPC_REG gpr[32]; + PPC_REG nip; + PPC_REG msr; + PPC_REG orig_gpr3; /* Used for restarting system calls */ + PPC_REG ctr; + PPC_REG link; + PPC_REG xer; + PPC_REG ccr; + PPC_REG mq; /* 601 only (not used at present) */ + /* Used on APUS to hold IPL value. */ + PPC_REG trap; /* Reason for being here */ + PPC_REG dar; /* Fault registers */ + PPC_REG dsisr; + PPC_REG result; /* Result of a system call */ }__attribute__((packed)) CELL_STACK_FRAME_t; #endif -#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ +#define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ /* Size of stack frame allocated when calling signal handler. */ -#define __SIGNAL_FRAMESIZE 64 +#define __SIGNAL_FRAMESIZE 64 #define instruction_pointer(regs) ((regs)->nip) #define user_mode(regs) (((regs)->msr & MSR_PR) != 0) @@ -56,51 +56,51 @@ struct pt_regs { * These can't be changed without breaking binary compatibility * with MkLinux, etc. */ -#define PT_R0 0 -#define PT_R1 1 -#define PT_R2 2 -#define PT_R3 3 -#define PT_R4 4 -#define PT_R5 5 -#define PT_R6 6 -#define PT_R7 7 -#define PT_R8 8 -#define PT_R9 9 -#define PT_R10 10 -#define PT_R11 11 -#define PT_R12 12 -#define PT_R13 13 -#define PT_R14 14 -#define PT_R15 15 -#define PT_R16 16 -#define PT_R17 17 -#define PT_R18 18 -#define PT_R19 19 -#define PT_R20 20 -#define PT_R21 21 -#define PT_R22 22 -#define PT_R23 23 -#define PT_R24 24 -#define PT_R25 25 -#define PT_R26 26 -#define PT_R27 27 -#define PT_R28 28 -#define PT_R29 29 -#define PT_R30 30 -#define PT_R31 31 +#define PT_R0 0 +#define PT_R1 1 +#define PT_R2 2 +#define PT_R3 3 +#define PT_R4 4 +#define PT_R5 5 +#define PT_R6 6 +#define PT_R7 7 +#define PT_R8 8 +#define PT_R9 9 +#define PT_R10 10 +#define PT_R11 11 +#define PT_R12 12 +#define PT_R13 13 +#define PT_R14 14 +#define PT_R15 15 +#define PT_R16 16 +#define PT_R17 17 +#define PT_R18 18 +#define PT_R19 19 +#define PT_R20 20 +#define PT_R21 21 +#define PT_R22 22 +#define PT_R23 23 +#define PT_R24 24 +#define PT_R25 25 +#define PT_R26 26 +#define PT_R27 27 +#define PT_R28 28 +#define PT_R29 29 +#define PT_R30 30 +#define PT_R31 31 -#define PT_NIP 32 -#define PT_MSR 33 +#define PT_NIP 32 +#define PT_MSR 33 #ifdef __KERNEL__ #define PT_ORIG_R3 34 #endif -#define PT_CTR 35 -#define PT_LNK 36 -#define PT_XER 37 -#define PT_CCR 38 -#define PT_MQ 39 +#define PT_CTR 35 +#define PT_LNK 36 +#define PT_XER 37 +#define PT_CCR 38 +#define PT_MQ 39 -#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ +#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */ #define PT_FPR31 (PT_FPR0 + 2*31) #define PT_FPSCR (PT_FPR0 + 2*32 + 1) diff --git a/libcpu/ppc/ppc405/include/asm/types.h b/libcpu/ppc/ppc405/include/asm/types.h index 6413895325..88c38e62cc 100644 --- a/libcpu/ppc/ppc405/include/asm/types.h +++ b/libcpu/ppc/ppc405/include/asm/types.h @@ -27,7 +27,7 @@ __extension__ typedef unsigned long long __u64; #endif typedef struct { - __u32 u[4]; + __u32 u[4]; } __attribute__((aligned(16))) vector128; #ifdef __KERNEL__ diff --git a/libcpu/ppc/ppc405/include/config.h b/libcpu/ppc/ppc405/include/config.h index dc01549b01..d464a3e371 100644 --- a/libcpu/ppc/ppc405/include/config.h +++ b/libcpu/ppc/ppc405/include/config.h @@ -1,25 +1,25 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_405EP 1 /* this is a PPC405 CPU */ -#define CONFIG_4xx 1 /* member of PPC4xx family */ +#define CONFIG_405EP 1 /* this is a PPC405 CPU */ +#define CONFIG_4xx 1 /* member of PPC4xx family */ -#define CONFIG_SYS_DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CONFIG_SYS_DCACHE_SIZE (16 << 10)/* For AMCC 405 CPUs */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_CLK_RECFG 0 /* Config the sys clks */ +#define CONFIG_SYS_CLK_RECFG 0 /* Config the sys clks */ #define CONFIG_SYS_CLK_FREQ 33333333 /*3300000*//* external frequency to pll */ #define CONFIG_SYS_HZ 100 -#define CONFIG_SYS_PIT_RELOAD (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) +#define CONFIG_SYS_PIT_RELOAD (CONFIG_SYS_CLK_FREQ / CONFIG_SYS_HZ) /* * UART */ -#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} @@ -33,26 +33,26 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ -#define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE 1 +#define CONFIG_SYS_BASE_BAUD 691200 +#define CONFIG_UART1_CONSOLE 1 /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) */ -#define CONFIG_SYS_FLASH_BASE 0xFFE00000 +#define CONFIG_SYS_FLASH_BASE 0xFFE00000 /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ #define CONFIG_SYS_FLASH_ADDR0 0x555 #define CONFIG_SYS_FLASH_ADDR1 0x2aa #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short -#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */ diff --git a/libcpu/ppc/ppc405/interrupt.c b/libcpu/ppc/ppc405/interrupt.c index 27a528e2f0..f072dd07e1 100644 --- a/libcpu/ppc/ppc405/interrupt.c +++ b/libcpu/ppc/ppc405/interrupt.c @@ -28,18 +28,18 @@ rt_uint32_t rt_thread_switch_interrput_flag; rt_isr_handler_t rt_hw_interrupt_handler(rt_uint32_t vector, void* param) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); - return RT_NULL; + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + return RT_NULL; } void uic_irq_ack(unsigned int vec) { - mtdcr(uic0sr, UIC_MASK(vec)); + mtdcr(uic0sr, UIC_MASK(vec)); } void uic_int_handler (unsigned int vec) { - rt_interrupt_enter(); + rt_interrupt_enter(); /* Allow external interrupts to the CPU. */ if (isr_table [vec].handler != 0) @@ -47,91 +47,91 @@ void uic_int_handler (unsigned int vec) (*isr_table[vec].handler)(vec, isr_table[vec].param); } uic_irq_ack(vec); - + rt_interrupt_leave(); } /* handler for UIC interrupt */ void uic_interrupt(rt_uint32_t uic_base, int vec_base) { - int vec; - rt_uint32_t uic_msr; - rt_uint32_t msr_shift; + int vec; + rt_uint32_t uic_msr; + rt_uint32_t msr_shift; - /* - * Read masked interrupt status register to determine interrupt source - */ - uic_msr = get_dcr(uic_base + UIC_MSR); - msr_shift = uic_msr; - vec = vec_base; + /* + * Read masked interrupt status register to determine interrupt source + */ + uic_msr = get_dcr(uic_base + UIC_MSR); + msr_shift = uic_msr; + vec = vec_base; - while (msr_shift != 0) - { - if (msr_shift & 0x80000000) - uic_int_handler(vec); + while (msr_shift != 0) + { + if (msr_shift & 0x80000000) + uic_int_handler(vec); - /* - * Shift msr to next position and increment vector - */ - msr_shift <<= 1; - vec++; - } + /* + * Shift msr to next position and increment vector + */ + msr_shift <<= 1; + vec++; + } } -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, +rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, void* param, const char* name) { - int intVal; + int intVal; rt_isr_handler_t old_handler; - if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS)) - { + if (((int)vector < 0) || ((int) vector >= MAX_HANDLERS)) + { return RT_NULL; /* out of range */ - } - + } + /* install the handler in the system interrupt table */ intVal = rt_hw_interrupt_disable (); /* lock interrupts to prevent races */ old_handler = isr_table[vector].handler; isr_table[vector].handler = new_handler; isr_table[vector].param = param; - + rt_hw_interrupt_enable (intVal); } void rt_hw_interrupt_mask(int vector) { - mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector)); + mtdcr(uic0er, mfdcr(uic0er) & ~UIC_MASK(vector)); } void rt_hw_interrupt_unmask(int vector) { - mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector)); + mtdcr(uic0er, mfdcr(uic0er) | UIC_MASK(vector)); } void rt_hw_interrupt_init() { - int vector; + int vector; rt_uint32_t pit_value; pit_value = RT_TICK_PER_SECOND * (100000000 / RT_CPU_FREQ); /* enable pit */ - mtspr(SPRN_PIT, pit_value); - mtspr(SPRN_TCR, 0x4400000); + mtspr(SPRN_PIT, pit_value); + mtspr(SPRN_TCR, 0x4400000); - /* set default interrupt handler */ + /* set default interrupt handler */ for (vector = 0; vector < MAX_HANDLERS; vector++) { - isr_table [vector].handler = (rt_isr_handler_t)rt_hw_interrupt_handler; + isr_table [vector].handler = (rt_isr_handler_t)rt_hw_interrupt_handler; isr_table [vector].param = RT_NULL; } - /* initialize interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrput_flag = 0; + /* initialize interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrput_flag = 0; } /*@}*/ diff --git a/libcpu/ppc/ppc405/io.h b/libcpu/ppc/ppc405/io.h index 32fcd56307..28341ead64 100644 --- a/libcpu/ppc/ppc405/io.h +++ b/libcpu/ppc/ppc405/io.h @@ -12,82 +12,82 @@ */ static inline int in_8(const volatile unsigned char __iomem *addr) { - int ret; + int ret; - __asm__ __volatile__( - "sync; lbz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__( + "sync; lbz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; } static inline void out_8(volatile unsigned char __iomem *addr, int val) { - __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val)); } extern inline int in_le16(const volatile unsigned short __iomem *addr) { - int ret; + int ret; - __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; + __asm__ __volatile__("sync; lhbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; } extern inline int in_be16(const volatile unsigned short __iomem *addr) { - int ret; + int ret; - __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__("sync; lhz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; } extern inline void out_le16(volatile unsigned short __iomem *addr, int val) { - __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); + __asm__ __volatile__("sync; sthbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); } extern inline void out_be16(volatile unsigned short __iomem *addr, int val) { - __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("sync; sth%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } extern inline unsigned in_le32(const volatile unsigned __iomem *addr) { - unsigned ret; + unsigned ret; - __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; + __asm__ __volatile__("sync; lwbrx %0,0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : + "r" (addr), "m" (*addr)); + return ret; } extern inline unsigned in_be32(const volatile unsigned __iomem *addr) { - unsigned ret; + unsigned ret; - __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : "m" (*addr)); - return ret; + __asm__ __volatile__("sync; lwz%U1%X1 %0,%1;\n" + "twi 0,%0,0;\n" + "isync" : "=r" (ret) : "m" (*addr)); + return ret; } extern inline void out_le32(volatile unsigned __iomem *addr, int val) { - __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : - "r" (val), "r" (addr)); + __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr) : + "r" (val), "r" (addr)); } extern inline void out_be32(volatile unsigned __iomem *addr, int val) { - __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); + __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); } #endif diff --git a/libcpu/ppc/ppc405/serial.c b/libcpu/ppc/ppc405/serial.c index ac68a13748..1fc9039769 100644 --- a/libcpu/ppc/ppc405/serial.c +++ b/libcpu/ppc/ppc405/serial.c @@ -12,18 +12,18 @@ #define UCR1_UDIV_POS 8 #define UDIV_MAX 127 -#define UART_RBR 0x00 -#define UART_THR 0x00 -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 -#define UART_DLL 0x00 -#define UART_DLM 0x01 +#define UART_RBR 0x00 +#define UART_THR 0x00 +#define UART_IER 0x01 +#define UART_IIR 0x02 +#define UART_FCR 0x02 +#define UART_LCR 0x03 +#define UART_MCR 0x04 +#define UART_LSR 0x05 +#define UART_MSR 0x06 +#define UART_SCR 0x07 +#define UART_DLL 0x00 +#define UART_DLM 0x01 /*-----------------------------------------------------------------------------+ | Line Status Register. @@ -40,280 +40,280 @@ /* PPC405 serial device */ struct rt_ppc405_serial { - /* inherit from device */ - struct rt_device parent; + /* inherit from device */ + struct rt_device parent; - rt_uint32_t hw_base; - rt_uint32_t irqno; - rt_uint32_t baudrate; + rt_uint32_t hw_base; + rt_uint32_t irqno; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; struct rt_ppc405_serial ppc405_serial; /* serial character device */ static rt_err_t rt_serial_init (rt_device_t dev) { - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_ppc405_serial* device; - device = (struct rt_ppc405_serial*) dev; - - RT_ASSERT(device != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* Enable "RX Data Available" Interrupt on UART */ - out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01); - /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */ - out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1); + struct rt_ppc405_serial* device; + device = (struct rt_ppc405_serial*) dev; - /* init UART rx interrupt */ - rt_hw_interrupt_unmask(device->irqno); - } + RT_ASSERT(device != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* Enable "RX Data Available" Interrupt on UART */ + out_8((rt_uint8_t*)device->hw_base + UART_IER, 0x01); + /* Setup UART FIFO: RX trigger level: 1 byte, Enable FIFO */ + out_8((rt_uint8_t*)device->hw_base + UART_FCR, 1); - return RT_EOK; + /* init UART rx interrupt */ + rt_hw_interrupt_unmask(device->irqno); + } + + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_ppc405_serial* device; - device = (struct rt_ppc405_serial*) dev; - - RT_ASSERT(device != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* mask UART rx interrupt */ - rt_hw_interrupt_mask(device->irqno); - } + struct rt_ppc405_serial* device; + device = (struct rt_ppc405_serial*) dev; + + RT_ASSERT(device != RT_NULL); + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* mask UART rx interrupt */ + rt_hw_interrupt_mask(device->irqno); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_control(rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_ppc405_serial* device; + rt_uint8_t* ptr; + struct rt_ppc405_serial* device; - device = (struct rt_ppc405_serial*) dev; - RT_ASSERT(device != RT_NULL); + device = (struct rt_ppc405_serial*) dev; + RT_ASSERT(device != RT_NULL); - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (device->read_index != device->save_index) - { - *ptr = device->rx_buffer[device->read_index]; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (device->read_index != device->save_index) + { + *ptr = device->rx_buffer[device->read_index]; - device->read_index ++; - if (device->read_index >= RT_UART_RX_BUFFER_SIZE) - device->read_index = 0; - } - else - { - /* no data in rx buffer */ + device->read_index ++; + if (device->read_index >= RT_UART_RX_BUFFER_SIZE) + device->read_index = 0; + } + else + { + /* no data in rx buffer */ - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - ptr ++; size --; - } + ptr ++; size --; + } - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } - /* polling mode */ - RT_ASSERT(0); + /* polling mode */ + RT_ASSERT(0); - return (rt_size_t)ptr - (rt_size_t)buffer; + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_size_t rt_serial_write(rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - char *ptr; - struct rt_ppc405_serial* device; + char *ptr; + struct rt_ppc405_serial* device; + + device = (struct rt_ppc405_serial*) dev; + RT_ASSERT(device != RT_NULL); + + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* not support */ + RT_ASSERT(0); + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) + { + /* not support */ + RT_ASSERT(0); + } - device = (struct rt_ppc405_serial*) dev; - RT_ASSERT(device != RT_NULL); + /* polling write */ + ptr = (char *)buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* not support */ - RT_ASSERT(0); - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_TX) - { - /* not support */ - RT_ASSERT(0); - } + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* stream mode */ + while (size) + { + if (*ptr == '\n') + { + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r'); + } - /* polling write */ - ptr = (char *)buffer; - - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* stream mode */ - while (size) - { - if (*ptr == '\n') - { - while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); - out_8((rt_uint8_t*)device->hw_base + UART_THR, '\r'); - } + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); - while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); - out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); + ptr ++; + size --; + } + } + else + { + while (size) + { + while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); + out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); - ptr ++; - size --; - } - } - else - { - while (size) - { - while ((in_8((rt_uint8_t*)device->hw_base + UART_LSR) & 0x20) != 0x20); - out_8((rt_uint8_t*)device->hw_base + UART_THR, *ptr); - - ptr ++; - size --; - } - } - - return (rt_size_t) ptr - (rt_size_t) buffer; + ptr ++; + size --; + } + } + + return (rt_size_t) ptr - (rt_size_t) buffer; } void rt_serial_set_baudrate(struct rt_ppc405_serial* device) { - rt_uint32_t bdiv; + rt_uint32_t bdiv; - bdiv = 115200; - out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv); /* set baudrate divisor */ - out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ + bdiv = 115200; + out_8((rt_uint8_t *)device->hw_base + UART_DLL, bdiv); /* set baudrate divisor */ + out_8((rt_uint8_t *)device->hw_base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ } void rt_serial_isr(int irqno, void* param) { - unsigned char status; - struct rt_ppc405_serial *device; + unsigned char status; + struct rt_ppc405_serial *device; + + device = (struct rt_ppc405_serial*) param; + status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); - device = (struct rt_ppc405_serial*) param; - status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); + if (status & 0x01) + { + rt_base_t level; - if (status & 0x01) - { - rt_base_t level; + while (status & 0x01) + { + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - while (status & 0x01) - { - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* read character */ + device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base)); + device->save_index ++; + if (device->save_index >= RT_UART_RX_BUFFER_SIZE) + device->save_index = 0; - /* read character */ - device->rx_buffer[device->save_index] = (0xff & (int) in_8((rt_uint8_t *)device->hw_base)); - device->save_index ++; - if (device->save_index >= RT_UART_RX_BUFFER_SIZE) - device->save_index = 0; - - /* if the next position is read index, discard this 'read char' */ - if (device->save_index == device->read_index) - { - device->read_index ++; - if (device->read_index >= RT_UART_RX_BUFFER_SIZE) - device->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (device->save_index == device->read_index) + { + device->read_index ++; + if (device->read_index >= RT_UART_RX_BUFFER_SIZE) + device->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - /* check error */ - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) - { - out_8((rt_uint8_t *)device->hw_base + UART_LSR, - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } + /* check error */ + if ((status & ( asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1 )) != 0) + { + out_8((rt_uint8_t *)device->hw_base + UART_LSR, + asyncLSRFramingError1 | + asyncLSROverrunError1 | + asyncLSRParityError1 | + asyncLSRBreakInterrupt1); + } - status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); - } + status = in_8((rt_uint8_t *)device->hw_base + UART_LSR); + } - /* invoke callback */ - if(device->parent.rx_indicate != RT_NULL) - { - device->parent.rx_indicate(&device->parent, 1); - } - } + /* invoke callback */ + if(device->parent.rx_indicate != RT_NULL) + { + device->parent.rx_indicate(&device->parent, 1); + } + } } void rt_hw_serial_init(void) { - volatile rt_uint8_t val; - struct rt_ppc405_serial* device; + volatile rt_uint8_t val; + struct rt_ppc405_serial* device; + + device = (struct rt_ppc405_serial*) &ppc405_serial; + device->parent.type = RT_Device_Class_Char; - device = (struct rt_ppc405_serial*) &ppc405_serial; - device->parent.type = RT_Device_Class_Char; - - device->hw_base = UART0_BASE; - device->baudrate = 115200; - device->irqno = VECNUM_U0; - rt_hw_interrupt_install(device->irqno, rt_serial_isr, device, "serial"); /* install isr */ + device->hw_base = UART0_BASE; + device->baudrate = 115200; + device->irqno = VECNUM_U0; + rt_hw_interrupt_install(device->irqno, rt_serial_isr, device, "serial"); /* install isr */ - rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer)); - device->read_index = device->save_index = 0; + rt_memset(device->rx_buffer, 0, sizeof(device->rx_buffer)); + device->read_index = device->save_index = 0; - out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */ - /* setup baudrate */ - rt_serial_set_baudrate(device); - out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */ - out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */ - val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */ - out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */ - out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */ + out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x80); /* set DLAB bit */ + /* setup baudrate */ + rt_serial_set_baudrate(device); + out_8((rt_uint8_t *)device->hw_base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ + out_8((rt_uint8_t *)device->hw_base + UART_FCR, 0x00); /* disable FIFO */ + out_8((rt_uint8_t *)device->hw_base + UART_MCR, 0x00); /* no modem control DTR RTS */ + val = in_8((rt_uint8_t *)device->hw_base + UART_LSR); /* clear line status */ + val = in_8((rt_uint8_t *)device->hw_base + UART_RBR); /* read receive buffer */ + out_8((rt_uint8_t *)device->hw_base + UART_SCR, 0x00); /* set scratchpad */ + out_8((rt_uint8_t *)device->hw_base + UART_IER, 0x00); /* set interrupt enable reg */ - device->parent.type = RT_Device_Class_Char; - device->parent.init = rt_serial_init; - device->parent.open = rt_serial_open; - device->parent.close = rt_serial_close; - device->parent.read = rt_serial_read; - device->parent.write = rt_serial_write; - device->parent.control = rt_serial_control; - device->parent.user_data = RT_NULL; + device->parent.type = RT_Device_Class_Char; + device->parent.init = rt_serial_init; + device->parent.open = rt_serial_open; + device->parent.close = rt_serial_close; + device->parent.read = rt_serial_read; + device->parent.write = rt_serial_write; + device->parent.control = rt_serial_control; + device->parent.user_data = RT_NULL; - rt_device_register(&device->parent, - "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); + rt_device_register(&device->parent, + "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM); } diff --git a/libcpu/ppc/ppc405/traps.c b/libcpu/ppc/ppc405/traps.c index 1deecbc92b..3ee754da23 100644 --- a/libcpu/ppc/ppc405/traps.c +++ b/libcpu/ppc/ppc405/traps.c @@ -7,8 +7,8 @@ extern unsigned long search_exception_table(unsigned long); /* THIS NEEDS CHANGING to use the board info structure. */ -#define END_OF_MEM 0x800000 -#define UICB0_ALL 0 +#define END_OF_MEM 0x800000 +#define UICB0_ALL 0 #define ESR_MCI 0x80000000 #define ESR_PIL 0x08000000 diff --git a/libcpu/risc-v/common/cpuport.c b/libcpu/risc-v/common/cpuport.c index 6cb8aaf3e7..622e1bd321 100644 --- a/libcpu/risc-v/common/cpuport.c +++ b/libcpu/risc-v/common/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/common/cpuport.h b/libcpu/risc-v/common/cpuport.h index d6cec2f0cf..e625d9f91f 100644 --- a/libcpu/risc-v/common/cpuport.h +++ b/libcpu/risc-v/common/cpuport.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -30,13 +30,13 @@ #define FSTORE fsd #define FLOAD fld #define FREGBYTES 8 -#define rv_floatreg_t rt_int64_t +#define rv_floatreg_t rt_int64_t #endif #ifdef ARCH_RISCV_FPU_S #define FSTORE fsw #define FLOAD flw #define FREGBYTES 4 -#define rv_floatreg_t rt_int32_t +#define rv_floatreg_t rt_int32_t #endif #endif diff --git a/libcpu/risc-v/common/riscv-ops.h b/libcpu/risc-v/common/riscv-ops.h index 0b321c6de4..35d009ad53 100644 --- a/libcpu/risc-v/common/riscv-ops.h +++ b/libcpu/risc-v/common/riscv-ops.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/common/riscv-plic.h b/libcpu/risc-v/common/riscv-plic.h index 1da14b2e45..53e19d2962 100644 --- a/libcpu/risc-v/common/riscv-plic.h +++ b/libcpu/risc-v/common/riscv-plic.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/k210/cpuport_smp.c b/libcpu/risc-v/k210/cpuport_smp.c index 8c57dfeafc..113df9b3e2 100644 --- a/libcpu/risc-v/k210/cpuport_smp.c +++ b/libcpu/risc-v/k210/cpuport_smp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/k210/interrupt.c b/libcpu/risc-v/k210/interrupt.c index b582599daf..934acbdbf8 100644 --- a/libcpu/risc-v/k210/interrupt.c +++ b/libcpu/risc-v/k210/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/k210/tick.c b/libcpu/risc-v/k210/tick.c index 144f7f1fff..2a76b50b6d 100644 --- a/libcpu/risc-v/k210/tick.c +++ b/libcpu/risc-v/k210/tick.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/k210/tick.h b/libcpu/risc-v/k210/tick.h index 0821004263..0bfd6f62e8 100644 --- a/libcpu/risc-v/k210/tick.h +++ b/libcpu/risc-v/k210/tick.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/nuclei/cpuport.c b/libcpu/risc-v/nuclei/cpuport.c index 717e9bb1c7..e74d174a54 100644 --- a/libcpu/risc-v/nuclei/cpuport.c +++ b/libcpu/risc-v/nuclei/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 @@ -26,23 +26,23 @@ /** * @brief from thread used interrupt context switch - * + * */ volatile rt_ubase_t rt_interrupt_from_thread = 0; /** * @brief to thread used interrupt context switch - * + * */ volatile rt_ubase_t rt_interrupt_to_thread = 0; /** * @brief flag to indicate context switch in interrupt or not - * + * */ volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0; /** * @brief thread stack frame of saved context - * + * */ struct rt_hw_stack_frame { @@ -121,7 +121,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, /** * @brief Do rt-thread context switch in interrupt context - * + * * @param from thread sp of from thread * @param to thread sp of to thread */ @@ -137,7 +137,7 @@ void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to) /** * @brief Do rt-thread context switch in task context - * + * * @param from thread sp of from thread * @param to thread sp of to thread */ @@ -150,7 +150,7 @@ void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to) /** * @brief shutdown CPU - * + * */ RT_WEAK void rt_hw_cpu_shutdown() { @@ -166,9 +166,9 @@ RT_WEAK void rt_hw_cpu_shutdown() /** * @brief Do extra task switch code - * + * * @details - * + * * - Clear software timer interrupt request flag * - clear rt_thread_switch_interrupt_flag to 0 */ @@ -181,9 +181,9 @@ void rt_hw_taskswitch(void) /** * @brief Setup systimer and software timer interrupt - * - * @details - * + * + * @details + * * - Set Systimer interrupt as NON-VECTOR interrupt with lowest interrupt level * - Set software timer interrupt as VECTOR interrupt with lowest interrupt level * - Enable these two interrupts @@ -216,7 +216,7 @@ void rt_hw_ticksetup(void) /** * @brief This is the timer interrupt service routine. - * + * */ void SysTick_Handler(void) { @@ -235,13 +235,13 @@ void SysTick_Handler(void) /** * @brief Disable cpu interrupt - * + * * @details - * + * * - Disable cpu interrupt by clear MIE bit in MSTATUS * - Return the previous value in MSTATUS before clear MIE bit - * - * @return the previous value in MSTATUS before clear MIE bit + * + * @return the previous value in MSTATUS before clear MIE bit */ rt_base_t rt_hw_interrupt_disable(void) { @@ -250,7 +250,7 @@ rt_base_t rt_hw_interrupt_disable(void) /** * @brief Restore previous saved interrupt status - * + * * @param level previous saved MSTATUS value */ void rt_hw_interrupt_enable(rt_base_t level) diff --git a/libcpu/risc-v/nuclei/cpuport.h b/libcpu/risc-v/nuclei/cpuport.h index 3736f0078a..1f9634d4b1 100644 --- a/libcpu/risc-v/nuclei/cpuport.h +++ b/libcpu/risc-v/nuclei/cpuport.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * Copyright (c) 2019-Present Nuclei Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 diff --git a/libcpu/risc-v/rv32m1/interrupt.c b/libcpu/risc-v/rv32m1/interrupt.c index 72cb344ff7..8da0dcfda6 100644 --- a/libcpu/risc-v/rv32m1/interrupt.c +++ b/libcpu/risc-v/rv32m1/interrupt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/risc-v/t-head/e906/cpuport.c b/libcpu/risc-v/t-head/e906/cpuport.c index 998bfdc340..0eaf5ffbce 100644 --- a/libcpu/risc-v/t-head/e906/cpuport.c +++ b/libcpu/risc-v/t-head/e906/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -131,7 +131,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, /** - * This function will disable global interrupt + * This function will disable global interrupt * * @param none * @@ -145,7 +145,7 @@ rt_base_t rt_hw_interrupt_disable(void) } /** - * This function will ennable global interrupt + * This function will ennable global interrupt * * @param level not used * diff --git a/libcpu/risc-v/t-head/e906/cpuport.h b/libcpu/risc-v/t-head/e906/cpuport.h index 90efc07653..20302f44aa 100644 --- a/libcpu/risc-v/t-head/e906/cpuport.h +++ b/libcpu/risc-v/t-head/e906/cpuport.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -42,13 +42,13 @@ #define FSTORE fsd #define FLOAD fld #define FREGBYTES 8 -#define rv_floatreg_t rt_int64_t +#define rv_floatreg_t rt_int64_t #endif #ifdef ARCH_RISCV_FPU_S #define FSTORE fsw #define FLOAD flw #define FREGBYTES 4 -#define rv_floatreg_t rt_int32_t +#define rv_floatreg_t rt_int32_t #endif #endif diff --git a/libcpu/rx/cpuport.c b/libcpu/rx/cpuport.c index a01f598e99..00f9e26ba9 100644 --- a/libcpu/rx/cpuport.c +++ b/libcpu/rx/cpuport.c @@ -34,9 +34,9 @@ rt_uint32_t rt_thread_switch_interrupt_flag; /* stack frame*/ struct stack_frame { - rt_uint32_t ACCLO; + rt_uint32_t ACCLO; rt_uint32_t ACCHI; - rt_uint32_t FPSW; + rt_uint32_t FPSW; rt_uint32_t R1; rt_uint32_t R2; rt_uint32_t R3; @@ -53,21 +53,21 @@ struct stack_frame rt_uint32_t R14; rt_uint32_t R15; //there is not R0 register,it is special for stack pointer - rt_uint32_t PC; - rt_uint32_t PSW; + rt_uint32_t PC; + rt_uint32_t PSW; }; /** * Initilial the thread stack. - * + * * @author LXZ (2014/11/8) - * - * @param void* tentry - * @param void* parameter - * @param rt_uint8_t* stack_addr - * @param void* texit - * - * @return rt_uint8_t* + * + * @param void* tentry + * @param void* parameter + * @param rt_uint8_t* stack_addr + * @param void* texit + * + * @return rt_uint8_t* */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) @@ -77,7 +77,7 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, unsigned long i; stk = (unsigned long *)stack_addr; - *(stk) = (unsigned long)texit; + *(stk) = (unsigned long)texit; stack_frame = (struct stack_frame *)(stack_addr - sizeof(struct stack_frame)) ; //Initilial all register @@ -85,12 +85,12 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, { ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef; } - + stack_frame->PSW = (unsigned long)0x00030000 ; /* psw */ stack_frame->PC = (unsigned long)tentry; /* thread entery*/ stack_frame->R1 = (unsigned long )parameter; /* r1 : parameter */ stack_frame->FPSW = 0x00000100; /* fpsw */ - + return(rt_uint8_t *)stack_frame; } @@ -99,16 +99,16 @@ extern void list_thread(void); #endif extern rt_thread_t rt_current_thread; /** - * deal exception - * + * deal exception + * * @author LXZ (2014/11/8) - * - * @param struct stack_frame* exception_contex + * + * @param struct stack_frame* exception_contex */ void rt_hw_hard_fault_exception(struct stack_frame* exception_contex) { if (exception_contex != RT_NULL) { - rt_kprintf("psw: 0x%08x\n", exception_contex->PSW); + rt_kprintf("psw: 0x%08x\n", exception_contex->PSW); rt_kprintf("pc: 0x%08x\n", exception_contex->PC); rt_kprintf("r0: 0x%08x\n", exception_contex->R1); rt_kprintf("r0: 0x%08x\n", exception_contex->R2); @@ -134,17 +134,17 @@ void rt_hw_hard_fault_exception(struct stack_frame* exception_contex) list_thread(); #endif while (1); - + } /** * switch thread in interrupt - * + * * @author LXZ (2014/11/8) - * - * @param rt_uint32_t from - * @param rt_uint32_t to + * + * @param rt_uint32_t from + * @param rt_uint32_t to */ void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) { @@ -159,11 +159,11 @@ void rt_hw_context_switch(rt_uint32_t from, rt_uint32_t to) } /** * switch thread out the interrupt - * + * * @author LXZ (2014/11/8) - * - * @param rt_uint32_t from - * @param rt_uint32_t to + * + * @param rt_uint32_t from + * @param rt_uint32_t to */ void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) { @@ -179,7 +179,7 @@ void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_uint32_t to) /** * shut down the chip - * + * * @author LXZ (2014/11/8) */ RT_WEAK void rt_hw_cpu_shutdown(void) @@ -190,10 +190,10 @@ RT_WEAK void rt_hw_cpu_shutdown(void) } /** * switch to the first thread,it just call one time - * + * * @author LXZ (2014/11/8) - * - * @param rt_uint32_t to + * + * @param rt_uint32_t to */ void rt_hw_context_switch_to(rt_uint32_t to) { diff --git a/libcpu/sim/posix/cpu_port.c b/libcpu/sim/posix/cpu_port.c index eb1ae4865c..dc3e9379dd 100644 --- a/libcpu/sim/posix/cpu_port.c +++ b/libcpu/sim/posix/cpu_port.c @@ -173,8 +173,8 @@ static void *thread_run(void *parameter) /*TODO: * 最后一行的pthread_exit永远没有机会执行，这是因为在threead->exit函数中 * 会发生线程切换，并永久将此pthread线程挂起，所以更完美的解决方案是在这 - * 里发送信号给主线程，主线程中再次唤醒此线程令其自动退出。 - */ + * 里发送信号给主线程，主线程中再次唤醒此线程令其自动退出。 + */ //sem_destroy(&thread->sem); pthread_exit(NULL); diff --git a/libcpu/sim/win32/cpu_port.c b/libcpu/sim/win32/cpu_port.c index cc8ad9a25c..621420e7bf 100644 --- a/libcpu/sim/win32/cpu_port.c +++ b/libcpu/sim/win32/cpu_port.c @@ -5,7 +5,7 @@ * Version : V1.00.00 * * By : prife -* Version : V1.00.01 +* Version : V1.00.01 ************************************************************************************************************************ */ @@ -47,10 +47,10 @@ const DWORD MS_VC_EXCEPTION=0x406D1388; #pragma pack(push,8) typedef struct tagTHREADNAME_INFO { - DWORD dwType; // Must be 0x1000. - LPCSTR szName; // Pointer to name (in user addr space). - DWORD dwThreadID; // Thread ID (-1=caller thread). - DWORD dwFlags; // Reserved for future use, must be zero. + DWORD dwType; // Must be 0x1000. + LPCSTR szName; // Pointer to name (in user addr space). + DWORD dwThreadID; // Thread ID (-1=caller thread). + DWORD dwFlags; // Reserved for future use, must be zero. } THREADNAME_INFO; #pragma pack(pop) @@ -115,19 +115,19 @@ static DWORD WINAPI ThreadforKeyGet(LPVOID lpParam); static void SetThreadName(DWORD dwThreadID, char* threadName) { #if defined(_MSC_VER) - THREADNAME_INFO info; - info.dwType = 0x1000; - info.szName = threadName; - info.dwThreadID = dwThreadID; - info.dwFlags = 0; + THREADNAME_INFO info; + info.dwType = 0x1000; + info.szName = threadName; + info.dwThreadID = dwThreadID; + info.dwFlags = 0; - __try - { - RaiseException( MS_VC_EXCEPTION, 0, sizeof(info)/sizeof(ULONG_PTR), (ULONG_PTR*)&info ); - } - __except(EXCEPTION_EXECUTE_HANDLER) - { - } + __try + { + RaiseException( MS_VC_EXCEPTION, 0, sizeof(info)/sizeof(ULONG_PTR), (ULONG_PTR*)&info ); + } + __except(EXCEPTION_EXECUTE_HANDLER) + { + } #endif } @@ -144,15 +144,15 @@ static void SetThreadName(DWORD dwThreadID, char* threadName) static DWORD WINAPI thread_run( LPVOID lpThreadParameter ) { - rt_thread_t tid = rt_thread_self(); - win_thread_t *pWinThread = (win_thread_t *)lpThreadParameter; + rt_thread_t tid = rt_thread_self(); + win_thread_t *pWinThread = (win_thread_t *)lpThreadParameter; - SetThreadName(GetCurrentThreadId(), tid->name); + SetThreadName(GetCurrentThreadId(), tid->name); - pWinThread->Entry(pWinThread->Param); + pWinThread->Entry(pWinThread->Param); - pWinThread->Exit(); - return 0; + pWinThread->Exit(); + return 0; } rt_uint8_t* rt_hw_stack_init(void *pEntry,void *pParam,rt_uint8_t *pStackAddr,void *pExit) @@ -261,7 +261,7 @@ void rt_hw_context_switch_interrupt(rt_uint32_t from, rt_interrupt_to_thread = *((rt_uint32_t *)(to)); - //trigger YIELD exception(cause context switch) + //trigger YIELD exception(cause context switch) TriggerSimulateInterrupt(CPU_INTERRUPT_YIELD); } /*** rt_hw_context_switch_interrupt ***/ @@ -312,7 +312,7 @@ void rt_hw_context_switch(rt_uint32_t from, */ void rt_hw_context_switch_to(rt_uint32_t to) { - //set to thread + //set to thread rt_interrupt_to_thread = *((rt_uint32_t *)(to)); //clear from thread diff --git a/libcpu/ti-dsp/c28x/cpuport.c b/libcpu/ti-dsp/c28x/cpuport.c index 15041fc846..44876a5af5 100644 --- a/libcpu/ti-dsp/c28x/cpuport.c +++ b/libcpu/ti-dsp/c28x/cpuport.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2018, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * diff --git a/libcpu/unicore32/sep6200/context_gcc.S b/libcpu/unicore32/sep6200/context_gcc.S index 6b958e7f93..9f8e2b8f13 100644 --- a/libcpu/unicore32/sep6200/context_gcc.S +++ b/libcpu/unicore32/sep6200/context_gcc.S @@ -1,21 +1,7 @@ /* - * File : context_gcc.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/libcpu/unicore32/sep6200/cpu.c b/libcpu/unicore32/sep6200/cpu.c index 9452b4e59d..966277295d 100644 --- a/libcpu/unicore32/sep6200/cpu.c +++ b/libcpu/unicore32/sep6200/cpu.c @@ -1,21 +1,7 @@ /* - * File : cpu.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -34,23 +20,23 @@ #ifdef __GNUC__ rt_inline void cache_invalid(void) { - __asm__ volatile ("movc p0.c5, r1, #28\n" - "nop;nop;nop;nop;nop;nop;nop;nop;\n" - : - : - :"memory", "cc" - ); + __asm__ volatile ("movc p0.c5, r1, #28\n" + "nop;nop;nop;nop;nop;nop;nop;nop;\n" + : + : + :"memory", "cc" + ); } rt_inline void cache_enable(void) { - __asm__ volatile ( "movc r1, p0.c1, #0\n" - "or r1, r1, #0xc\n" - "movc p0.c1, r1, #0\n" - "nop;nop;nop;nop;nop;nop;nop;nop;\n" - : - : - :"r0", "memory", "cc"); + __asm__ volatile ( "movc r1, p0.c1, #0\n" + "or r1, r1, #0xc\n" + "movc p0.c1, r1, #0\n" + "nop;nop;nop;nop;nop;nop;nop;nop;\n" + : + : + :"r0", "memory", "cc"); } rt_inline void clean_dcache(void) @@ -59,8 +45,8 @@ rt_inline void clean_dcache(void) "movc p0.c5, ip, #10\n" "nop; nop; nop; nop; nop; nop; nop; nop\n" : - : - :"ip", "memory", "cc"); + : + :"ip", "memory", "cc"); } rt_inline rt_uint32_t icache_status(void) @@ -91,7 +77,7 @@ rt_inline rt_uint32_t dcache_status(void) rt_inline void dcache_flush(void) { - __asm__ volatile ( "mov ip, #0\n" + __asm__ volatile ( "mov ip, #0\n" "movc p0.c5, ip, #14\n" "nop; nop; nop; nop; nop; nop; nop; nop\n" : @@ -101,7 +87,7 @@ rt_inline void dcache_flush(void) rt_inline void icache_invalid(void) { - __asm__ volatile ( "mov r0, #0\n" + __asm__ volatile ( "mov r0, #0\n" "movc p0.c5, r0, #20\n" "nop; nop; nop; nop; nop; nop; nop; nop\n" : @@ -121,8 +107,8 @@ rt_inline void dcache_invalid(void) rt_inline void icache_disable(void) { - icache_invalid(); - __asm__ volatile ( "movc r0, p0.c1, #0\n" + icache_invalid(); + __asm__ volatile ( "movc r0, p0.c1, #0\n" "andn r0, r0, #8\n" "movc p0.c1, r0, #0\n" : @@ -132,8 +118,8 @@ rt_inline void icache_disable(void) rt_inline void dcache_disable(void) { - dcache_flush(); - __asm__ volatile ( "movc r0, p0.c1, #0\n" + dcache_flush(); + __asm__ volatile ( "movc r0, p0.c1, #0\n" "andn r0, r0, #20\n" "movc p0.c1, r0, #0\n" : @@ -184,7 +170,7 @@ rt_inline void dcache_enable(void) */ void rt_hw_cpu_icache_enable() { - icache_enable(); + icache_enable(); } /** @@ -193,7 +179,7 @@ void rt_hw_cpu_icache_enable() */ void rt_hw_cpu_icache_disable() { - icache_disable(); + icache_disable(); } /** @@ -202,7 +188,7 @@ void rt_hw_cpu_icache_disable() */ rt_base_t rt_hw_cpu_icache_status() { - return icache_status(); + return icache_status(); } /** @@ -211,7 +197,7 @@ rt_base_t rt_hw_cpu_icache_status() */ void rt_hw_cpu_dcache_enable() { - dcache_enable(); + dcache_enable(); } /** @@ -220,7 +206,7 @@ void rt_hw_cpu_dcache_enable() */ void rt_hw_cpu_dcache_disable() { - dcache_disable(); + dcache_disable(); } /** @@ -229,29 +215,29 @@ void rt_hw_cpu_dcache_disable() */ rt_base_t rt_hw_cpu_dcache_status() { - return dcache_status(); + return dcache_status(); } static void sep6200_reset(rt_uint32_t addr) { __asm__ volatile ( "mov ip, #0\n" - "movc p0.c5, ip, #28\n" /*Cache invalidate all*/ - "movc p0.c6, ip, #6\n" /*TLB invalidate all*/ - "nop;nop;nop;nop;nop;nop;nop;nop;\n" - "movc ip, p0.c1, #0\n" /*ctrl register*/ - "andn ip, ip, #0x000f\n" /*disable caches and mmu*/ - "movc p0.c1, ip, #0\n" - "nop\n" - "mov pc, %0\n" - "nop;nop;nop;nop;nop;nop;nop;nop;\n" - : "=&r" (addr) - : - :"memory", "cc"); + "movc p0.c5, ip, #28\n" /*Cache invalidate all*/ + "movc p0.c6, ip, #6\n" /*TLB invalidate all*/ + "nop;nop;nop;nop;nop;nop;nop;nop;\n" + "movc ip, p0.c1, #0\n" /*ctrl register*/ + "andn ip, ip, #0x000f\n" /*disable caches and mmu*/ + "movc p0.c1, ip, #0\n" + "nop\n" + "mov pc, %0\n" + "nop;nop;nop;nop;nop;nop;nop;nop;\n" + : "=&r" (addr) + : + :"memory", "cc"); } static void sep6200_poweroff(void) { - rt_kprintf("sep6200 power off not implemented\n"); + rt_kprintf("sep6200 power off not implemented\n"); while(1); } @@ -262,12 +248,12 @@ static void sep6200_poweroff(void) RT_WEAK void rt_hw_cpu_reset() { - rt_kprintf("Soft reset, Restarting system...\n"); - sep6200_reset(0); + rt_kprintf("Soft reset, Restarting system...\n"); + sep6200_reset(0); - while(1); /* loop forever and wait for reset to happen */ + while(1); /* loop forever and wait for reset to happen */ - /* NEVER REACHED */ + /* NEVER REACHED */ } /** @@ -276,15 +262,15 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_uint32_t level; - rt_kprintf("shutdown...\n"); + rt_uint32_t level; + rt_kprintf("shutdown...\n"); - level = rt_hw_interrupt_disable(); - sep6200_poweroff(); - while (level) - { - RT_ASSERT(0); - } + level = rt_hw_interrupt_disable(); + sep6200_poweroff(); + while (level) + { + RT_ASSERT(0); + } } /*@}*/ diff --git a/libcpu/unicore32/sep6200/interrupt.c b/libcpu/unicore32/sep6200/interrupt.c index 31078320ea..b34e648630 100644 --- a/libcpu/unicore32/sep6200/interrupt.c +++ b/libcpu/unicore32/sep6200/interrupt.c @@ -1,21 +1,7 @@ /* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -26,38 +12,38 @@ #include <rthw.h> #include <sep6200.h> -#define MAX_HANDLERS 64 +#define MAX_HANDLERS 64 #define SEP6200_IRQ_TYPE 0 #define SEP6200_FIQ_TYPE 1 -#define int_enable_all() \ - do { \ - *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = ~0x0;\ - *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = ~0x0;\ - }while(0) -#define int_disable_all() \ - do { \ - *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = 0x0;\ - *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = 0x0;\ - }while(0) -#define mask_all_int(int_type) \ - do { \ - if (int_type == SEP6200_IRQ_TYPE){ \ - *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x1;\ - } else if (int_type == SEP6200_FIQ_TYPE) {\ - *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x2;\ - }\ - }while(0) +#define int_enable_all() \ + do { \ + *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = ~0x0;\ + *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = ~0x0;\ + }while(0) +#define int_disable_all() \ + do { \ + *(volatile unsigned long*)SEP6200_VIC_INT_EN_L = 0x0;\ + *(volatile unsigned long*)SEP6200_VIC_INT_EN_H = 0x0;\ + }while(0) +#define mask_all_int(int_type) \ + do { \ + if (int_type == SEP6200_IRQ_TYPE){ \ + *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x1;\ + } else if (int_type == SEP6200_FIQ_TYPE) {\ + *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = 0x2;\ + }\ + }while(0) #define unmask_all_int(int_type)\ - do { \ - if (int_type == SEP6200_IRQ_TYPE){ \ - *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x1;\ - } else if (int_type == SEP6200_FIQ_TYPE) {\ - *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x2;\ - }\ - }while(0) + do { \ + if (int_type == SEP6200_IRQ_TYPE){ \ + *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x1;\ + } else if (int_type == SEP6200_FIQ_TYPE) {\ + *(volatile unsigned long*)SEP6200_VIC_INT_MSK_ALL = ~0x2;\ + }\ + }while(0) #define SEP6200_INT_SET(intnum) \ do{ \ @@ -113,27 +99,27 @@ void rt_hw_interrupt_umask(int irq); rt_inline void sep6200_irq_enable(rt_uint32_t irq) { - SEP6200_INT_ENABLE(irq); + SEP6200_INT_ENABLE(irq); } rt_inline void sep6200_irq_disable(rt_uint32_t irq) { - SEP6200_INT_DISABLE(irq); + SEP6200_INT_DISABLE(irq); } rt_inline void sep6200_irq_unmask(rt_uint32_t irq) { - SEP6200_INT_ENABLE(irq); + SEP6200_INT_ENABLE(irq); } rt_inline void sep6200_irq_mask(rt_uint32_t irq) { - SEP6200_INT_DISABLE(irq); + SEP6200_INT_DISABLE(irq); } rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); - return RT_NULL; + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + return RT_NULL; } /** @@ -141,26 +127,26 @@ rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector) */ void rt_hw_interrupt_init(void) { - rt_int32_t i; - register rt_uint32_t idx; + rt_int32_t i; + register rt_uint32_t idx; - /* init exceptions table */ - for(idx=0; idx < MAX_HANDLERS; idx++) - { - isr_table[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; - } - int_disable_all(); - mask_all_int(SEP6200_FIQ_TYPE); + /* init exceptions table */ + for(idx=0; idx < MAX_HANDLERS; idx++) + { + isr_table[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; + } + int_disable_all(); + mask_all_int(SEP6200_FIQ_TYPE); - //int_enable_all(); - unmask_all_int(SEP6200_IRQ_TYPE); + //int_enable_all(); + unmask_all_int(SEP6200_IRQ_TYPE); - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } @@ -171,11 +157,11 @@ void rt_hw_interrupt_init(void) */ void rt_hw_interrupt_mask(int irq) { - if (irq >= MAX_HANDLERS) { - rt_kprintf("Wrong irq num to mask\n"); - } else { - sep6200_irq_mask(irq); - } + if (irq >= MAX_HANDLERS) { + rt_kprintf("Wrong irq num to mask\n"); + } else { + sep6200_irq_mask(irq); + } } @@ -185,11 +171,11 @@ void rt_hw_interrupt_mask(int irq) */ void rt_hw_interrupt_umask(int irq) { - if (irq >= MAX_HANDLERS) { - rt_kprintf("Wrong irq num to unmask\n"); - } else { - sep6200_irq_unmask(irq); - } + if (irq >= MAX_HANDLERS) { + rt_kprintf("Wrong irq num to unmask\n"); + } else { + sep6200_irq_unmask(irq); + } } /** @@ -210,7 +196,7 @@ rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, if (handler != RT_NULL) { #ifdef RT_USING_INTERRUPT_INFO - rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); + rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX); #endif /* RT_USING_INTERRUPT_INFO */ isr_table[vector].handler = handler; isr_table[vector].param = param; diff --git a/libcpu/unicore32/sep6200/sep6200.h b/libcpu/unicore32/sep6200/sep6200.h index c09823740b..773b505a02 100644 --- a/libcpu/unicore32/sep6200/sep6200.h +++ b/libcpu/unicore32/sep6200/sep6200.h @@ -1,21 +1,7 @@ /* - * File : sep6200.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -29,58 +15,58 @@ /*Core definations*/ #define PRIVMODE 0x13 -#define Mode_USR 0x10 -#define Mode_REAL 0x11 -#define Mode_IRQ 0x12 -#define Mode_PRIV 0x13 -#define Mode_TRAP 0x17 -#define Mode_EXT 0x1B -#define Mode_SUSR 0x1F +#define Mode_USR 0x10 +#define Mode_REAL 0x11 +#define Mode_IRQ 0x12 +#define Mode_PRIV 0x13 +#define Mode_TRAP 0x17 +#define Mode_EXT 0x1B +#define Mode_SUSR 0x1F /* * Address */ -#define SEP6200_VIC_BASE 0xb0000000 -#define SEP6200_PMU_BASE 0xb0001000 -#define SEP6200_RTC_BASE 0xb0002000 -#define SEP6200_TIMER_BASE 0xb0003000 -#define SEP6200_PWM_BASE 0xb0004000 -#define SEP6200_GPIO_BASE 0xb0006000 -#define SEP6200_TOUCH_ADC 0xb0007000 -#define SEP6200_SYSCTL_BASE 0xb0008000 -#define SEP6200_UART0_BASE 0xb1000000 -#define SEP6200_UART1_BASE 0xb1001000 -#define SEP6200_UART2_BASE 0xb1002000 -#define SEP6200_UART3_BASE 0xb1003000 -#define SEP6200_SSI1_BASE 0xb1004000 -#define SEP6200_SSI2_BASE 0xb1005000 -#define SEP6200_SSI3_BASE 0xb1006000 -#define SEP6200_I2C_BASE 0xb1007000 -#define SEP6200_I2S_BASE 0xb1008000 +#define SEP6200_VIC_BASE 0xb0000000 +#define SEP6200_PMU_BASE 0xb0001000 +#define SEP6200_RTC_BASE 0xb0002000 +#define SEP6200_TIMER_BASE 0xb0003000 +#define SEP6200_PWM_BASE 0xb0004000 +#define SEP6200_GPIO_BASE 0xb0006000 +#define SEP6200_TOUCH_ADC 0xb0007000 +#define SEP6200_SYSCTL_BASE 0xb0008000 +#define SEP6200_UART0_BASE 0xb1000000 +#define SEP6200_UART1_BASE 0xb1001000 +#define SEP6200_UART2_BASE 0xb1002000 +#define SEP6200_UART3_BASE 0xb1003000 +#define SEP6200_SSI1_BASE 0xb1004000 +#define SEP6200_SSI2_BASE 0xb1005000 +#define SEP6200_SSI3_BASE 0xb1006000 +#define SEP6200_I2C_BASE 0xb1007000 +#define SEP6200_I2S_BASE 0xb1008000 #define SEP6200_USB_BASE 0xb1010000 #define SEP6200_DMAC2_BASE 0xb1011000 #define SEP6200_ESRAM_BASE 0xb2000000 -#define SEP6200_NORREG_BASE0xb2020000 -#define SEP6200_SDIO1_BASE 0xb2022000 -#define SEP6200_SDIO2_BASE 0xb2023000 -#define SEP6200_LCDC_BASE 0xb2025000 -#define SEP6200_VPU_BASE 0xb2026000 -#define SEP6200_DMAC1_BASE 0xb2027000 -#define SEP6200_DDR2_REG 0xb3000000 -#define SEP6200_DDR_MEM 0x40000000 +#define SEP6200_NORREG_BASE0xb2020000 +#define SEP6200_SDIO1_BASE 0xb2022000 +#define SEP6200_SDIO2_BASE 0xb2023000 +#define SEP6200_LCDC_BASE 0xb2025000 +#define SEP6200_VPU_BASE 0xb2026000 +#define SEP6200_DMAC1_BASE 0xb2027000 +#define SEP6200_DDR2_REG 0xb3000000 +#define SEP6200_DDR_MEM 0x40000000 -#define SEP6200_UART0_DLBL (SEP6200_UART0_BASE+0x00) -#define SEP6200_UART0_RXFIFO (SEP6200_UART0_BASE+0x00) -#define SEP6200_UART0_TXFIFO (SEP6200_UART0_BASE+0x00) -#define SEP6200_UART0_DLBH (SEP6200_UART0_BASE+0x04) -#define SEP6200_UART0_IER (SEP6200_UART0_BASE+0x04) -#define SEP6200_UART0_IIR (SEP6200_UART0_BASE+0x08) -#define SEP6200_UART0_FCR (SEP6200_UART0_BASE+0x08) -#define SEP6200_UART0_LCR (SEP6200_UART0_BASE+0x0c) -#define SEP6200_UART0_MCR (SEP6200_UART0_BASE+0x10) -#define SEP6200_UART0_LSR (SEP6200_UART0_BASE+0x14) -#define SEP6200_UART0_MSR (SEP6200_UART0_BASE+0x18) +#define SEP6200_UART0_DLBL (SEP6200_UART0_BASE+0x00) +#define SEP6200_UART0_RXFIFO (SEP6200_UART0_BASE+0x00) +#define SEP6200_UART0_TXFIFO (SEP6200_UART0_BASE+0x00) +#define SEP6200_UART0_DLBH (SEP6200_UART0_BASE+0x04) +#define SEP6200_UART0_IER (SEP6200_UART0_BASE+0x04) +#define SEP6200_UART0_IIR (SEP6200_UART0_BASE+0x08) +#define SEP6200_UART0_FCR (SEP6200_UART0_BASE+0x08) +#define SEP6200_UART0_LCR (SEP6200_UART0_BASE+0x0c) +#define SEP6200_UART0_MCR (SEP6200_UART0_BASE+0x10) +#define SEP6200_UART0_LSR (SEP6200_UART0_BASE+0x14) +#define SEP6200_UART0_MSR (SEP6200_UART0_BASE+0x18) #define SEP6200_TIMER_T1LCR (SEP6200_TIMER_BASE + 0X000) @@ -362,7 +348,7 @@ typedef void (*FP)(); /* program start address */ #ifndef _BOOL_TYPE_ #define _BOOL_TYPE_ -typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ +typedef int BOOL; /* Boolean value. TRUE (1) or FALSE (0). */ #endif typedef int ER; /* Error code. A signed integer. */ @@ -382,88 +368,88 @@ typedef int ER; /* Error code. A signed integer. */ /*Macros for debug*/ #define EOUT(fmt,...) \ - do \ - { \ - rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + do \ + { \ + rt_kprintf("EOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #define RT_DEBUG #ifdef RT_DEBUG - #define DBOUT(fmt,...) \ - do \ - { \ - rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ - rt_kprintf(fmt,##__VA_ARGS__); \ - }while(0) + #define DBOUT(fmt,...) \ + do \ + { \ + rt_kprintf("DBOUT:(%s:%i) ",__FILE__,__LINE__); \ + rt_kprintf(fmt,##__VA_ARGS__); \ + }while(0) #else - #define DBOUT(fmt,...) \ - do{}while(0) + #define DBOUT(fmt,...) \ + do{}while(0) #endif -#ifdef RT_DEBUG - #define ASSERT(arg) \ - if((arg) == 0) \ - { \ - while(1) \ - { \ - rt_kprintf("have a assert failure\n"); \ - } \ - } +#ifdef RT_DEBUG + #define ASSERT(arg) \ + if((arg) == 0) \ + { \ + while(1) \ + { \ + rt_kprintf("have a assert failure\n"); \ + } \ + } #else - #define ASSERT(arg) \ - do \ - { \ - }while(0) + #define ASSERT(arg) \ + do \ + { \ + }while(0) #endif #define write_reg(reg,value) \ - do \ - { \ - *(RP)(reg) = value; \ - }while(0) + do \ + { \ + *(RP)(reg) = value; \ + }while(0) #define read_reg(reg) (*(RP)reg) struct rt_hw_register { - rt_uint32_t r0; - rt_uint32_t r1; - rt_uint32_t r2; - rt_uint32_t r3; - rt_uint32_t r4; - rt_uint32_t r5; - rt_uint32_t r6; - rt_uint32_t r7; - rt_uint32_t r8; - rt_uint32_t r9; - rt_uint32_t r10; - rt_uint32_t r11; - rt_uint32_t r12; - rt_uint32_t r13; - rt_uint32_t r14; - rt_uint32_t r15; - rt_uint32_t r16; - rt_uint32_t r17; - rt_uint32_t r18; - rt_uint32_t r19; - rt_uint32_t r20; - rt_uint32_t r21; - rt_uint32_t r22; - rt_uint32_t r23; - rt_uint32_t r24; - rt_uint32_t sb; - rt_uint32_t sl; - rt_uint32_t fp; - rt_uint32_t ip; - rt_uint32_t sp; - rt_uint32_t lr; - rt_uint32_t pc; - rt_uint32_t asr; - rt_uint32_t bsr; - rt_uint32_t ORIG_r0; + rt_uint32_t r0; + rt_uint32_t r1; + rt_uint32_t r2; + rt_uint32_t r3; + rt_uint32_t r4; + rt_uint32_t r5; + rt_uint32_t r6; + rt_uint32_t r7; + rt_uint32_t r8; + rt_uint32_t r9; + rt_uint32_t r10; + rt_uint32_t r11; + rt_uint32_t r12; + rt_uint32_t r13; + rt_uint32_t r14; + rt_uint32_t r15; + rt_uint32_t r16; + rt_uint32_t r17; + rt_uint32_t r18; + rt_uint32_t r19; + rt_uint32_t r20; + rt_uint32_t r21; + rt_uint32_t r22; + rt_uint32_t r23; + rt_uint32_t r24; + rt_uint32_t sb; + rt_uint32_t sl; + rt_uint32_t fp; + rt_uint32_t ip; + rt_uint32_t sp; + rt_uint32_t lr; + rt_uint32_t pc; + rt_uint32_t asr; + rt_uint32_t bsr; + rt_uint32_t ORIG_r0; }; /*@}*/ diff --git a/libcpu/unicore32/sep6200/serial.c b/libcpu/unicore32/sep6200/serial.c index 518257b617..f91834b6a7 100644 --- a/libcpu/unicore32/sep6200/serial.c +++ b/libcpu/unicore32/sep6200/serial.c @@ -1,25 +1,11 @@ /* - * File : serial.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes - * 2013-03-16 Peng Fan Modified from sep4020 + * 2013-03-16 Peng Fan Modified from sep4020 */ #include <rtthread.h> #include <rthw.h> @@ -36,204 +22,204 @@ */ static rt_err_t rt_serial_init (rt_device_t dev) { - struct serial_device* uart = (struct serial_device*) dev->user_data; + struct serial_device* uart = (struct serial_device*) dev->user_data; - if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) - { + if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED)) + { - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_memset(uart->int_rx->rx_buffer, 0, - sizeof(uart->int_rx->rx_buffer)); - uart->int_rx->read_index = uart->int_rx->save_index = 0; - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_memset(uart->int_rx->rx_buffer, 0, + sizeof(uart->int_rx->rx_buffer)); + uart->int_rx->read_index = uart->int_rx->save_index = 0; + } - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - rt_memset(uart->int_tx->tx_buffer, 0, - sizeof(uart->int_tx->tx_buffer)); - uart->int_tx->write_index = uart->int_tx->save_index = 0; - } + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + rt_memset(uart->int_tx->tx_buffer, 0, + sizeof(uart->int_tx->tx_buffer)); + uart->int_tx->write_index = uart->int_tx->save_index = 0; + } - dev->flag |= RT_DEVICE_FLAG_ACTIVATED; - } + dev->flag |= RT_DEVICE_FLAG_ACTIVATED; + } - return RT_EOK; + return RT_EOK; } /* save a char to serial buffer */ static void rt_serial_savechar(struct serial_device* uart, char ch) { - rt_base_t level; + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; - uart->int_rx->save_index ++; - if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->save_index = 0; + uart->int_rx->rx_buffer[uart->int_rx->save_index] = ch; + uart->int_rx->save_index ++; + if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (uart->int_rx->save_index == uart->int_rx->read_index) - { - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; - } + /* if the next position is read index, discard this 'read char' */ + if (uart->int_rx->save_index == uart->int_rx->read_index) + { + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - RT_ASSERT(dev != RT_NULL); - return RT_EOK; + RT_ASSERT(dev != RT_NULL); + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; - ptr = buffer; - err_code = RT_EOK; - uart = (struct serial_device*)dev->user_data; + ptr = buffer; + err_code = RT_EOK; + uart = (struct serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + rt_base_t level; - /* interrupt mode Rx */ - while (size) - { - if (uart->int_rx->read_index != uart->int_rx->save_index) - { - *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; - size --; + /* interrupt mode Rx */ + while (size) + { + if (uart->int_rx->read_index != uart->int_rx->save_index) + { + *ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index]; + size --; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - uart->int_rx->read_index ++; - if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) - uart->int_rx->read_index = 0; + uart->int_rx->read_index ++; + if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE) + uart->int_rx->read_index = 0; - /* enable interrupt */ - rt_hw_interrupt_enable(level); - } - else - { - /* set error code */ - err_code = -RT_EEMPTY; - break; - } - } - } - else - { - /* polling mode */ - while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) - { - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; - ptr ++; - } - } - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + } + else + { + /* set error code */ + err_code = -RT_EEMPTY; + break; + } + } + } + else + { + /* polling mode */ + while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size) + { + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + *ptr = uart->uart_device->dlbl_fifo.txfifo & 0xff; + ptr ++; + } + } + } - /* set error code */ - rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + /* set error code */ + rt_set_errno(err_code); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - rt_err_t err_code; - struct serial_device* uart; + rt_uint8_t* ptr; + rt_err_t err_code; + struct serial_device* uart; - err_code = RT_EOK; - ptr = (rt_uint8_t*)buffer; - uart = (struct serial_device*)dev->user_data; + err_code = RT_EOK; + ptr = (rt_uint8_t*)buffer; + uart = (struct serial_device*)dev->user_data; - if (dev->flag & RT_DEVICE_FLAG_INT_TX) - { - /* interrupt mode Tx */ - while (uart->int_tx->save_index != uart->int_tx->write_index) - { - /* save on tx buffer */ - uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; + if (dev->flag & RT_DEVICE_FLAG_INT_TX) + { + /* interrupt mode Tx */ + while (uart->int_tx->save_index != uart->int_tx->write_index) + { + /* save on tx buffer */ + uart->int_tx->tx_buffer[uart->int_tx->save_index] = *ptr++; - -- size; + -- size; - /* move to next position */ - uart->int_tx->save_index ++; + /* move to next position */ + uart->int_tx->save_index ++; - /* wrap save index */ - if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) - uart->int_tx->save_index = 0; - } + /* wrap save index */ + if (uart->int_tx->save_index >= UART_TX_BUFFER_SIZE) + uart->int_tx->save_index = 0; + } - /* set error code */ - if (size > 0) - err_code = -RT_EFULL; - } - else - { - /* polling mode */ - while (size) - { - /* - * to be polite with serial console add a line feed - * to the carriage return character - */ - if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) - { - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = '\r'; - } + /* set error code */ + if (size > 0) + err_code = -RT_EFULL; + } + else + { + /* polling mode */ + while (size) + { + /* + * to be polite with serial console add a line feed + * to the carriage return character + */ + if (*ptr == '\n' && (dev->flag & RT_DEVICE_FLAG_STREAM)) + { + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = '\r'; + } - while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); - uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); + while (!(uart->uart_device->lsr & USTAT_TXB_EMPTY)); + uart->uart_device->dlbl_fifo.txfifo = (*ptr & 0x1FF); - ++ptr; --size; - } - } + ++ptr; --size; + } + } - /* set error code */ - rt_set_errno(err_code); + /* set error code */ + rt_set_errno(err_code); - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - RT_ASSERT(dev != RT_NULL); + RT_ASSERT(dev != RT_NULL); - switch (cmd) - { - case RT_DEVICE_CTRL_SUSPEND: - /* suspend device */ - dev->flag |= RT_DEVICE_FLAG_SUSPENDED; - break; + switch (cmd) + { + case RT_DEVICE_CTRL_SUSPEND: + /* suspend device */ + dev->flag |= RT_DEVICE_FLAG_SUSPENDED; + break; - case RT_DEVICE_CTRL_RESUME: - /* resume device */ - dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; - break; - } + case RT_DEVICE_CTRL_RESUME: + /* resume device */ + dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED; + break; + } - return RT_EOK; + return RT_EOK; } /* @@ -241,49 +227,49 @@ static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) */ rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial) { - RT_ASSERT(device != RT_NULL); + RT_ASSERT(device != RT_NULL); - device->type = RT_Device_Class_Char; - device->rx_indicate = RT_NULL; - device->tx_complete = RT_NULL; - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; - device->user_data = serial; + device->type = RT_Device_Class_Char; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; + device->user_data = serial; - /* register a character device */ - return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); + /* register a character device */ + return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag); } /* ISR for serial interrupt */ void rt_hw_serial_isr(rt_device_t device) { - struct serial_device* uart = (struct serial_device*) device->user_data; + struct serial_device* uart = (struct serial_device*) device->user_data; - /* interrupt mode receive */ - RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); + /* interrupt mode receive */ + RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX); - /* save on rx buffer */ - while (uart->uart_device->lsr & USTAT_RCV_READY) - { - rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); - } + /* save on rx buffer */ + while (uart->uart_device->lsr & USTAT_RCV_READY) + { + rt_serial_savechar(uart, uart->uart_device->dlbl_fifo.rxfifo & 0xff); + } - /* invoke callback */ - if (device->rx_indicate != RT_NULL) - { - rt_size_t rx_length; + /* invoke callback */ + if (device->rx_indicate != RT_NULL) + { + rt_size_t rx_length; - /* get rx length */ - rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? - UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : - uart->int_rx->save_index - uart->int_rx->read_index; + /* get rx length */ + rx_length = uart->int_rx->read_index > uart->int_rx->save_index ? + UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index : + uart->int_rx->save_index - uart->int_rx->read_index; - device->rx_indicate(device, rx_length); - } + device->rx_indicate(device, rx_length); + } } /*@}*/ diff --git a/libcpu/unicore32/sep6200/serial.h b/libcpu/unicore32/sep6200/serial.h index e626f5e20f..dcfdc517d4 100644 --- a/libcpu/unicore32/sep6200/serial.h +++ b/libcpu/unicore32/sep6200/serial.h @@ -1,21 +1,7 @@ /* - * File : serial.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -30,73 +16,73 @@ #include <sep6200.h> -#define USTAT_RCV_READY 0x01 /* receive data ready */ -#define USTAT_OVERRUN 0x02 /* overrun */ -#define USTAT_PARITY_ERR 0x04 /* parity error */ -#define USTAT_FRAME_ERROR 0x08 /* frame error */ -#define USTAT_BREAK 0x10 /* break */ -#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ -#define USTAT_RCV_ERR 0x80 /* receive error */ +#define USTAT_RCV_READY 0x01 /* receive data ready */ +#define USTAT_OVERRUN 0x02 /* overrun */ +#define USTAT_PARITY_ERR 0x04 /* parity error */ +#define USTAT_FRAME_ERROR 0x08 /* frame error */ +#define USTAT_BREAK 0x10 /* break */ +#define USTAT_TXB_EMPTY 0x40 /* tx buffer empty */ +#define USTAT_RCV_ERR 0x80 /* receive error */ -#define BPS 115200 /* serial baudrate */ +#define BPS 115200 /* serial baudrate */ -#define UART_RX_BUFFER_SIZE 64 -#define UART_TX_BUFFER_SIZE 64 +#define UART_RX_BUFFER_SIZE 64 +#define UART_TX_BUFFER_SIZE 64 /*For sep6200's uart have several secondary function*/ /*we use union to decribe it*/ union dlbl_fifo { - rt_uint32_t dlbl; - rt_uint32_t rxfifo; - rt_uint32_t txfifo; + rt_uint32_t dlbl; + rt_uint32_t rxfifo; + rt_uint32_t txfifo; }; union dlbh_ier { - rt_uint32_t dlbh; - rt_uint32_t ier; + rt_uint32_t dlbh; + rt_uint32_t ier; }; union iir_fcr { - rt_uint32_t iir; - rt_uint32_t fcr; + rt_uint32_t iir; + rt_uint32_t fcr; }; struct serial_int_rx { - rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; - rt_uint32_t read_index, save_index; + rt_uint8_t rx_buffer[UART_RX_BUFFER_SIZE]; + rt_uint32_t read_index, save_index; }; struct serial_int_tx { - rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; - rt_uint32_t write_index, save_index; + rt_uint8_t tx_buffer[UART_TX_BUFFER_SIZE]; + rt_uint32_t write_index, save_index; }; typedef struct uartport { - union dlbl_fifo dlbl_fifo; - union dlbh_ier dlbh_ier; - union iir_fcr iir_fcr; - rt_uint32_t lcr; - rt_uint32_t mcr; - rt_uint32_t lsr; - rt_uint32_t msr; + union dlbl_fifo dlbl_fifo; + union dlbh_ier dlbh_ier; + union iir_fcr iir_fcr; + rt_uint32_t lcr; + rt_uint32_t mcr; + rt_uint32_t lsr; + rt_uint32_t msr; }uartport; struct serial_device { - uartport* uart_device; + uartport* uart_device; - /* rx structure */ - struct serial_int_rx* int_rx; + /* rx structure */ + struct serial_int_rx* int_rx; - /* tx structure */ - struct serial_int_tx* int_tx; + /* tx structure */ + struct serial_int_tx* int_tx; }; rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct serial_device *serial); diff --git a/libcpu/unicore32/sep6200/stack.c b/libcpu/unicore32/sep6200/stack.c index 722f40835e..049b075f6c 100644 --- a/libcpu/unicore32/sep6200/stack.c +++ b/libcpu/unicore32/sep6200/stack.c @@ -1,21 +1,7 @@ /* - * File : stack.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -42,47 +28,47 @@ */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - rt_uint32_t *stk; + rt_uint32_t *stk; - stk = (rt_uint32_t*)stack_addr; - *(stk) = (rt_uint32_t)tentry; /* entry point */ - *(--stk) = (rt_uint32_t)texit; /* lr */ - *(--stk) = 0; /* r28 */ - *(--stk) = 0; /* r27 */ - *(--stk) = 0; /* r26 */ - *(--stk) = 0; /* r25 */ - *(--stk) = 0; /* r24 */ - *(--stk) = 0; /* r23 */ - *(--stk) = 0; /* r22 */ - *(--stk) = 0; /* r21 */ - *(--stk) = 0; /* r20 */ - *(--stk) = 0; /* r19 */ - *(--stk) = 0; /* r18 */ - *(--stk) = 0; /* r17 */ - *(--stk) = 0; /* r16 */ - *(--stk) = 0; /* r15 */ - *(--stk) = 0; /* r14 */ - *(--stk) = 0; /* r13 */ - *(--stk) = 0; /* r12 */ - *(--stk) = 0; /* r11 */ - *(--stk) = 0; /* r10 */ - *(--stk) = 0; /* r9 */ - *(--stk) = 0; /* r8 */ - *(--stk) = 0; /* r7 */ - *(--stk) = 0; /* r6 */ - *(--stk) = 0; /* r5 */ - *(--stk) = 0; /* r4 */ - *(--stk) = 0; /* r3 */ - *(--stk) = 0; /* r2 */ - *(--stk) = 0; /* r1 */ - *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ - *(--stk) = Mode_PRIV; /* asr */ - *(--stk) = Mode_PRIV; /* bsr */ /*why both PRIV do not need switch?*/ + stk = (rt_uint32_t*)stack_addr; + *(stk) = (rt_uint32_t)tentry; /* entry point */ + *(--stk) = (rt_uint32_t)texit; /* lr */ + *(--stk) = 0; /* r28 */ + *(--stk) = 0; /* r27 */ + *(--stk) = 0; /* r26 */ + *(--stk) = 0; /* r25 */ + *(--stk) = 0; /* r24 */ + *(--stk) = 0; /* r23 */ + *(--stk) = 0; /* r22 */ + *(--stk) = 0; /* r21 */ + *(--stk) = 0; /* r20 */ + *(--stk) = 0; /* r19 */ + *(--stk) = 0; /* r18 */ + *(--stk) = 0; /* r17 */ + *(--stk) = 0; /* r16 */ + *(--stk) = 0; /* r15 */ + *(--stk) = 0; /* r14 */ + *(--stk) = 0; /* r13 */ + *(--stk) = 0; /* r12 */ + *(--stk) = 0; /* r11 */ + *(--stk) = 0; /* r10 */ + *(--stk) = 0; /* r9 */ + *(--stk) = 0; /* r8 */ + *(--stk) = 0; /* r7 */ + *(--stk) = 0; /* r6 */ + *(--stk) = 0; /* r5 */ + *(--stk) = 0; /* r4 */ + *(--stk) = 0; /* r3 */ + *(--stk) = 0; /* r2 */ + *(--stk) = 0; /* r1 */ + *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ + *(--stk) = Mode_PRIV; /* asr */ + *(--stk) = Mode_PRIV; /* bsr */ /*why both PRIV do not need switch?*/ - /* return task's current stack address */ - return (rt_uint8_t *)stk; + /* return task's current stack address */ + return (rt_uint8_t *)stk; } /*@}*/ diff --git a/libcpu/unicore32/sep6200/start_gcc.S b/libcpu/unicore32/sep6200/start_gcc.S index 4dd17aa387..11676e875c 100644 --- a/libcpu/unicore32/sep6200/start_gcc.S +++ b/libcpu/unicore32/sep6200/start_gcc.S @@ -1,21 +1,7 @@ /* - * File : start.S - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/libcpu/unicore32/sep6200/trace.c b/libcpu/unicore32/sep6200/trace.c index 8f11a18a17..d83447c291 100644 --- a/libcpu/unicore32/sep6200/trace.c +++ b/libcpu/unicore32/sep6200/trace.c @@ -1,21 +1,7 @@ /* - * File : trace.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes diff --git a/libcpu/unicore32/sep6200/trap.c b/libcpu/unicore32/sep6200/trap.c index 1e5d02a279..f2f342cfbe 100644 --- a/libcpu/unicore32/sep6200/trap.c +++ b/libcpu/unicore32/sep6200/trap.c @@ -1,21 +1,7 @@ /* - * File : trap.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2013, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes @@ -42,16 +28,16 @@ extern struct rt_thread *rt_current_thread; void rt_hw_show_register (struct rt_hw_register *regs) { - rt_kprintf("Execption:\n"); - rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); - rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); - rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x r11:0x%08x\n", regs->r8, regs->r9, regs->r10,regs->r11); - rt_kprintf("r12:0x%08x r13:0x%08x r14:0x%08x r15:0x%08x\n", regs->r12,regs->r13,regs->r14,regs->r15); - rt_kprintf("r16:0x%08x r17:0x%08x r18:0x%08x r19:0x%08x\n", regs->r16,regs->r17,regs->r18,regs->r19); - rt_kprintf("r20:0x%08x r21:0x%08x r22:0x%08x r23:0x%08x\n", regs->r20,regs->r21,regs->r22,regs->r23); - rt_kprintf("r24:0x%08x sb:0x%08x sl:0x%08xfp :0x%08x ip :0x%08x\n",regs->r24,regs->sb,regs->sl,regs->fp,regs->ip); - rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); - rt_kprintf("asr:0x%08x bsr:0x%08x\n", regs->asr,regs->bsr); + rt_kprintf("Execption:\n"); + rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3); + rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7); + rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x r11:0x%08x\n", regs->r8, regs->r9, regs->r10,regs->r11); + rt_kprintf("r12:0x%08x r13:0x%08x r14:0x%08x r15:0x%08x\n", regs->r12,regs->r13,regs->r14,regs->r15); + rt_kprintf("r16:0x%08x r17:0x%08x r18:0x%08x r19:0x%08x\n", regs->r16,regs->r17,regs->r18,regs->r19); + rt_kprintf("r20:0x%08x r21:0x%08x r22:0x%08x r23:0x%08x\n", regs->r20,regs->r21,regs->r22,regs->r23); + rt_kprintf("r24:0x%08x sb:0x%08x sl:0x%08xfp :0x%08x ip :0x%08x\n",regs->r24,regs->sb,regs->sl,regs->fp,regs->ip); + rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc); + rt_kprintf("asr:0x%08x bsr:0x%08x\n", regs->asr,regs->bsr); } /** @@ -64,13 +50,13 @@ void rt_hw_show_register (struct rt_hw_register *regs) */ void rt_hw_trap_extn(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("extn instruction\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("extn instruction\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -84,10 +70,10 @@ void rt_hw_trap_extn(struct rt_hw_register *regs) */ void rt_hw_trap_swi(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("software interrupt\n"); - rt_hw_cpu_shutdown(); + rt_kprintf("software interrupt\n"); + rt_hw_cpu_shutdown(); } /** @@ -100,13 +86,13 @@ void rt_hw_trap_swi(struct rt_hw_register *regs) */ void rt_hw_trap_pabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("prefetch abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("prefetch abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -119,13 +105,13 @@ void rt_hw_trap_pabt(struct rt_hw_register *regs) */ void rt_hw_trap_dabt(struct rt_hw_register *regs) { - rt_hw_show_register(regs); + rt_hw_show_register(regs); - rt_kprintf("data abort\n"); - rt_kprintf("thread - %s stack:\n", rt_current_thread->name); - rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); + rt_kprintf("data abort\n"); + rt_kprintf("thread - %s stack:\n", rt_current_thread->name); + rt_hw_backtrace((rt_uint32_t *)regs->fp, (rt_uint32_t)rt_current_thread->entry); - rt_hw_cpu_shutdown(); + rt_hw_cpu_shutdown(); } /** @@ -137,9 +123,9 @@ void rt_hw_trap_dabt(struct rt_hw_register *regs) */ void rt_hw_trap_resv(struct rt_hw_register *regs) { - rt_kprintf("not used\n"); - rt_hw_show_register(regs); - rt_hw_cpu_shutdown(); + rt_kprintf("not used\n"); + rt_hw_show_register(regs); + rt_hw_cpu_shutdown(); } extern struct rt_irq_desc isr_table[]; @@ -152,7 +138,7 @@ void rt_hw_trap_irq(void) void *param; /* get the interrupt number */ - irq = *(RP)(SEP6200_VIC_IRQ_VECTOR_NUM); + irq = *(RP)(SEP6200_VIC_IRQ_VECTOR_NUM); /* get interrupt service routine */ isr_func = isr_table[irq].handler; @@ -162,13 +148,13 @@ void rt_hw_trap_irq(void) isr_func(irq, param); #ifdef RT_USING_INTERRUPT_INFO - isr_table[irq].counter++; + isr_table[irq].counter++; #endif /* RT_USING_INTERRUPT_INFO */ } void rt_hw_trap_fiq() { - rt_kprintf("fast interrupt request\n"); + rt_kprintf("fast interrupt request\n"); } /*@}*/ diff --git a/libcpu/xilinx/microblaze/cpu.c b/libcpu/xilinx/microblaze/cpu.c index d37dcda350..37da5fd7c5 100755 --- a/libcpu/xilinx/microblaze/cpu.c +++ b/libcpu/xilinx/microblaze/cpu.c @@ -28,8 +28,8 @@ RT_WEAK void rt_hw_cpu_reset() */ RT_WEAK void rt_hw_cpu_shutdown() { - rt_kprintf("shutdown...\n"); + rt_kprintf("shutdown...\n"); - while (1); + while (1); } diff --git a/libcpu/xilinx/microblaze/serial.c b/libcpu/xilinx/microblaze/serial.c index 17cca9f84d..1902f11710 100755 --- a/libcpu/xilinx/microblaze/serial.c +++ b/libcpu/xilinx/microblaze/serial.c @@ -12,7 +12,7 @@ * 2006-08-23 Bernard first version * 2009-05-14 Bernard add RT-THread device interface * - * 2011-12-17 nl1031 MicroBlaze + * 2011-12-17 nl1031 MicroBlaze */ #include <rthw.h> @@ -22,23 +22,23 @@ typedef volatile rt_uint32_t REG32; struct rt_mb_uart_lite_hw { - REG32 Rx_FIFO; // Receiver Holding Register - REG32 Tx_FIFO; // Transmitter Holding Register - REG32 STAT_REG; // Channel Status Register - REG32 CTRL_REG; // Control Register + REG32 Rx_FIFO; // Receiver Holding Register + REG32 Tx_FIFO; // Transmitter Holding Register + REG32 STAT_REG; // Channel Status Register + REG32 CTRL_REG; // Control Register }; struct rt_mb_uart_lite { - struct rt_device parent; + struct rt_device parent; - struct rt_mb_uart_lite_hw* hw_base; - rt_uint16_t peripheral_id; - rt_uint32_t baudrate; + struct rt_mb_uart_lite_hw* hw_base; + rt_uint16_t peripheral_id; + rt_uint32_t baudrate; - /* reception field */ - rt_uint16_t save_index, read_index; - rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; + /* reception field */ + rt_uint16_t save_index, read_index; + rt_uint8_t rx_buffer[RT_UART_RX_BUFFER_SIZE]; }; #ifdef RT_USING_UART1 struct rt_mb_uart_lite serial1; @@ -46,271 +46,271 @@ struct rt_mb_uart_lite serial1; static void rt_hw_serial_isr(void) { - unsigned int status; - rt_base_t level; - struct rt_device* device; - struct rt_mb_uart_lite* serial = RT_NULL; + unsigned int status; + rt_base_t level; + struct rt_device* device; + struct rt_mb_uart_lite* serial = RT_NULL; #ifdef RT_USING_UART1 - /* serial 1 */ - serial = &serial1; + /* serial 1 */ + serial = &serial1; #endif - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - /* get generic device object */ - device = (rt_device_t)serial; + /* get generic device object */ + device = (rt_device_t)serial; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); + /* disable interrupt */ + level = rt_hw_interrupt_disable(); - /* get uart status register */ - status = serial->hw_base->STAT_REG; - while (status & XUL_SR_RX_FIFO_VALID_DATA) - { - /* get received character */ - serial->rx_buffer[serial->save_index] = serial->hw_base->Rx_FIFO; + /* get uart status register */ + status = serial->hw_base->STAT_REG; + while (status & XUL_SR_RX_FIFO_VALID_DATA) + { + /* get received character */ + serial->rx_buffer[serial->save_index] = serial->hw_base->Rx_FIFO; - /* move to next position */ - serial->save_index ++; - if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) - serial->save_index = 0; + /* move to next position */ + serial->save_index ++; + if (serial->save_index >= RT_UART_RX_BUFFER_SIZE) + serial->save_index = 0; - /* if the next position is read index, discard this 'read char' */ - if (serial->save_index == serial->read_index) - { - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - status = serial->hw_base->STAT_REG; - } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* if the next position is read index, discard this 'read char' */ + if (serial->save_index == serial->read_index) + { + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + status = serial->hw_base->STAT_REG; + } + /* enable interrupt */ + rt_hw_interrupt_enable(level); - /* indicate to upper layer application */ - if (device->rx_indicate != RT_NULL) - device->rx_indicate(device, 1); + /* indicate to upper layer application */ + if (device->rx_indicate != RT_NULL) + device->rx_indicate(device, 1); } static rt_err_t rt_serial_init (rt_device_t dev) { - struct rt_mb_uart_lite* serial = (struct rt_mb_uart_lite*) dev; + struct rt_mb_uart_lite* serial = (struct rt_mb_uart_lite*) dev; - RT_ASSERT(serial != RT_NULL); + RT_ASSERT(serial != RT_NULL); - RT_ASSERT(serial->peripheral_id != XPAR_UARTLITE_1_DEVICE_ID); + RT_ASSERT(serial->peripheral_id != XPAR_UARTLITE_1_DEVICE_ID); - /* reset rx index */ - serial->save_index = 0; - serial->read_index = 0; + /* reset rx index */ + serial->save_index = 0; + serial->read_index = 0; - /* reset rx buffer */ - rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); + /* reset rx buffer */ + rt_memset(serial->rx_buffer, 0, RT_UART_RX_BUFFER_SIZE); - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag) { - struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* enable UART rx interrupt */ - serial->hw_base->CTRL_REG = XUL_CR_ENABLE_INTR; /* enable interrupt */ + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* enable UART rx interrupt */ + serial->hw_base->CTRL_REG = XUL_CR_ENABLE_INTR; /* enable interrupt */ - /* install UART handler */ - rt_hw_interrupt_install(serial->peripheral_id, (rt_isr_handler_t)rt_hw_serial_isr, RT_NULL); - rt_hw_interrupt_umask(serial->peripheral_id); - } + /* install UART handler */ + rt_hw_interrupt_install(serial->peripheral_id, (rt_isr_handler_t)rt_hw_serial_isr, RT_NULL); + rt_hw_interrupt_umask(serial->peripheral_id); + } - return RT_EOK; + return RT_EOK; } static rt_err_t rt_serial_close(rt_device_t dev) { - struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; - RT_ASSERT(serial != RT_NULL); + struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; + RT_ASSERT(serial != RT_NULL); - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - /* disable interrupt */ - serial->hw_base->CTRL_REG = 0; /* RxReady interrupt */ - } + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + /* disable interrupt */ + serial->hw_base->CTRL_REG = 0; /* RxReady interrupt */ + } - return RT_EOK; + return RT_EOK; } static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; - RT_ASSERT(serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; + RT_ASSERT(serial != RT_NULL); - /* point to buffer */ - ptr = (rt_uint8_t*) buffer; + /* point to buffer */ + ptr = (rt_uint8_t*) buffer; - if (dev->flag & RT_DEVICE_FLAG_INT_RX) - { - while (size) - { - /* interrupt receive */ - rt_base_t level; + if (dev->flag & RT_DEVICE_FLAG_INT_RX) + { + while (size) + { + /* interrupt receive */ + rt_base_t level; - /* disable interrupt */ - level = rt_hw_interrupt_disable(); - if (serial->read_index != serial->save_index) - { - *ptr = serial->rx_buffer[serial->read_index]; + /* disable interrupt */ + level = rt_hw_interrupt_disable(); + if (serial->read_index != serial->save_index) + { + *ptr = serial->rx_buffer[serial->read_index]; - serial->read_index ++; - if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) - serial->read_index = 0; - } - else - { - /* no data in rx buffer */ + serial->read_index ++; + if (serial->read_index >= RT_UART_RX_BUFFER_SIZE) + serial->read_index = 0; + } + else + { + /* no data in rx buffer */ - /* enable interrupt */ - rt_hw_interrupt_enable(level); - break; - } + /* enable interrupt */ + rt_hw_interrupt_enable(level); + break; + } - /* enable interrupt */ - rt_hw_interrupt_enable(level); + /* enable interrupt */ + rt_hw_interrupt_enable(level); - ptr ++; size --; - } + ptr ++; size --; + } - return (rt_uint32_t)ptr - (rt_uint32_t)buffer; - } - else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) - { - /* not support right now */ - RT_ASSERT(0); - } - else - { - /* poll mode */ - while (size) - { - /* Wait for Full Rx Buffer */ - while (!(serial->hw_base->STAT_REG & XUL_SR_RX_FIFO_VALID_DATA)); + return (rt_uint32_t)ptr - (rt_uint32_t)buffer; + } + else if (dev->flag & RT_DEVICE_FLAG_DMA_RX) + { + /* not support right now */ + RT_ASSERT(0); + } + else + { + /* poll mode */ + while (size) + { + /* Wait for Full Rx Buffer */ + while (!(serial->hw_base->STAT_REG & XUL_SR_RX_FIFO_VALID_DATA)); - /* Read Character */ - *ptr = serial->hw_base->Rx_FIFO; - ptr ++; - size --; - } + /* Read Character */ + *ptr = serial->hw_base->Rx_FIFO; + ptr ++; + size --; + } - return (rt_size_t)ptr - (rt_size_t)buffer; - } + return (rt_size_t)ptr - (rt_size_t)buffer; + } - return 0; + return 0; } static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) { - rt_uint8_t* ptr; - struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; - RT_ASSERT(serial != RT_NULL); + rt_uint8_t* ptr; + struct rt_mb_uart_lite *serial = (struct rt_mb_uart_lite*)dev; + RT_ASSERT(serial != RT_NULL); - ptr = (rt_uint8_t*) buffer; - if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) - { - if (dev->flag & RT_DEVICE_FLAG_STREAM) - { - /* it's a stream mode device */ - while (size) - { - /* stream mode */ - if (*ptr == '\n') - { - while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); - serial->hw_base->Tx_FIFO = '\r'; - } + ptr = (rt_uint8_t*) buffer; + if (dev->open_flag & RT_DEVICE_OFLAG_WRONLY) + { + if (dev->flag & RT_DEVICE_FLAG_STREAM) + { + /* it's a stream mode device */ + while (size) + { + /* stream mode */ + if (*ptr == '\n') + { + while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); + serial->hw_base->Tx_FIFO = '\r'; + } - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); - /* Transmit Character */ - serial->hw_base->Tx_FIFO = *ptr; - if (*ptr & 1) - rt_hw_board_led_on(2); - else - rt_hw_board_led_off(2); - ptr ++; size --; - } - } - else - { - while (size) - { - /* Wait for Empty Tx Buffer */ - while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); + /* Transmit Character */ + serial->hw_base->Tx_FIFO = *ptr; + if (*ptr & 1) + rt_hw_board_led_on(2); + else + rt_hw_board_led_off(2); + ptr ++; size --; + } + } + else + { + while (size) + { + /* Wait for Empty Tx Buffer */ + while (!(serial->hw_base->STAT_REG & XUL_SR_TX_FIFO_EMPTY)); - /* Transmit Character */ - serial->hw_base->Tx_FIFO = *ptr; - if (*ptr & 1) - rt_hw_board_led_on(2); - else - rt_hw_board_led_off(2); - ptr ++; size --; - } - } - } + /* Transmit Character */ + serial->hw_base->Tx_FIFO = *ptr; + if (*ptr & 1) + rt_hw_board_led_on(2); + else + rt_hw_board_led_off(2); + ptr ++; size --; + } + } + } - return (rt_size_t)ptr - (rt_size_t)buffer; + return (rt_size_t)ptr - (rt_size_t)buffer; } static rt_err_t rt_serial_control (rt_device_t dev, int cmd, void *args) { - return RT_EOK; + return RT_EOK; } rt_err_t rt_hw_serial_init() { - rt_device_t device; + rt_device_t device; #ifndef RT_USING_CONSOLE - int Status; + int Status; - /* - * Initialize the UartLite driver so that it is ready to use. - */ - Status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID); - if (Status != XST_SUCCESS) - { - return; - } + /* + * Initialize the UartLite driver so that it is ready to use. + */ + Status = XUartLite_Initialize(&uart_lite, RS232_DEVICE_ID); + if (Status != XST_SUCCESS) + { + return; + } #endif #ifdef RT_USING_UART1 - device = (rt_device_t) &serial1; + device = (rt_device_t) &serial1; - /* init serial device private data */ - serial1.hw_base = (struct rt_mb_uart_lite_hw*)XPAR_USB_UART_BASEADDR; - serial1.peripheral_id = XPAR_UARTLITE_1_DEVICE_ID; - serial1.baudrate = 115200; + /* init serial device private data */ + serial1.hw_base = (struct rt_mb_uart_lite_hw*)XPAR_USB_UART_BASEADDR; + serial1.peripheral_id = XPAR_UARTLITE_1_DEVICE_ID; + serial1.baudrate = 115200; - /* set device virtual interface */ - device->init = rt_serial_init; - device->open = rt_serial_open; - device->close = rt_serial_close; - device->read = rt_serial_read; - device->write = rt_serial_write; - device->control = rt_serial_control; + /* set device virtual interface */ + device->init = rt_serial_init; + device->open = rt_serial_open; + device->close = rt_serial_close; + device->read = rt_serial_read; + device->write = rt_serial_write; + device->control = rt_serial_control; - /* register uart1 on device subsystem */ - rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); + /* register uart1 on device subsystem */ + rt_device_register(device, "uart1", RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX); #endif - return RT_EOK; + return RT_EOK; } diff --git a/libcpu/xilinx/microblaze/stack.c b/libcpu/xilinx/microblaze/stack.c index 686fc078a3..87f1dfa014 100755 --- a/libcpu/xilinx/microblaze/stack.c +++ b/libcpu/xilinx/microblaze/stack.c @@ -29,43 +29,43 @@ extern void *_SDA2_BASE_; * @return stack address */ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, - rt_uint8_t *stack_addr, void *texit) + rt_uint8_t *stack_addr, void *texit) { - unsigned long *stk; + unsigned long *stk; - stk = (unsigned long *)stack_addr; - stk--; - stk--; - *stk-- = 0; /* r31 */ - *stk-- = 0; /* r30 */ - *stk-- = 0; /* r29 */ - *stk-- = 0; /* r28 */ - *stk-- = 0; /* r27 */ - *stk-- = 0; /* r26 */ - *stk-- = 0; /* r25 */ - *stk-- = 0; /* r24 */ - *stk-- = 0; /* r23 */ - *stk-- = 0; /* r22 */ - *stk-- = 0; /* r21 */ - *stk-- = 0; /* r20 */ - *stk-- = 0; /* r19 */ - *stk-- = 0; /* r18 */ - *stk-- = 0; /* r17 */ - *stk-- = (unsigned long)texit - 8; /* r15 = task return address*/ - *stk-- = (unsigned long)tentry; /* r14 = entry address*/ - *stk-- = (unsigned long)&_SDA_BASE_; /* r13 */ - *stk-- = 0; /* r12 */ - *stk-- = 0; /* r11 */ - *stk-- = 0; /* r10 */ - *stk-- = 0; /* r09 */ - *stk-- = 0; /* r08 */ - *stk-- = 0; /* r07 */ - *stk-- = 0; /* r06 */ - *stk-- = (unsigned long) parameter; /* r05 */ - *stk-- = 0; /* r04 */ - *stk-- = 0; /* r03 */ - *stk-- = (unsigned long)&_SDA2_BASE_; /* r02 */ - *stk = 2; /* enable interrupt */ - return (rt_uint8_t *)stk; + stk = (unsigned long *)stack_addr; + stk--; + stk--; + *stk-- = 0; /* r31 */ + *stk-- = 0; /* r30 */ + *stk-- = 0; /* r29 */ + *stk-- = 0; /* r28 */ + *stk-- = 0; /* r27 */ + *stk-- = 0; /* r26 */ + *stk-- = 0; /* r25 */ + *stk-- = 0; /* r24 */ + *stk-- = 0; /* r23 */ + *stk-- = 0; /* r22 */ + *stk-- = 0; /* r21 */ + *stk-- = 0; /* r20 */ + *stk-- = 0; /* r19 */ + *stk-- = 0; /* r18 */ + *stk-- = 0; /* r17 */ + *stk-- = (unsigned long)texit - 8; /* r15 = task return address*/ + *stk-- = (unsigned long)tentry; /* r14 = entry address*/ + *stk-- = (unsigned long)&_SDA_BASE_; /* r13 */ + *stk-- = 0; /* r12 */ + *stk-- = 0; /* r11 */ + *stk-- = 0; /* r10 */ + *stk-- = 0; /* r09 */ + *stk-- = 0; /* r08 */ + *stk-- = 0; /* r07 */ + *stk-- = 0; /* r06 */ + *stk-- = (unsigned long) parameter; /* r05 */ + *stk-- = 0; /* r04 */ + *stk-- = 0; /* r03 */ + *stk-- = (unsigned long)&_SDA2_BASE_; /* r02 */ + *stk = 2; /* enable interrupt */ + return (rt_uint8_t *)stk; } diff --git a/libcpu/xilinx/microblaze/trap.c b/libcpu/xilinx/microblaze/trap.c index 3b3f98d105..bcfb3cc492 100755 --- a/libcpu/xilinx/microblaze/trap.c +++ b/libcpu/xilinx/microblaze/trap.c @@ -10,13 +10,13 @@ * Change Logs: * Date Author Notes * 2006-08-23 Bernard first version - * 2011-12-17 nl1031 for MicroBlaze + * 2011-12-17 nl1031 for MicroBlaze * */ -#include <rtthread.h> -#include "xparameters.h" -#include "xintc.h" +#include <rtthread.h> +#include "xparameters.h" +#include "xintc.h" #include "xintc_i.h" #include "xintc_l.h" @@ -33,7 +33,7 @@ rt_uint32_t rt_thread_switch_interrupt_flag; void rt_hw_interrupt_handler(int vector) { - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); + rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); } /** @@ -41,24 +41,24 @@ void rt_hw_interrupt_handler(int vector) */ void rt_hw_interrupt_init() { - rt_base_t index; + rt_base_t index; - XIntc_Config *CfgPtr; + XIntc_Config *CfgPtr; CfgPtr = &XIntc_ConfigTable[0]; - for (index = 0; index < MAX_HANDLERS; index ++) - { - CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler; - } + for (index = 0; index < MAX_HANDLERS; index ++) + { + CfgPtr->HandlerTable[index].Handler = (XInterruptHandler)rt_hw_interrupt_handler; + } - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; + /* init interrupt nest, and context in thread sp */ + rt_interrupt_nest = 0; + rt_interrupt_from_thread = 0; + rt_interrupt_to_thread = 0; + rt_thread_switch_interrupt_flag = 0; } /** @@ -67,8 +67,8 @@ void rt_hw_interrupt_init() */ void rt_hw_interrupt_mask(int vector) { - /* disable interrupt */ - XIntc_Disable(&int_ctl,vector); + /* disable interrupt */ + XIntc_Disable(&int_ctl,vector); } /** @@ -77,7 +77,7 @@ void rt_hw_interrupt_mask(int vector) */ void rt_hw_interrupt_umask(int vector) { - XIntc_Enable(&int_ctl,vector); + XIntc_Enable(&int_ctl,vector); } /** @@ -88,15 +88,15 @@ void rt_hw_interrupt_umask(int vector) */ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_handler_t *old_handler) { - XIntc_Config *CfgPtr; + XIntc_Config *CfgPtr; CfgPtr = &XIntc_ConfigTable[0]; - if(vector >= 0 && vector < MAX_HANDLERS) - { - if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)CfgPtr->HandlerTable[vector].Handler; - if (new_handler != RT_NULL) CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler)new_handler; - } + if(vector >= 0 && vector < MAX_HANDLERS) + { + if (*old_handler != RT_NULL) *old_handler = (rt_isr_handler_t)CfgPtr->HandlerTable[vector].Handler; + if (new_handler != RT_NULL) CfgPtr->HandlerTable[vector].Handler = (XInterruptHandler)new_handler; + } } /*****************************************************************************/ @@ -117,7 +117,7 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha * calling an interrupt handler. * * -* @return None. +* @return None. * * @note * @@ -131,81 +131,81 @@ void rt_hw_interrupt_install(int vector, rt_isr_handler_t new_handler, rt_isr_ha void rt_hw_trap_irq(void ) { - u32 intr_status; - u32 intr_mask = 1; - int intr_number; - volatile u32 reg; /* used as bit bucket */ - XIntc_Config *cfg_ptr; + u32 intr_status; + u32 intr_mask = 1; + int intr_number; + volatile u32 reg; /* used as bit bucket */ + XIntc_Config *cfg_ptr; - /* Get the configuration data using the device ID */ - cfg_ptr = &XIntc_ConfigTable[0]; + /* Get the configuration data using the device ID */ + cfg_ptr = &XIntc_ConfigTable[0]; - /* Get the interrupts that are waiting to be serviced */ - intr_status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR); + /* Get the interrupts that are waiting to be serviced */ + intr_status = XIntc_GetIntrStatus(XPAR_INTC_0_BASEADDR); - /* Service each interrupt that is active and enabled by checking each - * bit in the register from LSB to MSB which corresponds to an interrupt - * intput signal - */ - for (intr_number = 0; intr_number < XPAR_INTC_MAX_NUM_INTR_INPUTS; intr_number++) - { - if (intr_status & 1) - { - XIntc_VectorTableEntry *table_ptr; + /* Service each interrupt that is active and enabled by checking each + * bit in the register from LSB to MSB which corresponds to an interrupt + * intput signal + */ + for (intr_number = 0; intr_number < XPAR_INTC_MAX_NUM_INTR_INPUTS; intr_number++) + { + if (intr_status & 1) + { + XIntc_VectorTableEntry *table_ptr; - /* If the interrupt has been setup to acknowledge it - * before servicing the interrupt, then ack it - */ - if (cfg_ptr->AckBeforeService & intr_mask) - { - XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); - } + /* If the interrupt has been setup to acknowledge it + * before servicing the interrupt, then ack it + */ + if (cfg_ptr->AckBeforeService & intr_mask) + { + XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); + } - /* The interrupt is active and enabled, call the - * interrupt handler that was setup with the specified - * parameter - */ - table_ptr = &(cfg_ptr->HandlerTable[intr_number]); - table_ptr->Handler(table_ptr->CallBackRef); + /* The interrupt is active and enabled, call the + * interrupt handler that was setup with the specified + * parameter + */ + table_ptr = &(cfg_ptr->HandlerTable[intr_number]); + table_ptr->Handler(table_ptr->CallBackRef); - /* If the interrupt has been setup to acknowledge it - * after it has been serviced then ack it - */ - if ((cfg_ptr->AckBeforeService & intr_mask) == 0) - { - XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); - } + /* If the interrupt has been setup to acknowledge it + * after it has been serviced then ack it + */ + if ((cfg_ptr->AckBeforeService & intr_mask) == 0) + { + XIntc_AckIntr(cfg_ptr->BaseAddress, intr_mask); + } - /* - * Read the ISR again to handle architectures with posted write - * bus access issues. - */ - reg = XIntc_GetIntrStatus(cfg_ptr->BaseAddress); + /* + * Read the ISR again to handle architectures with posted write + * bus access issues. + */ + reg = XIntc_GetIntrStatus(cfg_ptr->BaseAddress); - /* - * If only the highest priority interrupt is to be - * serviced, exit loop and return after servicing - * the interrupt - */ - if (cfg_ptr->Options == XIN_SVC_SGL_ISR_OPTION) - { - return; - } - } + /* + * If only the highest priority interrupt is to be + * serviced, exit loop and return after servicing + * the interrupt + */ + if (cfg_ptr->Options == XIN_SVC_SGL_ISR_OPTION) + { + return; + } + } - /* Move to the next interrupt to check */ - intr_mask <<= 1; - intr_status >>= 1; + /* Move to the next interrupt to check */ + intr_mask <<= 1; + intr_status >>= 1; - /* If there are no other bits set indicating that all interrupts - * have been serviced, then exit the loop - */ - if (intr_status == 0) - { - break; - } - } + /* If there are no other bits set indicating that all interrupts + * have been serviced, then exit the loop + */ + if (intr_status == 0) + { + break; + } + } } |