[kernel] Add hook for malloc services

Including the patch for memory allocation, testsuites and fixups of
static analysis.

Signed-off-by: Shell <[email protected]>

5 files changed, 77 insertions, 42 deletions

diff --git a/libcpu/aarch64/common/backtrace.c b/libcpu/aarch64/common/backtrace.c
index 12cc3aedbf..7869d4960a 100644
--- a/libcpu/aarch64/common/backtrace.c
+++ b/libcpu/aarch64/common/backtrace.c
@@ -24,10 +24,19 @@
 #define INST_WORD_BYTES                 4
 #define WORD                            sizeof(rt_base_t)
 #define ARCH_CONTEXT_FETCH(pctx, id)    (*(((unsigned long *)pctx) + (id)))
+#define PTR_NORMALIZE(ptr)              (ptr = rt_backtrace_ptr_normalize(ptr))
+
+rt_weak void *rt_backtrace_ptr_normalize(void *ptr)
+{
+    return ptr;
+}
 
 rt_inline rt_err_t _bt_kaddr(rt_ubase_t *fp, struct rt_hw_backtrace_frame *frame)
 {
     rt_err_t rc;
+
+    PTR_NORMALIZE(fp);
+
     frame->fp = *fp;
     frame->pc = *(fp + 1) - INST_WORD_BYTES;
 
diff --git a/libcpu/aarch64/common/cpu.c b/libcpu/aarch64/common/cpu.c
index 15b17629a3..75781abdae 100644
--- a/libcpu/aarch64/common/cpu.c
+++ b/libcpu/aarch64/common/cpu.c
@@ -152,7 +152,7 @@ static int _cpus_init(int num_cpus, rt_uint64_t *cpu_hw_ids, struct cpu_ops_t *c
     // assuming that cpuid 0 has already init
     for (int i = 1; i < RT_CPUS_NR; i++)
     {
-        if (cpuid_to_hwid(i) == ID_ERROR)
+        if (rt_cpu_mpidr_early[i] == ID_ERROR)
         {
             LOG_E("Failed to find hardware id of CPU %d", i);
             continue;
@@ -166,7 +166,7 @@ static int _cpus_init(int num_cpus, rt_uint64_t *cpu_hw_ids, struct cpu_ops_t *c
         else
         {
             LOG_E("Failed to find cpu_init for cpu %d with cpu_ops[%p], cpu_ops->cpu_init[%p]"
-                , cpuid_to_hwid(i), cpu_ops_tbl[i], cpu_ops_tbl[i] ? cpu_ops_tbl[i]->cpu_init : NULL);
+                , rt_cpu_mpidr_early[i], cpu_ops_tbl[i], cpu_ops_tbl[i] ? cpu_ops_tbl[i]->cpu_init : NULL);
         }
     }
     return 0;
@@ -204,20 +204,4 @@ const char *rt_hw_cpu_arch(void)
     return "aarch64";
 }
 
-#ifdef RT_USING_CPU_FFS
-/**
- * This function finds the first bit set (beginning with the least significant bit)
- * in value and return the index of that bit.
- *
- * Bits are numbered starting at 1 (the least significant bit).  A return value of
- * zero from any of these functions means that the argument was zero.
- *
- * @return return the index of the first bit set. If value is 0, then this function
- * shall return 0.
- */
-int __rt_ffs(int value)
-{
-    return __builtin_ffs(value);
-}
-#endif
 /*@}*/
diff --git a/libcpu/aarch64/common/cpuport.h b/libcpu/aarch64/common/cpuport.h
index 00618fdfa0..1108ce98fe 100644
--- a/libcpu/aarch64/common/cpuport.h
+++ b/libcpu/aarch64/common/cpuport.h
@@ -5,6 +5,8 @@
  *
  * Change Logs:
  * Date           Author       Notes
+ * 2023-10-25     Shell        Move ffs to cpuport, add general implementation
+ *                             by inline assembly
  */
 
 #ifndef  CPUPORT_H__
@@ -35,4 +37,35 @@ typedef struct {
 #define rt_hw_cpu_relax() rt_hw_barrier(yield)
 
 void _thread_start(void);
+
+#ifdef RT_USING_CPU_FFS
+/**
+ * This function finds the first bit set (beginning with the least significant bit)
+ * in value and return the index of that bit.
+ *
+ * Bits are numbered starting at 1 (the least significant bit).  A return value of
+ * zero from any of these functions means that the argument was zero.
+ *
+ * @return return the index of the first bit set. If value is 0, then this function
+ * shall return 0.
+ */
+rt_inline int __rt_ffs(int value)
+{
+#ifdef __GNUC__
+    return __builtin_ffs(value);
+#else
+    __asm__ volatile (
+        "rbit w1, %w0\n"
+        "cmp %w0, 0\n"
+        "clz w1, w1\n"
+        "csinc %w0, wzr, w1, eq\n"
+        : "=r"(value)
+        : "0"(value)
+    );
+    return value;
+#endif
+}
+
+#endif /* RT_USING_CPU_FFS */
+
 #endif  /*CPUPORT_H__*/
diff --git a/libcpu/aarch64/common/mmu.c b/libcpu/aarch64/common/mmu.c
index 95cff08476..2485949367 100644
--- a/libcpu/aarch64/common/mmu.c
+++ b/libcpu/aarch64/common/mmu.c
@@ -9,6 +9,11 @@
  * 2021-11-28     GuEe-GUI     first version
  * 2022-12-10     WangXiaoyao  porting to MM
  */
+
+#define DBG_TAG "hw.mmu"
+#define DBG_LVL DBG_LOG
+#include <rtdbg.h>
+
 #include <rthw.h>
 #include <rtthread.h>
 #include <stddef.h>
@@ -27,9 +32,8 @@
 #include <lwp_mm.h>
 #endif
 
-#define DBG_TAG "hw.mmu"
-#define DBG_LVL DBG_LOG
-#include <rtdbg.h>
+#define TCR_CONFIG_TBI0     rt_hw_mmu_config_tbi(0)
+#define TCR_CONFIG_TBI1     rt_hw_mmu_config_tbi(1)
 
 #define MMU_LEVEL_MASK   0x1ffUL
 #define MMU_LEVEL_SHIFT  9
@@ -482,6 +486,11 @@ int rt_hw_mmu_map_init(rt_aspace_t aspace, void *v_address, size_t size,
     return 0;
 }
 
+rt_weak long rt_hw_mmu_config_tbi(int tbi_index)
+{
+    return 0;
+}
+
 /************ setting el1 mmu register**************
   MAIR_EL1
   index 0 : memory outer writeback, write/read alloc
@@ -500,25 +509,25 @@ void mmu_tcr_init(void)
     pa_range = val64 & 0xf; /* PARange */
 
     /* TCR_EL1 */
-    val64 = (16UL << 0)      /* t0sz 48bit */
-            | (0x0UL << 6)   /* reserved */
-            | (0x0UL << 7)   /* epd0 */
-            | (0x3UL << 8)   /* t0 wb cacheable */
-            | (0x3UL << 10)  /* inner shareable */
-            | (0x2UL << 12)  /* t0 outer shareable */
-            | (0x0UL << 14)  /* t0 4K */
-            | (16UL << 16)   /* t1sz 48bit */
-            | (0x0UL << 22)  /* define asid use ttbr0.asid */
-            | (0x0UL << 23)  /* epd1 */
-            | (0x3UL << 24)  /* t1 inner wb cacheable */
-            | (0x3UL << 26)  /* t1 outer wb cacheable */
-            | (0x2UL << 28)  /* t1 outer shareable */
-            | (0x2UL << 30)  /* t1 4k */
-            | (pa_range << 32)  /* PA range */
-            | (0x0UL << 35)  /* reserved */
-            | (0x1UL << 36)  /* as: 0:8bit 1:16bit */
-            | (0x0UL << 37)  /* tbi0 */
-            | (0x0UL << 38); /* tbi1 */
+    val64 = (16UL << 0)                /* t0sz 48bit */
+            | (0x0UL << 6)             /* reserved */
+            | (0x0UL << 7)             /* epd0 */
+            | (0x3UL << 8)             /* t0 wb cacheable */
+            | (0x3UL << 10)            /* inner shareable */
+            | (0x2UL << 12)            /* t0 outer shareable */
+            | (0x0UL << 14)            /* t0 4K */
+            | (16UL << 16)             /* t1sz 48bit */
+            | (0x0UL << 22)            /* define asid use ttbr0.asid */
+            | (0x0UL << 23)            /* epd1 */
+            | (0x3UL << 24)            /* t1 inner wb cacheable */
+            | (0x3UL << 26)            /* t1 outer wb cacheable */
+            | (0x2UL << 28)            /* t1 outer shareable */
+            | (0x2UL << 30)            /* t1 4k */
+            | (pa_range << 32)         /* PA range */
+            | (0x0UL << 35)            /* reserved */
+            | (0x1UL << 36)            /* as: 0:8bit 1:16bit */
+            | (TCR_CONFIG_TBI0 << 37)  /* tbi0 */
+            | (TCR_CONFIG_TBI1 << 38); /* tbi1 */
     __asm__ volatile("msr TCR_EL1, %0\n" ::"r"(val64));
 }
 
diff --git a/libcpu/aarch64/common/mmu.h b/libcpu/aarch64/common/mmu.h
index 5b6d3a78e6..a441a526e3 100644
--- a/libcpu/aarch64/common/mmu.h
+++ b/libcpu/aarch64/common/mmu.h
@@ -110,11 +110,11 @@ void rt_hw_mmu_kernel_map_init(struct rt_aspace *aspace, rt_size_t vaddr_start,
 void *rt_hw_mmu_pgtbl_create(void);
 void rt_hw_mmu_pgtbl_delete(void *pgtbl);
 
-static inline void *rt_hw_mmu_tbl_get()
+rt_inline void *rt_hw_mmu_tbl_get()
 {
     uintptr_t tbl;
     __asm__ volatile("MRS %0, TTBR0_EL1" : "=r"(tbl));
-    return (void *)(tbl & ((1ul << 48) - 2));
+    return rt_kmem_p2v((void *)(tbl & ((1ul << 48) - 2)));
 }
 
 static inline void *rt_hw_mmu_kernel_v2p(void *v_addr)