bsp beaglebone: add IAR support (#6443)

* bsp beaglebone: add IAR template files and fix it's build error

ATTENTION:
project.* was generated by scons, so I add it to gitignore.
rtconfig.py *FLAGS located in "PLATFORM == 'iccarm'" are unverified and maybe wrong.
（我只是从STM32里面抄来，然后根据自己的理解改了一下，并没有验证这些参数的正确性，
我也不知道怎么用命令行调用这些参数来编译）

* bsp beaglebone: add beaglebone_ram.icf ROM address from uboot_cmd.txt

am335x_DDR.icf use 0x82000000, different to uboot_cmd.txt & gcc beaglebone_ram.lds,
the difference will easy cause later developer got below error:

=> go 0x80200000
## Starting application at 0x80200000 ...
undefined instruction
pc : [<8200956c>]	   lr : [<8ff62497>]
reloc pc : [<728a956c>]	   lr : [<80802497>]
sp : 8df37358  ip : 00000000	 fp : 00000002
r10: 8df4d448  r9 : 8df3feb8	 r8 : 8ffd30f8
r7 : 8ff78089  r6 : 00000002	 r5 : 80200000  r4 : 8df4d44c
r3 : 80200000  r2 : 8df4d44c	 r1 : 8df4d44c  r0 : 00000001
Flags: nzCv  IRQs off  FIQs on  Mode SVC_32
Code: 5dbffcdd bb9bdf7f abf85423 eff1f77f (7ed7daaf)
Resetting CPU ...

resetting ...

* libcpu am335x: context_iar.S rt_hw_context_switch: add thumb mode support

IAR new project defualt Processor mode is Thumb, this will cause user
easy occur the following error:
...
msh />Execption:
r00:0x8800aaa8 r01:0x802080c5 r02:0x00000000 r03:0x88009b4c
r04:0x00001000 r05:0x00000000 r06:0x00001403 r07:0x00100000
r08:0x00000000 r09:0x00000000 r10:0x0000000a
fp :0x0000000a ip :0x65687374
sp :0x00006c6c lr :0x0000008a pc :0x88008be0
cpsr:0x880001bc
software interrupt
shutdown...
(0) assertion failed at function:rt_hw_cpu_shutdown, line number:160

* bsp beaglebone: change IAR template.ewp code use Arm mode

Arm mode bin size will bigger than Thumb mode

* libcpu am335x: IAR: use rt_hw_cpu_dcache_enable instead of rt_cpu_dcache_enable

Reviewer mysterywolf say:
麻烦把rt_cpu_icache_enable 和 rt_cpu_dcache_enable, 统一改成 rt_hw_cpu_icache_enable 和 rt_hw_cpu_dcache_enable
rt_hw_cpu_icache_enable 和 rt_hw_cpu_dcache_enable 是其他bsp也是这么命名的 这是个命名统一的函数

3 files changed, 41 insertions, 4 deletions

diff --git a/libcpu/arm/am335x/context_iar.S b/libcpu/arm/am335x/context_iar.S
index 1266d8cf74..a800367cfa 100644
--- a/libcpu/arm/am335x/context_iar.S
+++ b/libcpu/arm/am335x/context_iar.S
@@ -40,6 +40,8 @@ rt_hw_context_switch:
     STMFD   SP!, {LR}               ; push pc (lr should be pushed in place of PC)
     STMFD   SP!, {R0-R12, LR}       ; push lr & register file
     MRS     R4, CPSR
+    TST     LR, #0x01
+    ORRNE   R4, R4, #0x20           ; it's thumb code
     STMFD   SP!, {R4}               ; push cpsr
     STR     SP, [R0]                ; store sp in preempted tasks TCB
     LDR     SP, [R1]                ; get new task stack pointer
@@ -56,6 +58,8 @@ rt_hw_context_switch_to:
     LDR     SP, [R0]                ; get new task stack pointer
     LDMFD   SP!, {R4}               ; pop new task spsr
     MSR     SPSR_cxsf, R4
+    BIC     R4, R4, #0x20           ; must be ARM mode
+    MSR     CPSR_CXSF, R4
     LDMFD   SP!, {R0-R12, LR, PC}^  ; pop new task r0-r12, lr & pc
 
 /*
diff --git a/libcpu/arm/am335x/cpu.c b/libcpu/arm/am335x/cpu.c
index f04994af26..3688d31d56 100644
--- a/libcpu/arm/am335x/cpu.c
+++ b/libcpu/arm/am335x/cpu.c
@@ -6,6 +6,8 @@
  * Change Logs:
  * Date           Author       Notes
  * 2011-09-15     Bernard      first version
+ * 2022-09-20     YangZhongQing
+ *                             add IAR assembler
  */
 
 #include <rthw.h>
@@ -86,10 +88,42 @@ rt_inline void cache_disable(rt_uint32_t bit)
         :"r" (bit)                  \
         :"memory");
 }
-#endif
+#elif defined(__ICCARM__)
+rt_inline rt_uint32_t cp15_rd(void)
+{
+    rt_uint32_t i;
+
+    __asm volatile("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
+    return i;
+}
+
+rt_inline void cache_enable(rt_uint32_t bit)
+{
+    rt_uint32_t tmp;
 
+    __asm volatile(                 \
+        "mrc  p15,0,%0,c1,c0,0\n\t" \
+        "orr  %0,%0,%1\n\t"         \
+        "mcr  p15,0,%0,c1,c0,0"     \
+        :"+r"(tmp)                  \
+        :"r"(bit)                   \
+        :"memory");
+}
+
+rt_inline void cache_disable(rt_uint32_t bit)
+{
+    rt_uint32_t tmp;
+
+    __asm volatile(                 \
+        "mrc  p15,0,%0,c1,c0,0\n\t" \
+        "bic  %0,%0,%1\n\t"         \
+        "mcr  p15,0,%0,c1,c0,0"     \
+        :"+r"(tmp)                  \
+        :"r"(bit)                   \
+        :"memory");
+}
+#endif
 
-#if defined(__CC_ARM)|(__GNUC__)
 /**
  * enable I-Cache
  *
@@ -143,7 +177,6 @@ rt_base_t rt_hw_cpu_dcache_status()
 {
     return (cp15_rd() & DCACHE_MASK);
 }
-#endif
 
 /**
  *  shutdown CPU
diff --git a/libcpu/arm/am335x/mmu.c b/libcpu/arm/am335x/mmu.c
index fbd886d0e6..19cc9fc6e0 100644
--- a/libcpu/arm/am335x/mmu.c
+++ b/libcpu/arm/am335x/mmu.c
@@ -145,7 +145,7 @@ static volatile unsigned int _page_table[4*1024] __attribute__((aligned(16*1024)
 void mmu_setmtt(rt_uint32_t vaddrStart, rt_uint32_t vaddrEnd, rt_uint32_t paddrStart, rt_uint32_t attr)
 {
     volatile rt_uint32_t *pTT;
-    volatile int i,nSec;
+    int i,nSec;
     pTT=(rt_uint32_t *)_page_table+(vaddrStart>>20);
     nSec=(vaddrEnd>>20)-(vaddrStart>>20);
     for(i=0;i<=nSec;i++)