fix the cm3 assemble function issue.

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@121 bbd45198-f89e-11dd-88c7-29a3b14d5316

3 files changed, 8 insertions, 20 deletions

diff --git a/libcpu/arm/stm32/context_gcc.S b/libcpu/arm/stm32/context_gcc.S
index 8d4271ecfe..9fe6c23882 100644
--- a/libcpu/arm/stm32/context_gcc.S
+++ b/libcpu/arm/stm32/context_gcc.S
@@ -32,6 +32,7 @@
  * rt_base_t rt_hw_interrupt_disable();

  */

 .global rt_hw_interrupt_disable

+.type rt_hw_interrupt_disable, %function

 rt_hw_interrupt_disable:

 	MRS		r0, PRIMASK

 	CPSID		I

@@ -41,6 +42,7 @@ rt_hw_interrupt_disable:
  * void rt_hw_interrupt_enable(rt_base_t level);

  */

 .global rt_hw_interrupt_enable

+.type rt_hw_interrupt_enable, %function

 rt_hw_interrupt_enable:

 	MSR		PRIMASK, r0

 	BX		LR

@@ -51,7 +53,9 @@ rt_hw_interrupt_enable:
  * r1 --> to

  */

 .global rt_hw_context_switch_interrupt

+.type rt_hw_context_switch_interrupt, %function

 .global rt_hw_context_switch

+.type rt_hw_context_switch, %function

 

 rt_hw_context_switch_interrupt:

 rt_hw_context_switch:

@@ -80,6 +84,7 @@ _reswitch:
  * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack

  */

 .global rt_hw_pend_sv

+.type rt_hw_pend_sv, %function

 rt_hw_pend_sv:

 	/* disable interrupt to protect context switch */

 	MRS		r2, PRIMASK

@@ -118,6 +123,7 @@ swtich_to_thread:
  * r0 --> to

  */

 .global rt_hw_context_switch_to

+.type rt_hw_context_switch_to, %function

 rt_hw_context_switch_to:

 	LDR		r1, =rt_interrupt_to_thread

 	STR		r0, [r1]

@@ -142,6 +148,7 @@ rt_hw_context_switch_to:
 

 /* compatible with old version */

 .global rt_hw_interrupt_thread_switch

+.type rt_hw_interrupt_thread_switch, %function

 rt_hw_interrupt_thread_switch:

 	BX		lr

 	NOP

diff --git a/libcpu/arm/stm32/fault_gcc.S b/libcpu/arm/stm32/fault_gcc.S
index 6aae535043..929c9c380e 100644
--- a/libcpu/arm/stm32/fault_gcc.S
+++ b/libcpu/arm/stm32/fault_gcc.S
@@ -19,6 +19,7 @@
 .text

 

 .global rt_hw_hard_fault

+.type rt_hw_hard_fault, %function

 rt_hw_hard_fault:

     /* get current context */

     MRS     r0, psp                 /* get fault thread stack pointer */

diff --git a/libcpu/arm/stm32/start_gcc.s b/libcpu/arm/stm32/start_gcc.s
index eaecc16fd3..6dc850bed5 100644
--- a/libcpu/arm/stm32/start_gcc.s
+++ b/libcpu/arm/stm32/start_gcc.s
@@ -34,7 +34,6 @@
   .thumb

 

 .global  g_pfnVectors

-.global  SystemInit_ExtMemCtl_Dummy

 .global  Default_Handler

 

 /* start address for the initialization values of the .data section. 

@@ -48,7 +47,6 @@ defined in linker script */
 .word  _sbss

 /* end address for the .bss section. defined in linker script */

 .word  _ebss

-/* stack used for SystemInit_ExtMemCtl; always internal RAM used */

 

 .equ  Initial_spTop,  0x20000400 

 .equ  BootRAM,        0xF1E0F85F

@@ -65,10 +63,6 @@ defined in linker script */
   .weak  Reset_Handler

   .type  Reset_Handler, %function

 Reset_Handler:  

-

-/* FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 

-  required, then adjust the Register Addresses */

-  bl  SystemInit_ExtMemCtl

 /* restore original stack pointer */  

   LDR r0, =_estack

   MSR msp, r0

@@ -105,16 +99,6 @@ LoopFillZerobss:
 .size  Reset_Handler, .-Reset_Handler

 

 /**

- * @brief  Dummy SystemInit_ExtMemCtl function 

- * @param  None     

- * @retval : None       

-*/

-  .section  .text.SystemInit_ExtMemCtl_Dummy,"ax",%progbits

-SystemInit_ExtMemCtl_Dummy:

-  bx  lr

-  .size  SystemInit_ExtMemCtl_Dummy, .-SystemInit_ExtMemCtl_Dummy

-

-/**

  * @brief  This is the code that gets called when the processor receives an 

  *         unexpected interrupt.  This simply enters an infinite loop, preserving

  *         the system state for examination by a debugger.

@@ -468,7 +452,3 @@ g_pfnVectors:
 

   .weak  DMA2_Channel4_5_IRQHandler

   .thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler

-

-  .weak  SystemInit_ExtMemCtl

-  .thumb_set SystemInit_ExtMemCtl,SystemInit_ExtMemCtl_Dummy

-