Merge pull request #1 from RT-Thread/master

sync

49 files changed, 1631 insertions, 2732 deletions

diff --git a/libcpu/arm/cortex-m0/context_gcc.S b/libcpu/arm/cortex-m0/context_gcc.S
index 997c345179..3186a5ae9f 100644
--- a/libcpu/arm/cortex-m0/context_gcc.S
+++ b/libcpu/arm/cortex-m0/context_gcc.S
@@ -79,8 +79,8 @@ _reswitch:
     STR     R1, [R0]
     BX      LR
 
-/* R0 --> swith from thread stack
- * R1 --> swith to thread stack
+/* R0 --> switch from thread stack
+ * R1 --> switch to thread stack
  * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
  */
     .global PendSV_Handler
@@ -103,7 +103,7 @@ PendSV_Handler:
     LDR     R0, =rt_interrupt_from_thread
     LDR     R1, [R0]
     CMP     R1, #0x00
-    BEQ     swtich_to_thread    /* skip register save at the first time */
+    BEQ     switch_to_thread    /* skip register save at the first time */
 
 	MRS     R1, PSP                 /* get from thread stack pointer */
 
@@ -118,7 +118,7 @@ PendSV_Handler:
     MOV     R6, R10
     MOV     R7, R11
     STMIA   R1!, {R4 - R7}          /* push thread {R8 - R11} high register to thread stack */
-swtich_to_thread:
+switch_to_thread:
     LDR     R1, =rt_interrupt_to_thread
     LDR     R1, [R1]
     LDR     R1, [R1]                /* load thread stack pointer */
diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S
index f1318e552d..67ea808d8c 100644
--- a/libcpu/arm/cortex-m0/context_iar.S
+++ b/libcpu/arm/cortex-m0/context_iar.S
@@ -81,8 +81,8 @@ _reswitch
     STR     r1, [r0]
     BX      LR
 
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
     EXPORT PendSV_Handler
 PendSV_Handler:
@@ -104,7 +104,7 @@ PendSV_Handler:
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
     CMP     r1, #0x00
-    BEQ     swtich_to_thread        ; skip register save at the first time
+    BEQ     switch_to_thread        ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
 
@@ -120,7 +120,7 @@ PendSV_Handler:
     MOV     r7, r11
     STMIA   r1!, {r4 - r7}          ; push thread {r8 - r11} high register to thread stack
 
-swtich_to_thread
+switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer
diff --git a/libcpu/arm/cortex-m0/context_rvds.S b/libcpu/arm/cortex-m0/context_rvds.S
index 9c2f42ac83..89ac029282 100644
--- a/libcpu/arm/cortex-m0/context_rvds.S
+++ b/libcpu/arm/cortex-m0/context_rvds.S
@@ -85,8 +85,8 @@ _reswitch
     BX      LR
     ENDP
 
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
 PendSV_Handler    PROC
     EXPORT PendSV_Handler
@@ -108,7 +108,7 @@ PendSV_Handler    PROC
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
     CMP     r1, #0x00
-    BEQ     swtich_to_thread        ; skip register save at the first time
+    BEQ     switch_to_thread        ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
 
@@ -124,7 +124,7 @@ PendSV_Handler    PROC
     MOV     r7, r11
     STMIA   r1!, {r4 - r7}          ; push thread {r8 - r11} high register to thread stack
 
-swtich_to_thread
+switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer
diff --git a/libcpu/arm/cortex-m3/context_gcc.S b/libcpu/arm/cortex-m3/context_gcc.S
index 7ff810d534..ca961bbd87 100644
--- a/libcpu/arm/cortex-m3/context_gcc.S
+++ b/libcpu/arm/cortex-m3/context_gcc.S
@@ -80,8 +80,8 @@ _reswitch:
     STR     R1, [R0]
     BX      LR
 
-/* R0 --> swith from thread stack
- * R1 --> swith to thread stack
+/* R0 --> switch from thread stack
+ * R1 --> switch to thread stack
  * psr, pc, LR, R12, R3, R2, R1, R0 are pushed into [from] stack
  */
     .global PendSV_Handler
@@ -102,14 +102,14 @@ PendSV_Handler:
 
     LDR     R0, =rt_interrupt_from_thread
     LDR     R1, [R0]
-    CBZ     R1, swtich_to_thread    /* skip register save at the first time */
+    CBZ     R1, switch_to_thread    /* skip register save at the first time */
 
     MRS     R1, PSP                 /* get from thread stack pointer */
     STMFD   R1!, {R4 - R11}         /* push R4 - R11 register */
     LDR     R0, [R0]
     STR     R1, [R0]                /* update from thread stack pointer */
 
-swtich_to_thread:
+switch_to_thread:
     LDR     R1, =rt_interrupt_to_thread
     LDR     R1, [R1]
     LDR     R1, [R1]                /* load thread stack pointer */
diff --git a/libcpu/arm/cortex-m3/context_iar.S b/libcpu/arm/cortex-m3/context_iar.S
index 7dc595f6c1..ad9fa0dd0f 100644
--- a/libcpu/arm/cortex-m3/context_iar.S
+++ b/libcpu/arm/cortex-m3/context_iar.S
@@ -81,8 +81,8 @@ _reswitch
     STR     r1, [r0]
     BX      LR
 
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
     EXPORT PendSV_Handler
 PendSV_Handler:
@@ -102,14 +102,14 @@ PendSV_Handler:
 
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
-    CBZ     r1, swtich_to_thread    ; skip register save at the first time
+    CBZ     r1, switch_to_thread    ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
     STMFD   r1!, {r4 - r11}         ; push r4 - r11 register
     LDR     r0, [r0]
     STR     r1, [r0]                ; update from thread stack pointer
 
-swtich_to_thread
+switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer
diff --git a/libcpu/arm/cortex-m3/context_rvds.S b/libcpu/arm/cortex-m3/context_rvds.S
index 7f431cc042..c86b70e1f9 100644
--- a/libcpu/arm/cortex-m3/context_rvds.S
+++ b/libcpu/arm/cortex-m3/context_rvds.S
@@ -84,8 +84,8 @@ _reswitch
     BX      LR
     ENDP
 
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
 PendSV_Handler   PROC
     EXPORT PendSV_Handler
@@ -105,14 +105,14 @@ PendSV_Handler   PROC
 
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
-    CBZ     r1, swtich_to_thread    ; skip register save at the first time
+    CBZ     r1, switch_to_thread    ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
     STMFD   r1!, {r4 - r11}         ; push r4 - r11 register
     LDR     r0, [r0]
     STR     r1, [r0]                ; update from thread stack pointer
 
-swtich_to_thread
+switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer
diff --git a/libcpu/arm/cortex-m4/context_gcc.S b/libcpu/arm/cortex-m4/context_gcc.S
index 6a910355a8..908a44f847 100644
--- a/libcpu/arm/cortex-m4/context_gcc.S
+++ b/libcpu/arm/cortex-m4/context_gcc.S
@@ -82,8 +82,8 @@ _reswitch:
     STR r1, [r0]
     BX  LR
 
-/* r0 --> swith from thread stack
- * r1 --> swith to thread stack
+/* r0 --> switch from thread stack
+ * r1 --> switch to thread stack
  * psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
  */
 .global PendSV_Handler
@@ -104,7 +104,7 @@ PendSV_Handler:
 
     LDR r0, =rt_interrupt_from_thread
     LDR r1, [r0]
-    CBZ r1, swtich_to_thread    /* skip register save at the first time */
+    CBZ r1, switch_to_thread    /* skip register save at the first time */
 
     MRS r1, psp                 /* get from thread stack pointer */
     
@@ -127,7 +127,7 @@ PendSV_Handler:
     LDR r0, [r0]
     STR r1, [r0]                /* update from thread stack pointer */
 
-swtich_to_thread:
+switch_to_thread:
     LDR r1, =rt_interrupt_to_thread
     LDR r1, [r1]
     LDR r1, [r1]                /* load thread stack pointer */
diff --git a/libcpu/arm/cortex-m4/context_iar.S b/libcpu/arm/cortex-m4/context_iar.S
index e882f36f64..8761a97052 100644
--- a/libcpu/arm/cortex-m4/context_iar.S
+++ b/libcpu/arm/cortex-m4/context_iar.S
@@ -82,8 +82,8 @@ _reswitch
     STR     r1, [r0]
     BX      LR
 
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
     EXPORT PendSV_Handler
 PendSV_Handler:
@@ -103,7 +103,7 @@ PendSV_Handler:
 
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
-    CBZ     r1, swtich_to_thread    ; skip register save at the first time
+    CBZ     r1, switch_to_thread    ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
 
@@ -130,7 +130,7 @@ push_flag
     LDR     r0, [r0]
     STR     r1, [r0]                ; update from thread stack pointer
 
-swtich_to_thread
+switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer
diff --git a/libcpu/arm/cortex-m4/context_rvds.S b/libcpu/arm/cortex-m4/context_rvds.S
index 189ae33db1..af7461fd49 100644
--- a/libcpu/arm/cortex-m4/context_rvds.S
+++ b/libcpu/arm/cortex-m4/context_rvds.S
@@ -85,8 +85,8 @@ _reswitch
     BX      LR
     ENDP
 
-; r0 --> swith from thread stack
-; r1 --> swith to thread stack
+; r0 --> switch from thread stack
+; r1 --> switch to thread stack
 ; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
 PendSV_Handler   PROC
     EXPORT PendSV_Handler
@@ -106,7 +106,7 @@ PendSV_Handler   PROC
 
     LDR     r0, =rt_interrupt_from_thread
     LDR     r1, [r0]
-    CBZ     r1, swtich_to_thread    ; skip register save at the first time
+    CBZ     r1, switch_to_thread    ; skip register save at the first time
 
     MRS     r1, psp                 ; get from thread stack pointer
 
@@ -129,7 +129,7 @@ PendSV_Handler   PROC
     LDR     r0, [r0]
     STR     r1, [r0]                ; update from thread stack pointer
 
-swtich_to_thread
+switch_to_thread
     LDR     r1, =rt_interrupt_to_thread
     LDR     r1, [r1]
     LDR     r1, [r1]                ; load thread stack pointer
diff --git a/libcpu/arm/zynq7000/SConscript b/libcpu/arm/zynq7000/SConscript
new file mode 100644
index 0000000000..2ad51b573e
--- /dev/null
+++ b/libcpu/arm/zynq7000/SConscript
@@ -0,0 +1,17 @@
+Import('rtconfig')
+from building import *
+
+cwd     = GetCurrentDir()
+src	= Glob('*.c')
+CPPPATH = [cwd]
+
+if rtconfig.PLATFORM == 'iar':
+        src += Glob('*_iar.S')
+elif rtconfig.PLATFORM == 'gcc':
+        src += Glob('*_gcc.S')
+elif rtconfig.PLATFORM == 'armcc':
+        src += Glob('*_rvds.S')
+
+group = DefineGroup('AM1808', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/libcpu/arm/zynq7000/armv7.h b/libcpu/arm/zynq7000/armv7.h
new file mode 100644
index 0000000000..65f6c27860
--- /dev/null
+++ b/libcpu/arm/zynq7000/armv7.h
@@ -0,0 +1,65 @@
+#ifndef __ARMV7_H__
+#define __ARMV7_H__
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/* the exception stack without VFP registers */
+struct rt_hw_exp_stack
+{
+	unsigned long r0;
+	unsigned long r1;
+	unsigned long r2;
+	unsigned long r3;
+	unsigned long r4;
+	unsigned long r5;
+	unsigned long r6;
+	unsigned long r7;
+	unsigned long r8;
+	unsigned long r9;
+	unsigned long r10;
+	unsigned long fp;
+	unsigned long ip;
+	unsigned long sp;
+	unsigned long lr;
+	unsigned long pc;
+	unsigned long cpsr;
+};
+
+#define USERMODE    0x10
+#define FIQMODE     0x11
+#define IRQMODE     0x12
+#define SVCMODE     0x13
+#define MONITORMODE 0x16
+#define ABORTMODE   0x17
+#define HYPMODE     0x1b
+#define UNDEFMODE   0x1b
+#define MODEMASK    0x1f
+#define NOINT       0xc0
+
+#define T_Bit       (1<<5)
+#define F_Bit       (1<<6)
+#define I_Bit       (1<<7)
+#define A_Bit       (1<<8)
+#define E_Bit       (1<<9)
+#define J_Bit       (1<<24)
+
+void rt_hw_mmu_init(void);
+
+#endif
diff --git a/libcpu/arm/zynq7000/context_gcc.S b/libcpu/arm/zynq7000/context_gcc.S
new file mode 100644
index 0000000000..3dbf3c861d
--- /dev/null
+++ b/libcpu/arm/zynq7000/context_gcc.S
@@ -0,0 +1,102 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#define NOINT           0xc0
+
+/*
+ * rt_base_t rt_hw_interrupt_disable();
+ */
+.globl rt_hw_interrupt_disable
+rt_hw_interrupt_disable:
+    mrs r0, cpsr
+    orr r1, r0, #NOINT
+    msr cpsr_c, r1
+    bx  lr
+
+/*
+ * void rt_hw_interrupt_enable(rt_base_t level);
+ */
+.globl rt_hw_interrupt_enable
+rt_hw_interrupt_enable:
+    msr cpsr, r0
+    bx  lr
+
+/*
+ * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
+ * r0 --> from
+ * r1 --> to
+ */
+.globl rt_hw_context_switch
+rt_hw_context_switch:
+    stmfd   sp!, {lr}       @ push pc (lr should be pushed in place of PC)
+    stmfd   sp!, {r0-r12, lr}   @ push lr & register file
+
+    mrs r4, cpsr
+    tst lr, #0x01
+    beq _ARM_MODE
+    orr r4, r4, #0x20       @ it's thumb code
+
+_ARM_MODE:
+    stmfd sp!, {r4}         @ push cpsr
+
+    str sp, [r0]            @ store sp in preempted tasks TCB
+    ldr sp, [r1]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task cpsr to spsr
+    msr spsr_cxsf, r4
+
+    ldmfd sp!, {r0-r12, lr, pc}^  @ pop new task r0-r12, lr & pc, copy spsr to cpsr
+
+/*
+ * void rt_hw_context_switch_to(rt_uint32 to);
+ * r0 --> to
+ */
+.globl rt_hw_context_switch_to
+rt_hw_context_switch_to:
+    ldr sp, [r0]            @ get new task stack pointer
+
+    ldmfd sp!, {r4}         @ pop new task spsr
+    msr spsr_cxsf, r4
+
+    bic r4, r4, #0x20       @ must be ARM mode
+    msr cpsr_cxsf, r4
+
+    ldmfd sp!, {r0-r12, lr, pc}^   @ pop new task r0-r12, lr & pc
+
+/*
+ * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
+ */
+.globl rt_thread_switch_interrupt_flag
+.globl rt_interrupt_from_thread
+.globl rt_interrupt_to_thread
+.globl rt_hw_context_switch_interrupt
+rt_hw_context_switch_interrupt:
+    ldr r2, =rt_thread_switch_interrupt_flag
+    ldr r3, [r2]
+    cmp r3, #1
+    beq _reswitch
+    mov r3, #1              @ set rt_thread_switch_interrupt_flag to 1
+    str r3, [r2]
+    ldr r2, =rt_interrupt_from_thread   @ set rt_interrupt_from_thread
+    str r0, [r2]
+_reswitch:
+    ldr r2, =rt_interrupt_to_thread     @ set rt_interrupt_to_thread
+    str r1, [r2]
+    bx  lr
diff --git a/libcpu/arm/zynq7000/cp15.h b/libcpu/arm/zynq7000/cp15.h
new file mode 100644
index 0000000000..bd6a23f1b2
--- /dev/null
+++ b/libcpu/arm/zynq7000/cp15.h
@@ -0,0 +1,31 @@
+#ifndef __CP15_H__
+#define __CP15_H__
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+unsigned long rt_cpu_get_smp_id(void);
+
+void rt_cpu_mmu_disable(void);
+void rt_cpu_mmu_enable(void);
+void rt_cpu_tlb_set(volatile unsigned long*);
+
+void rt_cpu_vector_set_base(unsigned int addr);
+
+#endif
diff --git a/libcpu/arm/zynq7000/cp15_gcc.S b/libcpu/arm/zynq7000/cp15_gcc.S
new file mode 100644
index 0000000000..f1ed6492aa
--- /dev/null
+++ b/libcpu/arm/zynq7000/cp15_gcc.S
@@ -0,0 +1,140 @@
+/*
+ * File      : cp15_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ * http://www.rt-thread.org
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.globl rt_cpu_get_smp_id
+rt_cpu_get_smp_id:
+    mrc     p15, #0, r0, c0, c0, #5
+    bx      lr
+
+.globl rt_cpu_vector_set_base
+rt_cpu_vector_set_base:
+    mcr     p15, #0, r0, c12, c0, #0
+    dsb
+    bx      lr
+
+.globl rt_hw_cpu_dcache_enable
+rt_hw_cpu_dcache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_hw_cpu_icache_enable
+rt_hw_cpu_icache_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+_FLD_MAX_WAY:
+   .word  0x3ff
+_FLD_MAX_IDX:
+   .word  0x7ff
+
+.globl rt_cpu_dcache_clean_flush
+rt_cpu_dcache_clean_flush:
+    push    {r4-r11}
+    dmb
+    mrc     p15, #1, r0, c0, c0, #1  @ read clid register
+    ands    r3, r0, #0x7000000       @ get level of coherency
+    mov     r3, r3, lsr #23
+    beq     finished
+    mov     r10, #0
+loop1:
+    add     r2, r10, r10, lsr #1
+    mov     r1, r0, lsr r2
+    and     r1, r1, #7
+    cmp     r1, #2
+    blt     skip
+    mcr     p15, #2, r10, c0, c0, #0
+    isb
+    mrc     p15, #1, r1, c0, c0, #0
+    and     r2, r1, #7
+    add     r2, r2, #4
+    ldr     r4, _FLD_MAX_WAY
+    ands    r4, r4, r1, lsr #3
+    clz     r5, r4
+    ldr     r7, _FLD_MAX_IDX
+    ands    r7, r7, r1, lsr #13
+loop2:
+    mov     r9, r4
+loop3:
+    orr     r11, r10, r9, lsl r5
+    orr     r11, r11, r7, lsl r2
+    mcr     p15, #0, r11, c7, c14, #2
+    subs    r9, r9, #1
+    bge     loop3
+    subs    r7, r7, #1
+    bge     loop2
+skip:
+    add     r10, r10, #2
+    cmp     r3, r10
+    bgt     loop1
+
+finished:
+    dsb
+    isb
+    pop     {r4-r11}
+    bx      lr
+
+.globl rt_hw_cpu_dcache_disable
+rt_hw_cpu_dcache_disable:
+    push    {r4-r11, lr}
+    bl      rt_cpu_dcache_clean_flush
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00000004
+    mcr     p15, #0, r0, c1, c0, #0
+    pop     {r4-r11, lr}
+    bx      lr
+
+.globl rt_hw_cpu_icache_disable
+rt_hw_cpu_icache_disable:
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0,  r0, #0x00001000
+    mcr     p15, #0, r0, c1, c0, #0
+    bx      lr
+
+.globl rt_cpu_mmu_disable
+rt_cpu_mmu_disable:
+    mcr     p15, #0, r0, c8, c7, #0    @ invalidate tlb
+    mrc     p15, #0, r0, c1, c0, #0
+    bic     r0, r0, #1
+    mcr     p15, #0, r0, c1, c0, #0    @ clear mmu bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_mmu_enable
+rt_cpu_mmu_enable:
+    mrc     p15, #0, r0, c1, c0, #0
+    orr     r0, r0, #0x001
+    mcr     p15, #0, r0, c1, c0, #0    @ set mmu enable bit
+    dsb
+    bx      lr
+
+.globl rt_cpu_tlb_set
+rt_cpu_tlb_set:
+    mcr     p15, #0, r0, c2, c0, #0
+    dmb
+    bx      lr
diff --git a/libcpu/arm/zynq7000/cpu.c b/libcpu/arm/zynq7000/cpu.c
new file mode 100644
index 0000000000..9853effe3c
--- /dev/null
+++ b/libcpu/arm/zynq7000/cpu.c
@@ -0,0 +1,45 @@
+/*
+ * File      : cpu.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-20     Bernard      first version
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "zynq7000.h"
+
+/**
+ * reset cpu by dog's time-out
+ *
+ */
+void rt_hw_cpu_reset()
+{
+    while (1);  /* loop forever and wait for reset to happen */
+
+    /* NEVER REACHED */
+}
+
+/**
+ *  shutdown CPU
+ *
+ */
+void rt_hw_cpu_shutdown()
+{
+    rt_uint32_t level;
+    rt_kprintf("shutdown...\n");
+
+    level = rt_hw_interrupt_disable();
+    while (level)
+    {
+        RT_ASSERT(0);
+    }
+}
+
diff --git a/libcpu/arm/zynq7000/gic.c b/libcpu/arm/zynq7000/gic.c
new file mode 100644
index 0000000000..498446db43
--- /dev/null
+++ b/libcpu/arm/zynq7000/gic.c
@@ -0,0 +1,239 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <rtthread.h>
+#include <board.h>
+
+#include "gic.h"
+#include "cp15.h"
+
+struct arm_gic
+{
+    rt_uint32_t offset;
+
+    rt_uint32_t dist_hw_base;
+    rt_uint32_t cpu_hw_base;
+};
+static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
+
+#define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00)
+#define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04)
+#define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08)
+#define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0c)
+#define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10)
+#define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14)
+#define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18)
+
+#define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000)
+#define GIC_DIST_TYPE(hw_base)               __REG32((hw_base) + 0x004)
+#define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080 + (n/32) * 4)
+#define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100 + (n/32) * 4)
+#define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180 + (n/32) * 4)
+#define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200)
+#define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280)
+#define GIC_DIST_ACTIVE_BIT(hw_base)        __REG32((hw_base) + 0x300)
+#define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400 +  (n/4) * 4)
+#define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800 +  (n/4) * 4)
+#define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00 + (n/16) * 4)
+#define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00)
+#define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10 + (n/4) * 4)
+#define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8)
+
+static unsigned int _gic_max_irq;
+
+int arm_gic_get_active_irq(rt_uint32_t index)
+{
+    int irq;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
+    irq += _gic_table[index].offset;
+    return irq;
+}
+
+void arm_gic_ack(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+    GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_mask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
+{
+    rt_uint32_t old_tgt;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
+
+    old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
+    old_tgt |=   cpumask << ((irq % 4)*8);
+
+    GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
+}
+
+void arm_gic_umask(rt_uint32_t index, int irq)
+{
+    rt_uint32_t mask = 1 << (irq % 32);
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    irq = irq - _gic_table[index].offset;
+    RT_ASSERT(irq >= 0);
+
+    GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
+}
+
+void arm_gic_dump_type(rt_uint32_t index)
+{
+    unsigned int gic_type;
+
+    gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
+    rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
+               (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
+               _gic_table[index].dist_hw_base,
+               _gic_max_irq,
+               gic_type & (1 << 10) ? "has" : "no",
+               gic_type);
+}
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
+{
+    unsigned int gic_type, i;
+    rt_uint32_t cpumask = 1 << 0;
+
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].dist_hw_base = dist_base;
+    _gic_table[index].offset = irq_start;
+
+    /* Find out how many interrupts are supported. */
+    gic_type = GIC_DIST_TYPE(dist_base);
+    _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
+
+    /*
+     * The GIC only supports up to 1020 interrupt sources.
+     * Limit this to either the architected maximum, or the
+     * platform maximum.
+     */
+    if (_gic_max_irq > 1020)
+        _gic_max_irq = 1020;
+    if (_gic_max_irq > ARM_GIC_NR_IRQS)
+        _gic_max_irq = ARM_GIC_NR_IRQS;
+
+    cpumask |= cpumask << 8;
+    cpumask |= cpumask << 16;
+
+    GIC_DIST_CTRL(dist_base) = 0x0;
+
+    /* Set all global interrupts to be level triggered, active low. */
+    for (i = 32; i < _gic_max_irq; i += 16)
+        GIC_DIST_CONFIG(dist_base, i) = 0x0;
+
+    /* Set all global interrupts to this CPU only. */
+    for (i = 32; i < _gic_max_irq; i += 4)
+        GIC_DIST_TARGET(dist_base, i) = cpumask;
+
+    /* Set priority on all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 4)
+        GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
+
+    /* Disable all interrupts. */
+    for (i = 0; i < _gic_max_irq; i += 32)
+        GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
+
+    /* Set the FIQEn bit, signal FIQ for IGROUP0. */
+    GIC_DIST_CTRL(dist_base) = 0x01;
+
+    return 0;
+}
+
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
+{
+    RT_ASSERT(index < ARM_GIC_MAX_NR);
+
+    _gic_table[index].cpu_hw_base = cpu_base;
+
+    GIC_CPU_PRIMASK(cpu_base) = 0xf0;
+    /* Enable CPU interrupt */
+    GIC_CPU_CTRL(cpu_base) = 0x01;
+
+    return 0;
+}
+
+void arm_gic_set_group(rt_uint32_t index, int vector, int group)
+{
+    /* As for GICv2, there are only group0 and group1. */
+    RT_ASSERT(group <= 1);
+    RT_ASSERT(vector < _gic_max_irq);
+
+    if (group == 0)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) &= ~(1 << (vector % 32));
+    }
+    else if (group == 1)
+    {
+        GIC_DIST_IGROUP(_gic_table[index].dist_hw_base,
+                        vector) |=  (1 << (vector % 32));
+    }
+}
+
+void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq)
+{
+    unsigned int reg;
+
+    RT_ASSERT(irq <= 15);
+    RT_ASSERT(target_cpu <= 255);
+
+    reg = (target_cpu << 16) | irq;
+    GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg;
+}
+
+void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq)
+{
+    RT_ASSERT(irq <= 15);
+    RT_ASSERT(target_cpu <= 255);
+
+    GIC_DIST_CPENDSGI(_gic_table[index].dist_hw_base, irq) = target_cpu << (irq % 4);
+}
diff --git a/libcpu/arm/zynq7000/gic.h b/libcpu/arm/zynq7000/gic.h
new file mode 100644
index 0000000000..4b89538948
--- /dev/null
+++ b/libcpu/arm/zynq7000/gic.h
@@ -0,0 +1,41 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __GIC_H__
+#define __GIC_H__
+
+int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
+int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base);
+
+void arm_gic_mask(rt_uint32_t index, int irq);
+void arm_gic_umask(rt_uint32_t index, int irq);
+void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
+void arm_gic_set_group(rt_uint32_t index, int vector, int group);
+
+int arm_gic_get_active_irq(rt_uint32_t index);
+void arm_gic_ack(rt_uint32_t index, int irq);
+
+void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq);
+void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq);
+
+void arm_gic_dump_type(rt_uint32_t index);
+
+#endif
+
diff --git a/libcpu/arm/zynq7000/interrupt.c b/libcpu/arm/zynq7000/interrupt.c
new file mode 100644
index 0000000000..ce3fbc8dfb
--- /dev/null
+++ b/libcpu/arm/zynq7000/interrupt.c
@@ -0,0 +1,143 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <rthw.h>
+#include <rtthread.h>
+#include "zynq7000.h"
+#include "cp15.h"
+#include "gic.h"
+
+#define MAX_HANDLERS                IRQ_Zynq7000_MAXNR
+
+extern volatile rt_uint8_t rt_interrupt_nest;
+
+/* exception and interrupt handler table */
+struct rt_irq_desc isr_table[MAX_HANDLERS];
+rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
+rt_uint32_t rt_thread_switch_interrupt_flag;
+
+static void rt_hw_interrupt_handle(int vector, void *param)
+{
+    rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
+}
+
+const unsigned int VECTOR_BASE = 0x00;
+extern int system_vectors;
+
+static void rt_hw_vector_init(void)
+{
+    int sctrl;
+    unsigned int *src = (unsigned int *)&system_vectors;
+
+    /* C12-C0 is only active when SCTLR.V = 0 */
+    asm volatile ("mrc p15, #0, %0, c1, c0, #0"
+                  :"=r" (sctrl));
+    sctrl &= ~(1 << 13);
+    asm volatile ("mcr p15, #0, %0, c1, c0, #0"
+                  :
+                  :"r" (sctrl));
+
+    asm volatile ("mcr p15, #0, %0, c12, c0, #0"
+                  :
+                  :"r" (src));
+}
+
+/**
+ * This function will initialize hardware interrupt
+ */
+void rt_hw_interrupt_init(void)
+{
+    register rt_uint32_t idx;
+
+    /* set vector table */
+    rt_hw_vector_init();
+
+    /* init exceptions table */
+    rt_memset(isr_table, 0x00, sizeof(isr_table));
+    for (idx = 0; idx < MAX_HANDLERS; idx++)
+    {
+        isr_table[idx].handler = rt_hw_interrupt_handle;
+    }
+
+    /* initialize ARM GIC */
+    arm_gic_dist_init(0, Zynq7000_GIC_DIST_BASE, 0);
+    arm_gic_cpu_init(0, Zynq7000_GIC_CPU_BASE);
+
+    /* init interrupt nest, and context in thread sp */
+    rt_interrupt_nest = 0;
+    rt_interrupt_from_thread = 0;
+    rt_interrupt_to_thread = 0;
+    rt_thread_switch_interrupt_flag = 0;
+}
+
+/**
+ * This function will mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_mask(int vector)
+{
+    arm_gic_mask(0, vector);
+}
+
+/**
+ * This function will un-mask a interrupt.
+ * @param vector the interrupt number
+ */
+void rt_hw_interrupt_umask(int vector)
+{
+    arm_gic_umask(0, vector);
+}
+
+/**
+ * This function will install a interrupt service routine to a interrupt.
+ * @param vector the interrupt number
+ * @param new_handler the interrupt service routine to be installed
+ * @param old_handler the old interrupt service routine
+ */
+rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
+        void *param, char *name)
+{
+    rt_isr_handler_t old_handler = RT_NULL;
+
+    if (vector < MAX_HANDLERS)
+    {
+        old_handler = isr_table[vector].handler;
+
+        if (handler != RT_NULL)
+        {
+#ifdef RT_USING_INTERRUPT_INFO
+            rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
+#endif /* RT_USING_INTERRUPT_INFO */
+            isr_table[vector].handler = handler;
+            isr_table[vector].param = param;
+        }
+        /* set the interrupt to this cpu */
+        arm_gic_set_cpu(0, vector, 1 << rt_cpu_get_smp_id());
+    }
+
+    return old_handler;
+}
+
+void rt_hw_interrupt_clear(int vector)
+{
+    /* SGI will be cleared automatically. */
+    if (vector < 16)
+        return;
+}
diff --git a/libcpu/arm/zynq7000/interrupt.h b/libcpu/arm/zynq7000/interrupt.h
new file mode 100644
index 0000000000..07eafc84e5
--- /dev/null
+++ b/libcpu/arm/zynq7000/interrupt.h
@@ -0,0 +1,26 @@
+#ifndef __INTERRUPT_H__
+#define __INTERRUPT_H__
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+void rt_hw_interrupt_clear(int vector);
+
+#endif /* end of include guard: __INTERRUPT_H__ */
+
diff --git a/libcpu/arm/zynq7000/mmu.c b/libcpu/arm/zynq7000/mmu.c
new file mode 100644
index 0000000000..2a58fabe4f
--- /dev/null
+++ b/libcpu/arm/zynq7000/mmu.c
@@ -0,0 +1,182 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+#include <board.h>
+
+#include "cp15.h"
+
+#define DESC_SEC       (0x2)
+#define CB             (3<<2)  //cache_on, write_back
+#define CNB            (2<<2)  //cache_on, write_through
+#define NCB            (1<<2)  //cache_off,WR_BUF on
+#define NCNB           (0<<2)  //cache_off,WR_BUF off
+#define AP_RW          (3<<10) //supervisor=RW, user=RW
+#define AP_RO          (2<<10) //supervisor=RW, user=RO
+#define XN             (1<<4)  //eXecute Never
+
+#define DOMAIN_FAULT   (0x0)
+#define DOMAIN_CHK     (0x1)
+#define DOMAIN_NOTCHK  (0x3)
+#define DOMAIN0        (0x0<<5)
+#define DOMAIN1        (0x1<<5)
+
+#define DOMAIN0_ATTR   (DOMAIN_CHK<<0)
+#define DOMAIN1_ATTR   (DOMAIN_FAULT<<2)
+
+/* Read/Write, cache, write back */
+#define RW_CB          (AP_RW|DOMAIN0|CB|DESC_SEC)
+/* Read/Write, cache, write through */
+#define RW_CNB         (AP_RW|DOMAIN0|CNB|DESC_SEC)
+/* Read/Write, device type */
+#define RW_NCB         (AP_RW|DOMAIN0|NCB|DESC_SEC)
+/* Read/Write strongly ordered type */
+#define RW_NCNB        (AP_RW|DOMAIN0|NCNB|DESC_SEC)
+/* Read/Write without cache and write buffer, no execute */
+#define RW_NCNBXN      (AP_RW|DOMAIN0|NCNB|DESC_SEC|XN)
+/* Read/Write without cache and write buffer */
+#define RW_FAULT       (AP_RW|DOMAIN1|NCNB|DESC_SEC)
+
+void rt_hw_cpu_dump_page_table(rt_uint32_t *ptb)
+{
+    int i;
+    int fcnt = 0;
+
+    rt_kprintf("page table@%p\n", ptb);
+    for (i = 0; i < 1024*4; i++)
+    {
+        rt_uint32_t pte1 = ptb[i];
+        if ((pte1 & 0x3) == 0)
+        {
+            rt_kprintf("%03x: ", i);
+            fcnt++;
+            if (fcnt == 16)
+            {
+                rt_kprintf("fault\n");
+                fcnt = 0;
+            }
+            continue;
+        }
+        if (fcnt != 0)
+        {
+            rt_kprintf("fault\n");
+            fcnt = 0;
+        }
+
+        rt_kprintf("%03x: %08x: ", i, pte1);
+        if ((pte1 & 0x3) == 0x3)
+        {
+            rt_kprintf("LPAE\n");
+        }
+        else if ((pte1 & 0x3) == 0x1)
+        {
+            rt_kprintf("pte,ns:%d,domain:%d\n",
+                       (pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf);
+            /*
+             *rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000)
+             *                               - 0x80000000 + 0xC0000000));
+             */
+        }
+        else if (pte1 & (1 << 18))
+        {
+            rt_kprintf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       ((pte1 >> 10) | (pte1 >> 2)) & 0x1f);
+        }
+        else
+        {
+            rt_kprintf("section,ns:%d,ap:%x,"
+                       "xn:%d,texcb:%02x,domain:%d\n",
+                       (pte1 >> 19) & 0x1,
+                       ((pte1 >> 13) | (pte1 >> 10))& 0xf,
+                       (pte1 >> 4) & 0x1,
+                       (((pte1 & (0x7 << 12)) >> 10) |
+                        ((pte1 &        0x0c) >>  2)) & 0x1f,
+                       (pte1 >> 5) & 0xf);
+        }
+    }
+}
+
+/* level1 page table, each entry for 1MB memory. */
+/* MMUTable is the name used by codes of Xilinx */
+volatile unsigned long MMUTable[4*1024] SECTION("mmu_tbl") __attribute__((aligned(16*1024)));
+void rt_hw_mmu_setmtt(rt_uint32_t vaddrStart,
+                      rt_uint32_t vaddrEnd,
+                      rt_uint32_t paddrStart,
+                      rt_uint32_t attr)
+{
+    volatile rt_uint32_t *pTT;
+    volatile int i, nSec;
+    pTT  = (rt_uint32_t *)MMUTable + (vaddrStart >> 20);
+    nSec = (vaddrEnd >> 20) - (vaddrStart >> 20);
+    for(i = 0; i <= nSec; i++)
+    {
+        *pTT = attr | (((paddrStart >> 20) + i) << 20);
+        pTT++;
+    }
+}
+
+unsigned long rt_hw_set_domain_register(unsigned long domain_val)
+{
+    unsigned long old_domain;
+
+    asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain));
+    asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory");
+
+    return old_domain;
+}
+
+void rt_hw_mmu_init(void)
+{
+    extern rt_uint32_t __text_start;
+    rt_hw_cpu_dcache_disable();
+    rt_hw_cpu_icache_disable();
+    rt_cpu_mmu_disable();
+
+    /* set page table */
+    /* no access to the memory below .text */
+    /* 128M cached DDR memory */
+    rt_hw_mmu_setmtt((rt_uint32_t)&__text_start, 0x20000000-1,
+                     0x1ff00000, RW_CB);
+    /* PL region */
+    rt_hw_mmu_setmtt(0x40000000, 0xBFFFFFFF, 0x40000000, RW_NCNBXN);
+    /* IOP registers */
+    rt_hw_mmu_setmtt(0xE0000000, 0xE02FFFFF, 0xE0000000, RW_NCNBXN);
+    /* no access to the SMC memory(enable it if you want) */
+    /* SLCR, PS and CPU private registers, note we map more memory space as the
+     * entry is 1MB in size. */
+    rt_hw_mmu_setmtt(0xF8000000, 0xF8FFFFFF, 0xF8000000, RW_NCNBXN);
+
+    /*rt_hw_cpu_dump_page_table(MMUTable);*/
+
+    /* become clients for all domains */
+    rt_hw_set_domain_register(0x55555555);
+
+    rt_cpu_tlb_set(MMUTable);
+
+    rt_cpu_mmu_enable();
+
+    rt_hw_cpu_icache_enable();
+    rt_hw_cpu_dcache_enable();
+}
+
diff --git a/libcpu/arm/zynq7000/stack.c b/libcpu/arm/zynq7000/stack.c
new file mode 100644
index 0000000000..8e1b86432e
--- /dev/null
+++ b/libcpu/arm/zynq7000/stack.c
@@ -0,0 +1,60 @@
+/*
+ * File      : stack.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-09-23     Bernard      the first version
+ * 2011-10-05     Bernard      add thumb mode
+ * 2013-07-15     Bernard      add Cortex-A8 support.
+ */
+#include <rtthread.h>
+#include "zynq7000.h"
+
+/**
+ * This function will initialize thread stack
+ *
+ * @param tentry the entry of thread
+ * @param parameter the parameter of entry
+ * @param stack_addr the beginning stack address
+ * @param texit the function will be called when thread exit
+ *
+ * @return stack address
+ */
+rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter,
+                             rt_uint8_t *stack_addr, void *texit)
+{
+    rt_uint32_t *stk;
+
+    stk      = (rt_uint32_t *)stack_addr;
+    *(stk)   = (rt_uint32_t)tentry;         /* entry point */
+    *(--stk) = (rt_uint32_t)texit;          /* lr */
+    *(--stk) = 0;                           /* r12 */
+    *(--stk) = 0;                           /* r11 */
+    *(--stk) = 0;                           /* r10 */
+    *(--stk) = 0;                           /* r9 */
+    *(--stk) = 0;                           /* r8 */
+    *(--stk) = 0;                           /* r7 */
+    *(--stk) = 0;                           /* r6 */
+    *(--stk) = 0;                           /* r5 */
+    *(--stk) = 0;                           /* r4 */
+    *(--stk) = 0;                           /* r3 */
+    *(--stk) = 0;                           /* r2 */
+    *(--stk) = 0;                           /* r1 */
+    *(--stk) = (rt_uint32_t)parameter;      /* r0 : argument */
+
+    /* cpsr */
+    if ((rt_uint32_t)tentry & 0x01)
+        *(--stk) = SVCMODE | 0x20;          /* thumb mode */
+    else
+        *(--stk) = SVCMODE;                 /* arm mode   */
+
+    /* return task's current stack address */
+    return (rt_uint8_t *)stk;
+}
+
diff --git a/libcpu/arm/zynq7000/start_gcc.S b/libcpu/arm/zynq7000/start_gcc.S
new file mode 100644
index 0000000000..41a7906b00
--- /dev/null
+++ b/libcpu/arm/zynq7000/start_gcc.S
@@ -0,0 +1,254 @@
+/*
+ * File      : start_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.equ Mode_USR,        0x10
+.equ Mode_FIQ,        0x11
+.equ Mode_IRQ,        0x12
+.equ Mode_SVC,        0x13
+.equ Mode_ABT,        0x17
+.equ Mode_UND,        0x1B
+.equ Mode_SYS,        0x1F
+
+.equ I_Bit,           0x80            @ when I bit is set, IRQ is disabled
+.equ F_Bit,           0x40            @ when F bit is set, FIQ is disabled
+
+.equ UND_Stack_Size,  0x00000000
+.equ SVC_Stack_Size,  0x00000000
+.equ ABT_Stack_Size,  0x00000000
+.equ FIQ_Stack_Size,  0x00000100
+.equ IRQ_Stack_Size,  0x00000100
+.equ USR_Stack_Size,  0x00000000
+
+#define ISR_Stack_Size  (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
+                 FIQ_Stack_Size + IRQ_Stack_Size)
+
+/* stack */
+.globl stack_start
+.globl stack_top
+
+.bss
+stack_start:
+.rept ISR_Stack_Size
+.long 0
+.endr
+stack_top:
+
+.text
+/* reset entry */
+.globl _reset
+_reset:
+	/* invalidate SCU */
+	ldr	r7, =0xF8F0000C
+	ldr	r6, =0xFFFF
+	str	r6, [r7]
+
+	/* disable MMU */
+	mrc	p15, 0, r0, c1, c0, 0		/* read CP15 register 1 */
+	bic	r0, r0, #0x1				/* clear bit 0 */
+	mcr	p15, 0, r0, c1, c0, 0		/* write value back */
+
+    /* set the cpu to SVC32 mode and disable interrupt */
+    mrs     r0, cpsr
+    bic     r0, r0, #0x1f
+    orr     r0, r0, #0x13
+    msr     cpsr_c, r0
+
+    /* setup stack */
+    bl      stack_setup
+
+    /* clear .bss */
+    mov     r0,#0                   /* get a zero                       */
+    ldr     r1,=__bss_start         /* bss start                        */
+    ldr     r2,=__bss_end           /* bss end                          */
+
+bss_loop:
+    cmp     r1,r2                   /* check if data to clear           */
+    strlo   r0,[r1],#4              /* clear 4 bytes                    */
+    blo     bss_loop                /* loop until done                  */
+
+    /* call C++ constructors of global objects                          */
+    ldr     r0, =__ctors_start__
+    ldr     r1, =__ctors_end__
+
+ctor_loop:
+    cmp     r0, r1
+    beq     ctor_end
+    ldr     r2, [r0], #4
+    stmfd   sp!, {r0-r1}
+    mov     lr, pc
+    bx      r2
+    ldmfd   sp!, {r0-r1}
+    b       ctor_loop
+ctor_end:
+
+    /* start RT-Thread Kernel       */
+    ldr     pc, _rtthread_startup
+
+_rtthread_startup:
+    .word rtthread_startup
+
+stack_setup:
+    ldr     r0, =stack_top
+
+    @  Set the startup stack for svc
+    mov     sp, r0
+
+    @  Enter Undefined Instruction Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_UND|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #UND_Stack_Size
+
+    @  Enter Abort Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_ABT|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #ABT_Stack_Size
+
+    @  Enter FIQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_FIQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #FIQ_Stack_Size
+
+    @  Enter IRQ Mode and set its Stack Pointer
+    msr     cpsr_c, #Mode_IRQ|I_Bit|F_Bit
+    mov     sp, r0
+    sub     r0, r0, #IRQ_Stack_Size
+
+    @  Switch back to SVC
+    msr     cpsr_c, #Mode_SVC|I_Bit|F_Bit
+
+    bx      lr
+
+.section .text.isr, "ax"
+/* exception handlers: undef, swi, padt, dabt, resv, irq, fiq          */
+    .align  5
+.globl vector_fiq
+vector_fiq:
+    stmfd   sp!,{r0-r7,lr}
+    bl      rt_hw_trap_fiq
+    ldmfd   sp!,{r0-r7,lr}
+    subs    pc,lr,#4
+
+.globl      rt_interrupt_enter
+.globl      rt_interrupt_leave
+.globl      rt_thread_switch_interrupt_flag
+.globl      rt_interrupt_from_thread
+.globl      rt_interrupt_to_thread
+
+    .align  5
+.globl vector_irq
+vector_irq:
+    stmfd   sp!, {r0-r12,lr}
+    bl      rt_interrupt_enter
+    bl      rt_hw_trap_irq
+    bl      rt_interrupt_leave
+
+    @ if rt_thread_switch_interrupt_flag set, jump to
+    @ rt_hw_context_switch_interrupt_do and don't return
+    ldr     r0, =rt_thread_switch_interrupt_flag
+    ldr     r1, [r0]
+    cmp     r1, #1
+    beq rt_hw_context_switch_interrupt_do
+
+    ldmfd   sp!, {r0-r12,lr}
+    subs    pc, lr, #4
+
+rt_hw_context_switch_interrupt_do:
+    mov     r1,  #0         @ clear flag
+    str     r1,  [r0]
+
+    mov     r1, sp          @ r1 point to {r0-r3} in stack
+    add     sp, sp, #4*4
+    ldmfd   sp!, {r4-r12,lr}@ reload saved registers
+    mrs     r0,  spsr       @ get cpsr of interrupt thread
+    sub     r2,  lr, #4     @ save old task's pc to r2
+
+    @ Switch to SVC mode with no interrupt.
+    msr     cpsr_c, #I_Bit|F_Bit|Mode_SVC
+
+    stmfd   sp!, {r2}       @ push old task's pc
+    stmfd   sp!, {r4-r12,lr}@ push old task's lr,r12-r4
+    ldmfd   r1,  {r1-r4}    @ restore r0-r3 of the interrupt thread
+    stmfd   sp!, {r1-r4}    @ push old task's r0-r3
+    stmfd   sp!, {r0}       @ push old task's cpsr
+
+    ldr     r4,  =rt_interrupt_from_thread
+    ldr     r5,  [r4]
+    str     sp,  [r5]       @ store sp in preempted tasks's TCB
+
+    ldr     r6,  =rt_interrupt_to_thread
+    ldr     r7,  [r6]
+    ldr     sp,  [r7]       @ get new task's stack pointer
+
+    ldmfd   sp!, {r4}       @ pop new task's cpsr to spsr
+    msr     spsr_cxsf, r4
+
+    ldmfd   sp!, {r0-r12,lr,pc}^ @ pop new task's r0-r12,lr & pc, copy spsr to cpsr
+
+
+.macro push_svc_reg
+    sub     sp, sp, #17 * 4         @/* Sizeof(struct rt_hw_exp_stack)  */
+    stmia   sp, {r0 - r12}          @/* Calling r0-r12                  */
+    mov     r0, sp
+    mrs     r6, spsr                @/* Save CPSR                       */
+    str     lr, [r0, #15*4]         @/* Push PC                         */
+    str     r6, [r0, #16*4]         @/* Push CPSR                       */
+    cps     #Mode_SVC
+    str     sp, [r0, #13*4]         @/* Save calling SP                 */
+    str     lr, [r0, #14*4]         @/* Save calling PC                 */
+.endm
+
+    .align  5
+    .globl	vector_swi
+vector_swi:
+    push_svc_reg
+    bl      rt_hw_trap_swi
+    b       .
+
+    .align  5
+    .globl	vector_undef
+vector_undef:
+    push_svc_reg
+    bl      rt_hw_trap_undef
+    b       .
+
+    .align  5
+    .globl	vector_pabt
+vector_pabt:
+    push_svc_reg
+    bl      rt_hw_trap_pabt
+    b       .
+
+    .align  5
+    .globl	vector_dabt
+vector_dabt:
+    push_svc_reg
+    bl      rt_hw_trap_dabt
+    b       .
+
+    .align  5
+    .globl	vector_resv
+vector_resv:
+    push_svc_reg
+    bl      rt_hw_trap_resv
+    b       .
diff --git a/libcpu/arm/zynq7000/trap.c b/libcpu/arm/zynq7000/trap.c
new file mode 100644
index 0000000000..9bf58f916c
--- /dev/null
+++ b/libcpu/arm/zynq7000/trap.c
@@ -0,0 +1,185 @@
+/*
+ * COPYRIGHT (C) 2013-2014, Shanghai Real-Thread Technology Co., Ltd
+ *
+ *  All rights reserved.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <rtthread.h>
+#include <rthw.h>
+
+#include "zynq7000.h"
+#include "gic.h"
+
+extern struct rt_thread *rt_current_thread;
+#ifdef RT_USING_FINSH
+extern long list_thread(void);
+#endif
+
+/**
+ * this function will show registers of CPU
+ *
+ * @param regs the registers point
+ */
+void rt_hw_show_register (struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("Execption:\n");
+    rt_kprintf("r00:0x%08x r01:0x%08x r02:0x%08x r03:0x%08x\n", regs->r0, regs->r1, regs->r2, regs->r3);
+    rt_kprintf("r04:0x%08x r05:0x%08x r06:0x%08x r07:0x%08x\n", regs->r4, regs->r5, regs->r6, regs->r7);
+    rt_kprintf("r08:0x%08x r09:0x%08x r10:0x%08x\n", regs->r8, regs->r9, regs->r10);
+    rt_kprintf("fp :0x%08x ip :0x%08x\n", regs->fp, regs->ip);
+    rt_kprintf("sp :0x%08x lr :0x%08x pc :0x%08x\n", regs->sp, regs->lr, regs->pc);
+    rt_kprintf("cpsr:0x%08x\n", regs->cpsr);
+}
+
+/**
+ * When comes across an instruction which it cannot handle,
+ * it takes the undefined instruction trap.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_undef(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("undefined instruction:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * The software interrupt instruction (SWI) is used for entering
+ * Supervisor mode, usually to request a particular supervisor
+ * function.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_swi(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("software interrupt:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during an instruction prefetch.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_pabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("prefetch abort:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * An abort indicates that the current memory access cannot be completed,
+ * which occurs during a data access.
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_dabt(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("data abort:");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+/**
+ * Normally, system will never reach here
+ *
+ * @param regs system registers
+ *
+ * @note never invoke this function in application
+ */
+void rt_hw_trap_resv(struct rt_hw_exp_stack *regs)
+{
+    rt_kprintf("reserved trap:\n");
+    rt_hw_show_register(regs);
+#ifdef RT_USING_FINSH
+    list_thread();
+#endif
+    rt_hw_cpu_shutdown();
+}
+
+#define GIC_ACK_INTID_MASK					0x000003ff
+
+void rt_hw_trap_irq()
+{
+    void *param;
+    unsigned long ir;
+    unsigned long fullir;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    fullir = arm_gic_get_active_irq(0);
+    ir = fullir & GIC_ACK_INTID_MASK;
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+    if (isr_func)
+    {
+        param = isr_table[ir].param;
+        /* turn to interrupt service routine */
+        isr_func(ir, param);
+    }
+
+    /* end of interrupt */
+    arm_gic_ack(0, fullir);
+}
+
+void rt_hw_trap_fiq()
+{
+    void *param;
+    unsigned long ir;
+    unsigned long fullir;
+    rt_isr_handler_t isr_func;
+    extern struct rt_irq_desc isr_table[];
+
+    fullir = arm_gic_get_active_irq(0);
+    ir = fullir & GIC_ACK_INTID_MASK;
+
+    /* get interrupt service routine */
+    isr_func = isr_table[ir].handler;
+    param = isr_table[ir].param;
+
+    /* turn to interrupt service routine */
+    isr_func(ir, param);
+
+    /* end of interrupt */
+    arm_gic_ack(0, fullir);
+}
+
diff --git a/libcpu/arm/zynq7000/vector_gcc.S b/libcpu/arm/zynq7000/vector_gcc.S
new file mode 100644
index 0000000000..4a44a7395c
--- /dev/null
+++ b/libcpu/arm/zynq7000/vector_gcc.S
@@ -0,0 +1,65 @@
+/*
+ * File      : vector_gcc.S
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2013, RT-Thread Development Team
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2013-07-05     Bernard      the first version
+ */
+
+.section .vectors, "ax"
+.code 32
+
+.globl system_vectors
+system_vectors:
+    ldr pc, _vector_reset
+    ldr pc, _vector_undef
+    ldr pc, _vector_swi
+    ldr pc, _vector_pabt
+    ldr pc, _vector_dabt
+    ldr pc, _vector_resv
+    ldr pc, _vector_irq
+    ldr pc, _vector_fiq
+
+.globl _reset
+.globl vector_undef
+.globl vector_swi
+.globl vector_pabt
+.globl vector_dabt
+.globl vector_resv
+.globl vector_irq
+.globl vector_fiq
+
+_vector_reset:
+    .word _reset
+_vector_undef:
+    .word vector_undef
+_vector_swi:
+    .word vector_swi
+_vector_pabt:
+    .word vector_pabt
+_vector_dabt:
+    .word vector_dabt
+_vector_resv:
+    .word vector_resv
+_vector_irq:
+    .word vector_irq
+_vector_fiq:
+    .word vector_fiq
+
+.balignl 	16,0xdeadbeef
diff --git a/libcpu/mips/jz47xx/cache.c b/libcpu/mips/jz47xx/cache.c
deleted file mode 100644
index 8a502cdb12..0000000000
--- a/libcpu/mips/jz47xx/cache.c
+++ /dev/null
@@ -1,93 +0,0 @@
-#include "jz47xx.h"
-#include "cache.h"
-
-#define CACHE_SIZE		16*1024
-#define CACHE_LINE_SIZE		32
-#define KSEG0			0x80000000
-
-
-#define K0_TO_K1()				\
-do {						\
-	unsigned long __k0_addr;		\
-						\
-	__asm__ __volatile__(			\
-	"la %0, 1f\n\t"				\
-	"or	%0, %0, %1\n\t"			\
-	"jr	%0\n\t"				\
-	"nop\n\t"				\
-	"1: nop\n"				\
-	: "=&r"(__k0_addr)			\
-	: "r" (0x20000000) );			\
-} while(0)
-
-#define K1_TO_K0()				\
-do {						\
-	unsigned long __k0_addr;		\
-	__asm__ __volatile__(			\
-	"nop;nop;nop;nop;nop;nop;nop\n\t"	\
-	"la %0, 1f\n\t"				\
-	"jr	%0\n\t"				\
-	"nop\n\t"				\
-	"1:	nop\n"				\
-	: "=&r" (__k0_addr));			\
-} while (0)
-
-#define INVALIDATE_BTB()			\
-do {						\
-	unsigned long tmp;			\
-	__asm__ __volatile__(			\
-	".set mips32\n\t"			\
-	"mfc0 %0, $16, 7\n\t"			\
-	"nop\n\t"				\
-	"ori %0, 2\n\t"				\
-	"mtc0 %0, $16, 7\n\t"			\
-	"nop\n\t"				\
-	".set mips2\n\t"			\
-	: "=&r" (tmp));				\
-} while (0)
-
-#define SYNC_WB() __asm__ __volatile__ ("sync")
-
-#define cache_op(op,addr)						\
-	__asm__ __volatile__(						\
-	"	.set	noreorder		\n"			\
-	"	.set	mips32\n\t		\n"			\
-	"	cache	%0, %1			\n"			\
-	"	.set	mips0			\n"			\
-	"	.set	reorder"					\
-	:										\
-	: "i" (op), "m" (*(unsigned char *)(addr)))
-
-void __icache_invalidate_all(void)
-{
-	unsigned int i;
-
-	K0_TO_K1();
-
-	asm volatile (".set noreorder\n"
-		      ".set mips32\n\t"
-		      "mtc0\t$0,$28\n\t"
-		      "mtc0\t$0,$29\n"
-		      ".set mips0\n"
-		      ".set reorder\n");
-	for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
-		cache_op(Index_Store_Tag_I, i);
-
-	K1_TO_K0();
-
-	INVALIDATE_BTB();
-}
-
-void __dcache_writeback_all(void)
-{
-	unsigned int i;
-	for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
-		cache_op(Index_Writeback_Inv_D, i);
-	SYNC_WB();
-}
-
-void rt_hw_cache_init(void)
-{
-	__dcache_writeback_all();
-	__icache_invalidate_all();
-}
diff --git a/libcpu/mips/jz47xx/cache.h b/libcpu/mips/jz47xx/cache.h
deleted file mode 100644
index d1f3e25493..0000000000
--- a/libcpu/mips/jz47xx/cache.h
+++ /dev/null
@@ -1,40 +0,0 @@
-#ifndef	__CACHE_H__
-#define	__CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I		0x04
-#define Index_Load_Tag_D		0x05
-#define Index_Load_Tag_SI		0x06
-#define Index_Load_Tag_SD		0x07
-#define Index_Store_Tag_I		0x08
-#define Index_Store_Tag_D		0x09
-#define Index_Store_Tag_SI		0x0A
-#define Index_Store_Tag_SD		0x0B
-#define Create_Dirty_Excl_D		0x0d
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_I		0x10
-#define Hit_Invalidate_D		0x11
-#define Hit_Invalidate_SI		0x12
-#define Hit_Invalidate_SD		0x13
-#define Fill					0x14
-#define Hit_Writeback_Inv_D		0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_I			0x18
-#define Hit_Writeback_D			0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD		0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI		0x1e
-#define Hit_Set_Virtual_SD		0x1f
-
-void rt_hw_cache_init(void);
-
-#endif
diff --git a/libcpu/mips/jz47xx/cache_gcc.S b/libcpu/mips/jz47xx/cache_gcc.S
deleted file mode 100644
index 76552698d0..0000000000
--- a/libcpu/mips/jz47xx/cache_gcc.S
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * File      : cache_init.S
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- */
-#include "../common/mips.inc"
-#include "../common/mipsregs.h"
-#include "../common/stackframe.h"
-
-    .text
-    .set noreorder
-
-    .globl  cache_init
-    .ent    cache_init
-cache_init:
-    .set    noreorder
-    mtc0    zero, CP0_TAGLO
-    move    t0, a0                  // cache total size
-    move    t1, a1                  // cache line size
-    li      t2, 0x80000000
-    addu    t3, t0, t2
-
-_cache_init_loop:
-    cache   8, 0(t2)                // icache_index_store_tag
-    cache   9, 0(t2)                // dcache_index_store_tag
-    addu    t2, t1
-    bne     t2, t3, _cache_init_loop
-    nop
-
-    mfc0    t0, CP0_CONFIG
-    li      t1, 0x7
-    not     t1
-    and     t0, t0, t1
-    or      t0, 0x3                 // cacheable, noncoherent, write-back, write allocate
-    mtc0    t0, CP0_CONFIG
-
-    jr      ra
-    nop
-
-    .set    reorder
-    .end    cache_init
diff --git a/libcpu/mips/jz47xx/context_gcc.S b/libcpu/mips/jz47xx/context_gcc.S
deleted file mode 100644
index b480a10219..0000000000
--- a/libcpu/mips/jz47xx/context_gcc.S
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * File      : context_gcc.S
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to Jz4755
- */
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-#include "jz47xx.h"
-
-    .section ".text", "ax"
-    .set noreorder
-
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
-    .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mfc0    v0, CP0_STATUS
-    and     v1, v0, 0xfffffffe
-    mtc0    v1, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
-    .globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    mtc0    a0, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
- * a0 --> from
- * a1 --> to
- */
-    .globl rt_hw_context_switch
-rt_hw_context_switch:
-    mtc0    ra, CP0_EPC
-    SAVE_ALL
-
-    sw      sp, 0(a0)       /* store sp in preempted tasks TCB */
-    lw      sp, 0(a1)       /* get new task stack pointer */
-
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * a0 --> to
- */
-    .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    lw      sp, 0(a0)       /* get new task stack pointer */
-
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
- */
-    .globl rt_thread_switch_interrupt_flag
-    .globl rt_interrupt_from_thread
-    .globl rt_interrupt_to_thread
-    .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-    la      t0, rt_thread_switch_interrupt_flag
-    lw      t1, 0(t0)
-    nop
-    bnez    t1, _reswitch
-    nop
-    li      t1, 0x01                       /* set rt_thread_switch_interrupt_flag to 1 */
-    sw      t1, 0(t0)
-    la      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
-    sw      a0, 0(t0)
-_reswitch:
-    la      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
-    sw      a1, 0(t0)
-    jr      ra
-    nop
-
-	.globl system_dump
-
-/*
- * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
- */
-    .globl rt_interrupt_enter
-    .globl rt_interrupt_leave
-    .globl mips_irq_handle
-mips_irq_handle:
-    SAVE_ALL
-
-    mfc0    t0, CP0_CAUSE
-    mfc0    t1, CP0_STATUS
-    and     t0, t1
-
-    andi    t0, 0xff00
-    beqz    t0, spurious_interrupt
-    nop
-
-	/* let k0 keep the current context sp */
-    move    k0, sp 
-    /* switch to kernel stack */
-    li      sp, SYSTEM_STACK
-
-    jal     rt_interrupt_enter
-    nop
-    jal     rt_interrupt_dispatch
-    nop
-    jal     rt_interrupt_leave
-    nop
-
-    /* switch sp back to thread's context */
-    move    sp, k0
-
-    /*
-     * if rt_thread_switch_interrupt_flag set, jump to
-     * rt_hw_context_switch_interrupt_do and don't return
-     */
-    la      k0, rt_thread_switch_interrupt_flag
-    lw      k1, 0(k0)
-    beqz    k1, spurious_interrupt
-    nop
-    sw      zero, 0(k0)                     /* clear flag */
-	nop
-
-    /*
-     * switch to the new thread
-     */
-    la      k0, rt_interrupt_from_thread
-    lw      k1, 0(k0)
-    nop
-    sw      sp, 0(k1)                       /* store sp in preempted tasks's TCB */
-
-    la      k0, rt_interrupt_to_thread
-    lw      k1, 0(k0)
-    nop
-    lw      sp, 0(k1)                       /* get new task's stack pointer */
-    j       spurious_interrupt
-    nop
-
-spurious_interrupt:
-    RESTORE_ALL_AND_RET
-
-    .set reorder
diff --git a/libcpu/mips/jz47xx/cpu.c b/libcpu/mips/jz47xx/cpu.c
deleted file mode 100644
index f44a44e020..0000000000
--- a/libcpu/mips/jz47xx/cpu.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2010-09-11     Bernard      add CPU reset implementation
- */
-#include <rtthread.h>
-#include <jz4755.h>
-
-/* Watchdog definitions */
-#define	WDT_CLK_PRESCALE_CLK1			( 0x0 << 3)
-#define	WDT_CLK_PRESCALE_CLK4			( 0x1 << 3)
-#define	WDT_CLK_PRESCALE_CLK16			( 0x2 << 3)
-#define	WDT_CLK_PRESCALE_CLK64			( 0x3 << 3)
-#define	WDT_CLK_PRESCALE_CLK256			( 0x4 << 3)
-#define	WDT_CLK_PRESCALE_CLK1024		( 0x5 << 3)
-#define	WDT_CLK_PRESCALE_MASK			( 0x3F << 3)
-
-#define	WDT_CLK_EXTAL					( 0x1 << 2)
-#define	WDT_CLK_RTC						( 0x1 << 1)
-#define	WDT_CLK_PCLK					( 0x1 << 0)
-#define	WDT_CLK_MASK					( 7 )
-
-#define	WDT_ENABLE			( 1 << 0 )
-
-/**
- * @addtogroup Jz47xx
- */
-/*@{*/
-
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset()
-{
-	/* open the watch-dog */
-	WDT_TCSR = WDT_CLK_EXTAL;
-	WDT_TCSR |= WDT_CLK_PRESCALE_CLK1024;
-	WDT_TDR  = 0x03;
-	WDT_TCNT = 0x00;
-	WDT_TCER |= WDT_ENABLE;
-
-	rt_kprintf("reboot system...\n");
-	while (1);
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown()
-{
-	rt_kprintf("shutdown...\n");
-
-	while (1);
-}
-
-/*@}*/
-
diff --git a/libcpu/mips/jz47xx/exception.c b/libcpu/mips/jz47xx/exception.c
deleted file mode 100644
index 6d47d3ca4e..0000000000
--- a/libcpu/mips/jz47xx/exception.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * File      : exception.c
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- */
-#include <rtthread.h>
-#include <rthw.h>
-#include "../common/exception.h"
-#include "../common/mipsregs.h"
-
-/**
- * @addtogroup Jz47xx
- */
-/*@{*/
-
-/**
- * exception handle table
- */
-exception_func_t sys_exception_handlers[33];
-
-/**
- * setup the exception handle
- */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
-    exception_func_t old_handler = sys_exception_handlers[n];
-
-    if ((n == 0) || (n > 32) || (!func))
-    {
-        return 0;
-    }
-
-    sys_exception_handlers[n] = func;
-
-    return old_handler;
-}
-
-void tlb_refill_handler(void)
-{
-	rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-void cache_error_handler(void)
-{
-	rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-static void unhandled_exception_handle(pt_regs_t *regs)
-{
-	rt_kprintf("exception happens, epc: 0x%08x\n", regs->cp0_epc);
-}
-
-void install_default_execpt_handle(void)
-{
-	rt_int32_t i;
-
-	for (i=0; i<33; i++)
-		sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-}
-
-/*@}*/
-
diff --git a/libcpu/mips/jz47xx/interrupt.c b/libcpu/mips/jz47xx/interrupt.c
deleted file mode 100644
index 0ea4827ee2..0000000000
--- a/libcpu/mips/jz47xx/interrupt.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- */
-#include <rthw.h>
-#include "jz47xx.h"
-
-#define JZ47XX_MAX_INTR 32
-
-extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-static struct rt_irq_desc irq_handle_table[JZ47XX_MAX_INTR];
-
-/**
- * @addtogroup Jz47xx
- */
-/*@{*/
-
-void rt_hw_interrupt_handler(int vector)
-{
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init()
-{
-	rt_int32_t index;
-
-    rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
-	for (index = 0; index < JZ47XX_MAX_INTR; index ++)
-	{
-		irq_handle_table[index].handler = (rt_isr_handler_t)rt_hw_interrupt_handler;
-	}
-
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-	/* mask interrupt */
-	INTC_IMSR = (1 << vector);
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-	INTC_IMCR = (1 << vector);
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param handler the interrupt service routine to be installed
- * @param param the interrupt service function parameter
- * @param name the interrupt name
- * @return old handler
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector,
-                             rt_isr_handler_t  handler,
-                             void *param,
-                             char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-	if (vector >= 0 && vector < JZ47XX_MAX_INTR)
-	{
-        old_handler = irq_handle_table[vector].handler;
-
-#ifdef RT_USING_INTERRUPT_INFO
-        rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-        irq_handle_table[vector].handler = handler;
-        irq_handle_table[vector].param = param;
-	}
-
-    return old_handler;
-}
-
-void rt_interrupt_dispatch(void *ptreg)
-{
-    int i;
-	rt_isr_handler_t irq_func;
-	static rt_uint32_t pending = 0;
-
-    /* the hardware interrupt */
-	pending |= INTC_IPR;
-	if (!pending) return;
-
-    for (i = JZ47XX_MAX_INTR; i > 0; --i)
-    {
-		if ((pending & (1<<i)))
-        {
-			pending &= ~(1<<i);
-			irq_func = irq_handle_table[i].handler;
-
-			/* do interrupt */
-			(*irq_func)(i, irq_handle_table[i].param);
-
-#ifdef RT_USING_INTERRUPT_INFO
-			irq_handle_table[i].counter++;
-#endif /* RT_USING_INTERRUPT_INFO */
-
-			/* ack interrupt */
-			INTC_IPR = (1 << i);
-		}
-	}
-}
-
-/*@}*/
diff --git a/libcpu/mips/jz47xx/jz4740.h b/libcpu/mips/jz47xx/jz4740.h
deleted file mode 100644
index a6fdd34c83..0000000000
--- a/libcpu/mips/jz47xx/jz4740.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef __JZ4740_H__
-#define __JZ4740_H__
-
-#include "jz47xx.h"
-
-#define	WDT_BASE	0xB0002000
-
-/* Watchdog */
-#define WDT_TDR		__REG16(WDT_BASE + 0x00)	/* Watchdog Timer Data Register */
-#define WDT_TCER	__REG8(WDT_BASE + 0x04)		/* Watchdog Counter Enable Register */
-#define WDT_TCNT	__REG16(WDT_BASE + 0x08)	/* Watchdog Timer Counter Register */
-#define WDT_TCSR	__REG16(WDT_BASE + 0x0C)	/* Watchdog Timer Control Register */
-
-/* Clock Gate Register Definitions */
-#define CPM_CLKGR_UART1   (1 << 15)
-#define CPM_CLKGR_UHC     (1 << 14)
-#define CPM_CLKGR_IPU     (1 << 13)
-#define CPM_CLKGR_DMAC    (1 << 12)
-#define CPM_CLKGR_UDC     (1 << 11)
-#define CPM_CLKGR_LCD     (1 << 10)
-#define CPM_CLKGR_CIM     (1 << 9)
-#define CPM_CLKGR_SADC    (1 << 8)
-#define CPM_CLKGR_MSC     (1 << 7)
-#define CPM_CLKGR_AIC1    (1 << 6)
-#define CPM_CLKGR_AIC2    (1 << 5)
-#define CPM_CLKGR_SSI     (1 << 4)
-#define CPM_CLKGR_I2C     (1 << 3)
-#define CPM_CLKGR_RTC     (1 << 2)
-#define CPM_CLKGR_TCU     (1 << 1)
-#define CPM_CLKGR_UART0   (1 << 0)
-
-/* Interrupt Definitions */
-#define IRQ_I2C		1
-#define IRQ_UHC		3
-#define IRQ_UART0	9
-#define IRQ_SADC	12
-#define IRQ_MSC		14
-#define IRQ_RTC		15
-#define IRQ_SSI		16
-#define IRQ_CIM		17
-#define IRQ_AIC		18
-#define IRQ_ETH		19
-#define IRQ_DMAC	20
-#define IRQ_TCU2	21
-#define IRQ_TCU1	22
-#define IRQ_TCU0	23
-#define IRQ_UDC		24
-#define IRQ_GPIO3	25
-#define IRQ_GPIO2	26
-#define IRQ_GPIO1	27
-#define IRQ_GPIO0	28
-#define IRQ_IPU		29
-#define IRQ_LCD		30
-
-#endif
diff --git a/libcpu/mips/jz47xx/jz4755.h b/libcpu/mips/jz47xx/jz4755.h
deleted file mode 100644
index 847f657f4e..0000000000
--- a/libcpu/mips/jz47xx/jz4755.h
+++ /dev/null
@@ -1,83 +0,0 @@
-#ifndef __JZ4755_H__
-#define __JZ4755_H__
-
-#include "jz47xx.h"
-
-#define	WDT_BASE	0xB0002000
-#define	OST_BASE	0xB00020e0
-
-/* Watchdog */
-#define WDT_TDR		__REG16(WDT_BASE + 0x00)	/* Watchdog Timer Data Register */
-#define WDT_TCER	__REG8(WDT_BASE + 0x04)		/* Watchdog Counter Enable Register */
-#define WDT_TCNT	__REG16(WDT_BASE + 0x08)	/* Watchdog Timer Counter Register */
-#define WDT_TCSR	__REG16(WDT_BASE + 0x0C)	/* Watchdog Timer Control Register */
-
-/* OS Timer */
-#define OST_DR		__REG32(OST_BASE + 0x00)	/* OS Timer Data Register */
-#define OST_CNT		__REG32(OST_BASE + 0x08)	/* OS Timer Counter Register */
-#define OST_CSR		__REG16(OST_BASE + 0x0C)	/* OS Timer Control Register */
-
-/* OST Register Definitions */
-#define OST_TCSR_EXT_EN		( 0x1 << 2)
-#define OST_TCSR_RTC_EN		( 0x1 << 1)
-#define OST_TCSR_PCLK_EN	( 0x1 << 0)
-
-/* Clock Gate Register Definitions */
-#define CPM_CLKGR_AUX_CPU      ( 1 << 24 )
-#define CPM_CLKGR_AHB1         ( 1 << 23 )
-#define CPM_CLKGR_IDCT         ( 1 << 22 )
-#define CPM_CLKGR_DB           ( 1 << 21 )
-#define CPM_CLKGR_ME           ( 1 << 20 )
-#define CPM_CLKGR_MC           ( 1 << 19 )
-#define CPM_CLKGR_TVE          ( 1 << 18 )
-#define CPM_CLKGR_TSSI         ( 1 << 17 )
-#define CPM_CLKGR_MSC1         ( 1 << 16 )
-#define CPM_CLKGR_UART2        ( 1 << 15 )
-#define CPM_CLKGR_UART1        ( 1 << 14 )
-#define CPM_CLKGR_IPU          ( 1 << 13 )
-#define CPM_CLKGR_DMAC         ( 1 << 12 )
-#define CPM_CLKGR_BCH          ( 1 << 11 )
-#define CPM_CLKGR_UDC          ( 1 << 10 )
-#define CPM_CLKGR_LCD          ( 1 << 9 )
-#define CPM_CLKGR_CIM          ( 1 << 8 )
-#define CPM_CLKGR_SADC         ( 1 << 7 )
-#define CPM_CLKGR_MSC0         ( 1 << 6 )
-#define CPM_CLKGR_AIC          ( 1 << 5 )
-#define CPM_CLKGR_SSI1         ( 1 << 4 )
-#define CPM_CLKGR_I2C          ( 1 << 3 )
-#define CPM_CLKGR_RTC          ( 1 << 2 )
-#define CPM_CLKGR_TCU          ( 1 << 1 )
-#define CPM_CLKGR_UART0        ( 1 << 0 )
-
-/* Interrupt Definitions */
-#define IRQ_ETH		0
-#define IRQ_SFT		4
-#define IRQ_I2C		5
-#define IRQ_RTC		6
-#define IRQ_UART2	7
-#define IRQ_UART1	8
-#define IRQ_UART0	9
-#define IRQ_AIC		10
-#define IRQ_GPIO5	11
-#define IRQ_GPIO4	12
-#define IRQ_GPIO3	13
-#define IRQ_GPIO2	14
-#define IRQ_GPIO1	15
-#define IRQ_GPIO0	16
-#define IRQ_BCH		17
-#define IRQ_SADC	18
-#define IRQ_CIM		19
-#define IRQ_TSSI	20
-#define IRQ_TCU2	21
-#define IRQ_TCU1	22
-#define IRQ_TCU0	23
-#define IRQ_MSC1	24
-#define IRQ_MSC0	25
-#define IRQ_SSI		26
-#define IRQ_UDC		27
-#define IRQ_DMA1	28		/* Used for DMA channel 4-7 */
-#define IRQ_DMA0	29		/* Used for DMA channel 0-3 */
-#define IRQ_IPU		30
-#define IRQ_LCD		31
-
-#endif
diff --git a/libcpu/mips/jz47xx/jz47xx.h b/libcpu/mips/jz47xx/jz47xx.h
deleted file mode 100644
index 3d1b7cee1f..0000000000
--- a/libcpu/mips/jz47xx/jz47xx.h
+++ /dev/null
@@ -1,263 +0,0 @@
-#ifndef __JZ47XX_H__
-#define __JZ47XX_H__
-
-#include "../common/mipsregs.h"
-
-#define __REG8(addr)	*((volatile unsigned char *)(addr))
-#define __REG16(addr)	*((volatile unsigned short *)(addr))
-#define __REG32(addr)	*((volatile unsigned int *)(addr))
-
-#define	HARB_BASE	0xB3000000
-#define	EMC_BASE	0xB3010000
-#define	DMAC_BASE	0xB3020000
-#define	UHC_BASE	0xB3030000
-#define	UDC_BASE	0xB3040000
-#define	LCD_BASE	0xB3050000
-#define	CIM_BASE	0xB3060000
-#define	ETH_BASE	0xB3100000
-#define	NBM_BASE	0xB3F00000
-
-#define	CPM_BASE	0xB0000000
-#define	INTC_BASE	0xB0001000
-#define TCU_BASE	0xB0002000
-#define	RTC_BASE	0xB0003000
-#define	GPIO_BASE	0xB0010000
-#define	AIC_BASE	0xB0020000
-#define	MSC_BASE	0xB0021000
-#define	UART0_BASE	0xB0030000
-#define	UART1_BASE	0xB0031000
-#define	UART2_BASE	0xB0032000
-#define	UART3_BASE	0xB0033000
-#define	FIR_BASE	0xB0040000
-#define	SCC_BASE	0xB0041000
-#define	SCC0_BASE	0xB0041000
-#define	I2C_BASE	0xB0042000
-#define	SSI_BASE	0xB0043000
-#define	SCC1_BASE	0xB0044000
-#define	PWM0_BASE	0xB0050000
-#define	PWM1_BASE	0xB0051000
-#define	DES_BASE	0xB0060000
-#define	UPRT_BASE	0xB0061000
-#define KBC_BASE	0xB0062000
-
-/* CPM Register */
-#define CPM_CPCCR			__REG32(CPM_BASE + 0x00)	/* Clock Control Register */
-#define CPM_LCR				__REG32(CPM_BASE + 0x04)	/* Low Power Control Register */
-#define CPM_RSR				__REG32(CPM_BASE + 0x08)	/* Reset Status Register */
-#define CPM_CPPCR			__REG32(CPM_BASE + 0x10)	/* PLL Control Register */
-#define CPM_CPPSR			__REG32(CPM_BASE + 0x14)	/* PLL Switch and Status Register */
-#define CPM_CLKGR			__REG32(CPM_BASE + 0x20)	/* Clock Gate Register */
-#define CPM_OPCR			__REG32(CPM_BASE + 0x24)	/* Osillator and Power Control Register */
-#define CPM_I2SCDR			__REG32(CPM_BASE + 0x60)	/* I2S Device Clock Divider Register */
-#define CPM_LPCDR			__REG32(CPM_BASE + 0x64)	/* LCD Pixel Clock Divider Register */
-#define CPM_MSCCDR			__REG32(CPM_BASE + 0x68)	/* MSC Clock Divider Register */
-#define CPM_SSICDR			__REG32(CPM_BASE + 0x74)	/* SSI Clock Divider Register */
-#define CPM_CIMCDR			__REG32(CPM_BASE + 0x7C)	/* CIM MCLK Clock Divider Register */
-
-/* Interrupt Controller Regester */
-#define INTC_ISR			__REG32(INTC_BASE + 0x00)
-#define INTC_IMR			__REG32(INTC_BASE + 0x04)
-#define INTC_IMSR			__REG32(INTC_BASE + 0x08)
-#define INTC_IMCR			__REG32(INTC_BASE + 0x0c)
-#define INTC_IPR			__REG32(INTC_BASE + 0x10)
-
-/* TCU Register */
-#define TCU_TSTR			__REG32(TCU_BASE + 0xF0)
-#define TCU_TSTSR			__REG32(TCU_BASE + 0xF4)
-#define TCU_TSTCR			__REG32(TCU_BASE + 0xF8)
-#define TCU_TSR				__REG32(TCU_BASE + 0x1C)
-#define TCU_TSSR			__REG32(TCU_BASE + 0x2C)
-#define TCU_TSCR			__REG32(TCU_BASE + 0x3C)
-#define TCU_TER				__REG32(TCU_BASE + 0x10)
-#define TCU_TESR			__REG32(TCU_BASE + 0x14)
-#define TCU_TECR			__REG32(TCU_BASE + 0x18)
-#define TCU_TFR				__REG32(TCU_BASE + 0x20)
-#define TCU_TFSR			__REG32(TCU_BASE + 0x24)
-#define TCU_TFCR			__REG32(TCU_BASE + 0x28)
-#define TCU_TMR				__REG32(TCU_BASE + 0x30)
-#define TCU_TMSR			__REG32(TCU_BASE + 0x34)
-#define TCU_TMCR			__REG32(TCU_BASE + 0x38)
-#define TCU_TDFR0_OFFSET	0x40
-#define TCU_TDFR(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TDFR0_OFFSET)
-#define TCU_TDHR0_OFFSET	0x44
-#define TCU_TDHR(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TDHR0_OFFSET)
-#define TCU_TCNT0_OFFSET	0x48
-#define TCU_TCNT(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TCNT0_OFFSET)
-#define TCU_TCSR0_OFFSET	0x4C
-#define TCU_TCSR(x)			__REG16(TCU_BASE + (x) * 0x10 + TCU_TCSR0_OFFSET)
-
-/* TCU Register Definitions */
-#define TCU_TCSR_PWM_SD         (1 << 9)
-#define TCU_TCSR_PWM_INITL_HIGH (1 << 8)
-#define TCU_TCSR_PWM_EN         (1 << 7)
-#define TCU_TCSR_PRESCALE_BIT   3
-#define TCU_TCSR_PRESCALE_MASK  (0x7 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1      (0x0 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE4      (0x1 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE16     (0x2 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE64     (0x3 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE256    (0x4 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_PRESCALE1024   (0x5 << TCU_TCSR_PRESCALE_BIT)
-#define TCU_TCSR_EXT_EN         (1 << 2)
-#define TCU_TCSR_RTC_EN         (1 << 1)
-#define TCU_TCSR_PCK_EN         (1 << 0)
-
-#define TCU_TER_OSTEN   (1 << 15)
-#define TCU_TER_TCEN5   (1 << 5)
-#define TCU_TER_TCEN4   (1 << 4)
-#define TCU_TER_TCEN3   (1 << 3)
-#define TCU_TER_TCEN2   (1 << 2)
-#define TCU_TER_TCEN1   (1 << 1)
-#define TCU_TER_TCEN0   (1 << 0)
-
-#define TCU_TESR_OSTST  (1 << 15)
-#define TCU_TESR_TCST5  (1 << 5)
-#define TCU_TESR_TCST4  (1 << 4)
-#define TCU_TESR_TCST3  (1 << 3)
-#define TCU_TESR_TCST2  (1 << 2)
-#define TCU_TESR_TCST1  (1 << 1)
-#define TCU_TESR_TCST0  (1 << 0)
-
-#define TCU_TECR_OSTCL  (1 << 15)
-#define TCU_TECR_TCCL5  (1 << 5)
-#define TCU_TECR_TCCL4  (1 << 4)
-#define TCU_TECR_TCCL3  (1 << 3)
-#define TCU_TECR_TCCL2  (1 << 2)
-#define TCU_TECR_TCCL1  (1 << 1)
-#define TCU_TECR_TCCL0  (1 << 0)
-
-#define TCU_TFR_HFLAG5  (1 << 21)
-#define TCU_TFR_HFLAG4  (1 << 20)
-#define TCU_TFR_HFLAG3  (1 << 19)
-#define TCU_TFR_HFLAG2  (1 << 18)
-#define TCU_TFR_HFLAG1  (1 << 17)
-#define TCU_TFR_HFLAG0  (1 << 16)
-#define TCU_TFR_FFLAG5  (1 << 5)
-#define TCU_TFR_FFLAG4  (1 << 4)
-#define TCU_TFR_FFLAG3  (1 << 3)
-#define TCU_TFR_FFLAG2  (1 << 2)
-#define TCU_TFR_FFLAG1  (1 << 1)
-#define TCU_TFR_FFLAG0  (1 << 0)
-
-#define TCU_TFSR_HFLAG5 (1 << 21)
-#define TCU_TFSR_HFLAG4 (1 << 20)
-#define TCU_TFSR_HFLAG3 (1 << 19)
-#define TCU_TFSR_HFLAG2 (1 << 18)
-#define TCU_TFSR_HFLAG1 (1 << 17)
-#define TCU_TFSR_HFLAG0 (1 << 16)
-#define TCU_TFSR_OSTFLAG (1 << 15)
-#define TCU_TFSR_FFLAG5 (1 << 5)
-#define TCU_TFSR_FFLAG4 (1 << 4)
-#define TCU_TFSR_FFLAG3 (1 << 3)
-#define TCU_TFSR_FFLAG2 (1 << 2)
-#define TCU_TFSR_FFLAG1 (1 << 1)
-#define TCU_TFSR_FFLAG0 (1 << 0)
-
-#define TCU_TFCR_HFLAG5 (1 << 21)
-#define TCU_TFCR_HFLAG4 (1 << 20)
-#define TCU_TFCR_HFLAG3 (1 << 19)
-#define TCU_TFCR_HFLAG2 (1 << 18)
-#define TCU_TFCR_HFLAG1 (1 << 17)
-#define TCU_TFCR_HFLAG0 (1 << 16)
-#define TCU_TFCR_OSTFLAG (1 << 15)
-#define TCU_TFCR_FFLAG5 (1 << 5)
-#define TCU_TFCR_FFLAG4 (1 << 4)
-#define TCU_TFCR_FFLAG3 (1 << 3)
-#define TCU_TFCR_FFLAG2 (1 << 2)
-#define TCU_TFCR_FFLAG1 (1 << 1)
-#define TCU_TFCR_FFLAG0 (1 << 0)
-
-#define TCU_TMR_HMASK5  (1 << 21)
-#define TCU_TMR_HMASK4  (1 << 20)
-#define TCU_TMR_HMASK3  (1 << 19)
-#define TCU_TMR_HMASK2  (1 << 18)
-#define TCU_TMR_HMASK1  (1 << 17)
-#define TCU_TMR_HMASK0  (1 << 16)
-#define TCU_TMR_OSTMASK (1 << 15)
-#define TCU_TMR_FMASK5  (1 << 5)
-#define TCU_TMR_FMASK4  (1 << 4)
-#define TCU_TMR_FMASK3  (1 << 3)
-#define TCU_TMR_FMASK2  (1 << 2)
-#define TCU_TMR_FMASK1  (1 << 1)
-#define TCU_TMR_FMASK0  (1 << 0)
-
-#define TCU_TMSR_HMST5  (1 << 21)
-#define TCU_TMSR_HMST4  (1 << 20)
-#define TCU_TMSR_HMST3  (1 << 19)
-#define TCU_TMSR_HMST2  (1 << 18)
-#define TCU_TMSR_HMST1  (1 << 17)
-#define TCU_TMSR_HMST0  (1 << 16)
-#define TCU_TMSR_OSTMST (1 << 15)
-#define TCU_TMSR_FMST5  (1 << 5)
-#define TCU_TMSR_FMST4  (1 << 4)
-#define TCU_TMSR_FMST3  (1 << 3)
-#define TCU_TMSR_FMST2  (1 << 2)
-#define TCU_TMSR_FMST1  (1 << 1)
-#define TCU_TMSR_FMST0  (1 << 0)
-
-#define TCU_TMCR_HMCL5  (1 << 21)
-#define TCU_TMCR_HMCL4  (1 << 20)
-#define TCU_TMCR_HMCL3  (1 << 19)
-#define TCU_TMCR_HMCL2  (1 << 18)
-#define TCU_TMCR_HMCL1  (1 << 17)
-#define TCU_TMCR_HMCL0  (1 << 16)
-#define TCU_TMCR_OSTMCL (1 << 15)
-#define TCU_TMCR_FMCL5  (1 << 5)
-#define TCU_TMCR_FMCL4  (1 << 4)
-#define TCU_TMCR_FMCL3  (1 << 3)
-#define TCU_TMCR_FMCL2  (1 << 2)
-#define TCU_TMCR_FMCL1  (1 << 1)
-#define TCU_TMCR_FMCL0  (1 << 0)
-
-#define TCU_TSR_WDTS    (1 << 16)
-#define TCU_TSR_STOP5   (1 << 5)
-#define TCU_TSR_STOP4   (1 << 4)
-#define TCU_TSR_STOP3   (1 << 3)
-#define TCU_TSR_STOP2   (1 << 2)
-#define TCU_TSR_STOP1   (1 << 1)
-#define TCU_TSR_STOP0   (1 << 0)
-
-#define TCU_TSSR_WDTSS  (1 << 16)
-#define TCU_TSSR_STPS5  (1 << 5)
-#define TCU_TSSR_STPS4  (1 << 4)
-#define TCU_TSSR_STPS3  (1 << 3)
-#define TCU_TSSR_STPS2  (1 << 2)
-#define TCU_TSSR_STPS1  (1 << 1)
-#define TCU_TSSR_STPS0  (1 << 0)
-
-#define TCU_TSSR_WDTSC  (1 << 16)
-#define TCU_TSSR_STPC5  (1 << 5)
-#define TCU_TSSR_STPC4  (1 << 4)
-#define TCU_TSSR_STPC3  (1 << 3)
-#define TCU_TSSR_STPC2  (1 << 2)
-#define TCU_TSSR_STPC1  (1 << 1)
-#define TCU_TSSR_STPC0  (1 << 0)
-
-#define OST_TCSR_CNT_MD                  ( 1 << 15 )
-#define OST_TCSR_PWM_SHUT_ABRUPT         ( 1 << 9 )
-#define OST_TCSR_PRESCALE1               ( 0x0 << 3)
-#define OST_TCSR_PRESCALE4               ( 0x1 << 3)
-#define OST_TCSR_PRESCALE16              ( 0x2 << 3)
-#define OST_TCSR_PRESCALE64              ( 0x3 << 3)
-#define OST_TCSR_PRESCALE256             ( 0x4 << 3)
-#define OST_TCSR_PRESCALE1024            ( 0x5 << 3)
-
-/* Uart Register */
-#define UART_RDR(base)		__REG8((base) + 0x00)	/* R  8b H'xx */
-#define UART_TDR(base)		__REG8((base) + 0x00)	/* W  8b H'xx */
-#define UART_DLLR(base)		__REG8((base) + 0x00)	/* RW 8b H'00 */
-#define UART_DLHR(base)		__REG8((base) + 0x04)	/* RW 8b H'00 */
-#define UART_IER(base)		__REG8((base) + 0x04)	/* RW 8b H'00 */
-#define UART_ISR(base)		__REG8((base) + 0x08)	/* R  8b H'01 */
-#define UART_FCR(base)		__REG8((base) + 0x08)	/* W  8b H'00 */
-#define UART_LCR(base)		__REG8((base) + 0x0C)	/* RW 8b H'00 */
-#define UART_MCR(base)		__REG8((base) + 0x10)	/* RW 8b H'00 */
-#define UART_LSR(base)		__REG8((base) + 0x14)	/* R  8b H'00 */
-#define UART_MSR(base)		__REG8((base) + 0x18)	/* R  8b H'00 */
-#define UART_SPR(base)		__REG8((base) + 0x1C)	/* RW 8b H'00 */
-#define UART_MCR(base)		__REG8((base) + 0x10)	/* RW 8b H'00 */
-#define UART_SIRCR(base)	__REG8((base) + 0x20)	/* RW 8b H'00 */
-
-#define SYSTEM_STACK          0x80003fe8		/* the kernel system stack address */
-
-#endif
diff --git a/libcpu/mips/jz47xx/mipscfg.c b/libcpu/mips/jz47xx/mipscfg.c
deleted file mode 100644
index 8a96f458ab..0000000000
--- a/libcpu/mips/jz47xx/mipscfg.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * File      : mipscfg.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-27     swkyer       first version
- */
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-#include "../common/mipscfg.h"
-
-mips32_core_cfg_t g_mips_core =
-{
-	16,		/* icache_line_size */
-	256,	/* icache_lines_per_way */
-	4,		/* icache_ways */
-	16,		/* dcache_line_size */
-	256,	/* dcache_lines_per_way */
-	4,		/* dcache_ways */
-	16,		/* max_tlb_entries */
-};
-
-static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
-{
-	rt_uint16_t rets = 1;
-
-    while (n--)
-        rets *= b;
-
-    return rets;
-}
-
-static rt_uint16_t m_log2(rt_uint16_t b)
-{
-	rt_uint16_t rets = 0;
-
-    while (b != 1)
-    {
-        b /= 2;
-        rets++;
-    }
-
-    return rets;
-}
-
-/**
- * read core attribute
- */
-void mips32_cfg_init(void)
-{
-	rt_uint16_t val;
-	rt_uint32_t cp0_config1;
-
-	cp0_config1 = read_c0_config();
-	if (cp0_config1 & 0x80000000)
-	{
-		cp0_config1 = read_c0_config1();
-
-		val = (cp0_config1 & (7<<22))>>22;
-		g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<19))>>19;
-		g_mips_core.icache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<16))>>16;
-		g_mips_core.icache_ways = val + 1;
-
-		val = (cp0_config1 & (7<<13))>>13;
-		g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<10))>>10;
-		g_mips_core.dcache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<7))>>7;
-		g_mips_core.dcache_ways = val + 1;
-
-		val = (cp0_config1 & (0x3F<<25))>>25;
-		g_mips_core.max_tlb_entries = val + 1;
-	}
-}
diff --git a/libcpu/mips/jz47xx/stack.c b/libcpu/mips/jz47xx/stack.c
deleted file mode 100644
index 1d408bbff1..0000000000
--- a/libcpu/mips/jz47xx/stack.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-07-07     Bernard      porting to Jz47xx
- */
-#include <rtthread.h>
-
-/**
- * @addtogroup Jz47xx
- */
-/*@{*/
-
-extern rt_uint32_t cp0_get_cause(void);
-extern rt_uint32_t cp0_get_status(void);
-extern rt_uint32_t cp0_get_hi(void);
-extern rt_uint32_t cp0_get_lo(void);
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
-	rt_uint32_t *stk;
-    static rt_uint32_t g_sr = 0;
-
-    if (g_sr == 0)
-    {
-    	g_sr = cp0_get_status();
-    	g_sr &= 0xfffffffe;
-    	g_sr |= 0x0403;
-    }
-
-    /** Start at stack top */
-    stk = (rt_uint32_t *)stack_addr;
-	*(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
-	*(--stk) = (rt_uint32_t) 0xeeee; 		/* c0_cause */
-	*(--stk) = (rt_uint32_t) 0xffff;		/* c0_badvaddr */
-	*(--stk) = (rt_uint32_t) cp0_get_lo();	/* lo */
-	*(--stk) = (rt_uint32_t) cp0_get_hi();	/* hi */
-	*(--stk) = (rt_uint32_t) g_sr; 			/* C0_SR: HW2 = En, IE = En */
-	*(--stk) = (rt_uint32_t) texit;	        /* ra */
-	*(--stk) = (rt_uint32_t) 0x0000001e;	/* s8 */
-	*(--stk) = (rt_uint32_t) stack_addr;	/* sp */
-	*(--stk) = (rt_uint32_t) 0x0000001c;	/* gp */
-	*(--stk) = (rt_uint32_t) 0x0000001b;	/* k1 */
-	*(--stk) = (rt_uint32_t) 0x0000001a;	/* k0 */
-	*(--stk) = (rt_uint32_t) 0x00000019;	/* t9 */
-	*(--stk) = (rt_uint32_t) 0x00000018;	/* t8 */
-	*(--stk) = (rt_uint32_t) 0x00000017;	/* s7 */
-	*(--stk) = (rt_uint32_t) 0x00000016;	/* s6 */
-	*(--stk) = (rt_uint32_t) 0x00000015;	/* s5 */
-	*(--stk) = (rt_uint32_t) 0x00000014;	/* s4 */
-	*(--stk) = (rt_uint32_t) 0x00000013;	/* s3 */
-	*(--stk) = (rt_uint32_t) 0x00000012;	/* s2 */
-	*(--stk) = (rt_uint32_t) 0x00000011;	/* s1 */
-	*(--stk) = (rt_uint32_t) 0x00000010;	/* s0 */
-	*(--stk) = (rt_uint32_t) 0x0000000f;	/* t7 */
-	*(--stk) = (rt_uint32_t) 0x0000000e;	/* t6 */
-	*(--stk) = (rt_uint32_t) 0x0000000d;	/* t5 */
-	*(--stk) = (rt_uint32_t) 0x0000000c;	/* t4 */
-	*(--stk) = (rt_uint32_t) 0x0000000b;	/* t3 */
-	*(--stk) = (rt_uint32_t) 0x0000000a; 	/* t2 */
-	*(--stk) = (rt_uint32_t) 0x00000009;	/* t1 */
-	*(--stk) = (rt_uint32_t) 0x00000008;	/* t0 */
-	*(--stk) = (rt_uint32_t) 0x00000007;	/* a3 */
-	*(--stk) = (rt_uint32_t) 0x00000006;	/* a2 */
-	*(--stk) = (rt_uint32_t) 0x00000005;	/* a1 */
-	*(--stk) = (rt_uint32_t) parameter;	    /* a0 */
-	*(--stk) = (rt_uint32_t) 0x00000003;	/* v1 */
-	*(--stk) = (rt_uint32_t) 0x00000002;	/* v0 */
-	*(--stk) = (rt_uint32_t) 0x00000001;	/* at */
-	*(--stk) = (rt_uint32_t) 0x00000000;	/* zero */
-
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
-}
-
-/*@}*/
diff --git a/libcpu/mips/jz47xx/start_gcc.S b/libcpu/mips/jz47xx/start_gcc.S
deleted file mode 100644
index 418a68d0f8..0000000000
--- a/libcpu/mips/jz47xx/start_gcc.S
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * File      : start_gcc.S
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      porting to Jz47xx
- */
-
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-#include "jz47xx.h"
-
-    .section ".start", "ax"
-    .set noreorder
-
-    /* the program entry */
-    .globl  _start
-_start:
-    .set    noreorder
-    la      ra, _start
-
-    li	    t1, 0x00800000
-    mtc0    t1, CP0_CAUSE
-
-    /* init cp0 registers. */
-    li	    t0, 0x0000FC00 /* BEV = 0 and mask all interrupt */
-    mtc0    t0, CP0_STATUS
-
-    /* setup stack pointer */
-    li      sp, SYSTEM_STACK
-    la      gp, _gp
-
-    /* init caches, assumes a 4way * 128set * 32byte I/D cache */
-    mtc0    zero, CP0_TAGLO  /* TAGLO reg */
-    mtc0    zero, CP0_TAGHI  /* TAGHI reg */
-    li      t0, 3            /* enable cache for kseg0 accesses */
-    mtc0    t0, CP0_CONFIG    /* CONFIG reg */
-    la      t0, 0x80000000   /* an idx op should use an unmappable address */
-    ori     t1, t0, 0x4000   /* 16kB cache */
-
-_cache_loop:
-    cache   0x8, 0(t0)       /* index store icache tag */
-    cache   0x9, 0(t0)       /* index store dcache tag */
-    bne     t0, t1, _cache_loop
-    addiu   t0, t0, 0x20     /* 32 bytes per cache line */
-    nop
-
-    /* invalidate BTB */
-    mfc0    t0, CP0_CONFIG
-    nop
-    ori     t0, 2
-    mtc0    t0, CP0_CONFIG
-    nop
-
-    /* copy IRAM section */
-    la     t0, _iramcopy
-    la     t1, _iramstart
-    la     t2, _iramend
-_iram_loop:
-    lw     t3, 0(t0)
-    sw     t3, 0(t1)
-    addiu  t1, 4
-    bne    t1, t2, _iram_loop
-    addiu  t0, 4
-
-    /* clear bss */
-    la      t0, __bss_start
-    la      t1, __bss_end
-_clr_bss_loop:
-    sw      zero, 0(t0)
-    bne     t0, t1, _clr_bss_loop
-    addiu   t0, t0, 4
-
-    /* jump to RT-Thread RTOS */
-    jal     rtthread_startup
-    nop
-
-    /* restart, never die */
-    j       _start
-    nop
-    .set    reorder
-
-    .globl  cp0_get_cause
-cp0_get_cause:
-    mfc0    v0, CP0_CAUSE
-    jr      ra
-    nop
-
-    .globl  cp0_get_status
-cp0_get_status:
-    mfc0    v0, CP0_STATUS
-    jr      ra
-    nop
-
-    .globl  cp0_get_hi
-cp0_get_hi:
-    mfhi    v0
-    jr      ra
-    nop
-
-    .globl  cp0_get_lo
-cp0_get_lo:
-    mflo    v0
-    jr      ra
-    nop
-
-	.extern tlb_refill_handler
-	.extern cache_error_handler
-
-	/* Exception Handler */
-	/* 0x0 - TLB refill handler */
-    .section .vectors.1, "ax", %progbits
-    j      tlb_refill_handler
-    nop
-	
-	/* 0x100 - Cache error handler */
-    .section .vectors.2, "ax", %progbits
-    j      cache_error_handler
-    nop
-    
-	/* 0x180 - Exception/Interrupt handler */
-    .section .vectors.3, "ax", %progbits
-    j      _general_exception_handler
-    nop
-    
-	/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
-    .section .vectors.4, "ax", %progbits
-    j      _irq_handler
-    nop
-	
-    .section .vectors, "ax", %progbits
-	.extern mips_irq_handle
-
-    /* general exception handler */
-_general_exception_handler:
-    .set    noreorder
-    mfc0    k1, CP0_CAUSE
-    andi    k1, k1, 0x7c
-    srl     k1, k1, 2
-    lw      k0, sys_exception_handlers(k1)
-    jr      k0
-    nop
-    .set    reorder
-
-    /* interrupt handler */
-_irq_handler:
-    .set    noreorder
-    la      k0, mips_irq_handle
-    jr      k0
-    nop
-    .set    reorder
diff --git a/libcpu/mips/loongson/cache.c b/libcpu/mips/loongson/cache.c
deleted file mode 100644
index 6b3ad84b0e..0000000000
--- a/libcpu/mips/loongson/cache.c
+++ /dev/null
@@ -1,188 +0,0 @@
-#include "../common/mipsregs.h"
-#include "cache.h"
-
-#define K0BASE			0x80000000
-#define PRID_3210I 		0x4200
-
-typedef struct cacheinfo_t {
-	unsigned int	icache_size;
-	unsigned int	dcache_size;
-	unsigned int	icacheline_size;
-	unsigned int	dcacheline_size;
-} cacheinfo_t ;
-
-typedef struct cacheop_t {
-	void (*Clear_TagLo) (void);
-	void (*Invalidate_Icache) (unsigned int);
-	void (*Invalidate_Dcache_Fill) (unsigned int);
-	void (*Invalidate_Dcache_ClearTag) (unsigned int);
-	void (*Init_Cache)(void);
-} cacheop_t ;
-
-static cacheop_t cacheop, *pcacheop;
-static cacheinfo_t cacheinfo, *pcacheinfo;
-
-int identify_cpu (void)
-{
-    unsigned int cpu_id;
-    void invalidate_cache (void);
-
-    pcacheop = &cacheop;
-    pcacheinfo = &cacheinfo;
-
-	rt_kprintf("CPU configure: 0x%08x\n", read_c0_config());
-    cpu_id = read_c0_prid();
-    switch (cpu_id)
-	{
-	case PRID_3210I: 
-	    rt_kprintf ("CPU:SoC3210\n");
-	    pcacheop->Clear_TagLo = Clear_TagLo;
-	    pcacheop->Invalidate_Icache = Invalidate_Icache_Gc3210I;
-	    pcacheop->Invalidate_Dcache_Fill = Invalidate_Dcache_Fill_Gc3210I;
-	    pcacheop->Invalidate_Dcache_ClearTag = Invalidate_Dcache_ClearTag_Gc3210I;
-	    break;
-	default:
-	    rt_kprintf ("Unknown CPU type, system halted!\n");
-	    while (1) {}
-	    break;
-    }
-
-    return 0;
-}
-
-void probe_cache(void)
-{
-    unsigned int config = read_c0_config ();
-    unsigned int icache_size, ic_lsize;
-    unsigned int dcache_size, dc_lsize;
-
-    icache_size = 1 << (12 + ((config >> 9) & 7)); 
-    dcache_size = 1 << (12 + ((config >> 6) & 7));
-    ic_lsize = 16 << ((config >> 5) & 1);
-    dc_lsize = 16 << ((config >> 4) & 1);
-
-    rt_kprintf("DCache %2dkb, linesize %d bytes.\n",
-	    dcache_size >> 10, dc_lsize);
-    rt_kprintf("ICache %2dkb, linesize %d bytes.\n",
-	    icache_size >> 10, ic_lsize);
-
-    pcacheinfo->icache_size = icache_size;
-    pcacheinfo->dcache_size = dcache_size;
-    pcacheinfo->icacheline_size = ic_lsize;
-    pcacheinfo->dcacheline_size = dc_lsize;
-
-    return ;
-}
-
-void invalidate_writeback_dcache_all(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
-
-	start = K0BASE;
-	while(start < end) {
-		Writeback_Invalidate_Dcache(start);  //hit writeback invalidate 
-		start += pcacheinfo->dcacheline_size;
-	}
-}
-
-void invalidate_writeback_dcache(unsigned long addr, int size)
-{
-	unsigned long start, end;
-			
-	start = (addr +pcacheinfo->dcacheline_size -1) & (- pcacheinfo->dcacheline_size);
-	end = (end + size + pcacheinfo->dcacheline_size -1) & ( -pcacheinfo->dcacheline_size);
-	
-	while(start <end){
-		Writeback_Invalidate_Dcache(start);
-		start += pcacheinfo->dcacheline_size;
-	}		
-}
-
-
-void invalidate_icache_all(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->icache_size);
-
-	while(start < end) {
-		pcacheop->Invalidate_Icache(start); 
-		start += pcacheinfo->icacheline_size;
-	}
-}
-
-void invalidate_dcache_all()
-{ 
-	unsigned int start = K0BASE;
-	unsigned int end  = (start + pcacheinfo->dcache_size);
-	while(start <end){
-		Invalidate_Dcache_Fill_Gc3210I(start);
-		start += pcacheinfo->icacheline_size;
-	}
-}
-
-//with cache disabled
-void init_dcache(void)
-{
-	unsigned int start = K0BASE;
-	unsigned int end = (start + pcacheinfo->dcache_size);
-
-	while(start < end){
-		pcacheop->Invalidate_Dcache_ClearTag(start);
-		start += pcacheinfo->dcacheline_size;
-	}
-
-}
-
-void rt_hw_cache_init(void)
-{
-    unsigned int start, end;
-	
-	/* 1. identify cpu and probe cache */
-	identify_cpu();
-	probe_cache();
-
-	start = K0BASE;
-	end = (start + pcacheinfo->icache_size);
-
-    /*
-     *	2. clear CP0 taglo/taghi register;
-     */
-    pcacheop->Clear_TagLo();
-
-	/*
-     *	3. invalidate instruction cache;
-     */
-    while(start < end) {
-		pcacheop->Invalidate_Icache(start); //index invalidate icache 
-		start += pcacheinfo->icacheline_size;
-    }
-
-    /*
-     *	4. invalidate data cache;
-     */
-    start = K0BASE;
-    end = (start + pcacheinfo->dcache_size);
-    while(start < end) {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
-    }
-
-    start = K0BASE;
-    while(start < end) {
-		pcacheop->Invalidate_Dcache_Fill(start);  //index invalidate dcache
-		start += pcacheinfo->dcacheline_size;
-    }
-
-    start = K0BASE;
-    while(start < end) {
-		pcacheop->Invalidate_Dcache_ClearTag(start); 
-		start += pcacheinfo->dcacheline_size;
-    }
-
-	/* enable cache */
-	enable_cpu_cache();
-	rt_kprintf("enable cpu cache done\n");
-
-	return ;
-}
diff --git a/libcpu/mips/loongson/cache.h b/libcpu/mips/loongson/cache.h
deleted file mode 100644
index 26f7649b42..0000000000
--- a/libcpu/mips/loongson/cache.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef	__CACHE_H__
-#define	__CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I		0x04
-#define Index_Load_Tag_D		0x05
-#define Index_Load_Tag_SI		0x06
-#define Index_Load_Tag_SD		0x07
-#define Index_Store_Tag_I		0x08
-#define Index_Store_Tag_D		0x09
-#define Index_Store_Tag_SI		0x0A
-#define Index_Store_Tag_SD		0x0B
-#define Create_Dirty_Excl_D		0x0d
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_I		0x10
-#define Hit_Invalidate_D		0x11
-#define Hit_Invalidate_SI		0x12
-#define Hit_Invalidate_SD		0x13
-#define Fill					0x14
-#define Hit_Writeback_Inv_D		0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_I			0x18
-#define Hit_Writeback_D			0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD		0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI		0x1e
-#define Hit_Set_Virtual_SD		0x1f
-
-extern void Clear_TagLo (void);
-
-extern void Invalidate_Icache_Gc3210I (unsigned int);
-extern void Invalidate_Dcache_ClearTag_Gc3210I (unsigned int);
-extern void Invalidate_Dcache_Fill_Gc3210I(unsigned int);
-extern void Writeback_Invalidate_Dcache(unsigned int);
-
-void rt_hw_cache_init(void);
-
-#endif
diff --git a/libcpu/mips/loongson/cache.inc b/libcpu/mips/loongson/cache.inc
deleted file mode 100644
index 815abb7f92..0000000000
--- a/libcpu/mips/loongson/cache.inc
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef	__CACHE_H__
-#define	__CACHE_H__
-
-/*
- * Cache Operations
- */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_I		0x04
-#define Index_Load_Tag_D		0x05
-#define Index_Load_Tag_SI		0x06
-#define Index_Load_Tag_SD		0x07
-#define Index_Store_Tag_I		0x08
-#define Index_Store_Tag_D		0x09
-#define Index_Store_Tag_SI		0x0A
-#define Index_Store_Tag_SD		0x0B
-#define Create_Dirty_Excl_D		0x0d
-#define Create_Dirty_Excl_SD	0x0f
-#define Hit_Invalidate_I		0x10
-#define Hit_Invalidate_D		0x11
-#define Hit_Invalidate_SI		0x12
-#define Hit_Invalidate_SD		0x13
-#define Fill					0x14
-#define Hit_Writeback_Inv_D		0x15
-/* 0x16 is unused */
-#define Hit_Writeback_Inv_SD	0x17
-#define Hit_Writeback_I			0x18
-#define Hit_Writeback_D			0x19
-/* 0x1a is unused */
-#define Hit_Writeback_SD		0x1b
-/* 0x1c is unused */
-/* 0x1e is unused */
-#define Hit_Set_Virtual_SI		0x1e
-#define Hit_Set_Virtual_SD		0x1f
-
-#endif
diff --git a/libcpu/mips/loongson/cache_gcc.S b/libcpu/mips/loongson/cache_gcc.S
deleted file mode 100644
index 00fd861eec..0000000000
--- a/libcpu/mips/loongson/cache_gcc.S
+++ /dev/null
@@ -1,202 +0,0 @@
-#include "../common/mipsregs.h"
-#include "../common/mips.inc"
-#include "../common/asm.h"
-#include "cache.inc"
-
-	.ent	cache_init
-    .global cache_init
-    .set noreorder
-cache_init:
-        move t1,ra
-####part 2####
-cache_detect_4way:
-        mfc0    t4, CP0_CONFIG
-        andi    t5, t4, 0x0e00
-        srl     t5, t5, 9     #ic
-        andi    t6, t4, 0x01c0
-        srl     t6, t6, 6     #dc
-        addiu   t8, $0, 1
-        addiu   t9, $0, 2
-                                #set dcache way
-        beq     t6, $0,  cache_d1way
-        addiu   t7, $0, 1       #1 way
-        beq     t6, t8,  cache_d2way
-        addiu   t7, $0, 2       #2 way
-        beq     $0, $0, cache_d4way
-        addiu   t7, $0, 4       #4 way
-cache_d1way:
-        beq     $0, $0, 1f
-        addiu   t6, t6, 12      #1 way
-cache_d2way:
-        beq     $0, $0, 1f
-        addiu   t6, t6, 11      #2 way
-cache_d4way:
-        addiu   t6, t6, 10      #4 way (10), 2 way(11), 1 way(12)
-1:                              #set icache way
-        beq     t5, $0,  cache_i1way
-        addiu   t3, $0, 1       #1 way
-        beq     t5, t8,  cache_i2way
-        addiu   t3, $0, 2       #2 way
-        beq     $0, $0, cache_i4way
-        addiu   t3, $0, 4       #4 way
-cache_i1way:
-        beq     $0, $0, 1f
-        addiu   t5, t5, 12
-cache_i2way:
-        beq     $0, $0, 1f
-        addiu   t5, t5, 11
-cache_i4way:
-        addiu   t5, t5, 10      #4 way (10), 2 way(11), 1 way(12)
-
-1:      addiu   t4, $0, 1
-        sllv    t6, t4, t6
-        sllv    t5, t4, t5
-#if 0
-    la	t0, memvar
-	sw	t7, 0x0(t0) #ways
-	sw	t5, 0x4(t0) #icache size
-	sw	t6, 0x8(t0) #dcache size
-#endif
-####part 3####
-	.set	mips3
-	lui	a0, 0x8000
-	addu	a1, $0, t5
-	addu	a2, $0, t6
-cache_init_d2way:
-#a0=0x80000000, a1=icache_size, a2=dcache_size
-#a3, v0 and v1 used as local registers
-	mtc0	$0, CP0_TAGHI
-	addu	v0, $0, a0
-	addu	v1, a0, a2
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	mtc0	$0, CP0_TAGLO
-	beq	t7, 1, 4f
-	cache	Index_Store_Tag_D, 0x0(v0)	# 1 way
-	beq	t7, 2 ,4f
-	cache	Index_Store_Tag_D, 0x1(v0)	# 2 way
-	cache	Index_Store_Tag_D, 0x2(v0)	# 4 way
-	cache	Index_Store_Tag_D, 0x3(v0)
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_flush_i2way:
-	addu	v0, $0, a0
-	addu	v1, a0, a1
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	beq	t3, 1, 4f
-	cache	Index_Invalidate_I, 0x0(v0)	# 1 way
-	beq	t3, 2, 4f
-	cache	Index_Invalidate_I, 0x1(v0)	# 2 way
-	cache	Index_Invalidate_I, 0x2(v0)
-	cache	Index_Invalidate_I, 0x3(v0)	# 4 way
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_flush_d2way:
-	addu	v0, $0, a0
-	addu	v1, a0, a2
-1:	slt	a3, v0, v1
-	beq	a3, $0, 1f
-	nop
-	beq	t7, 1, 4f
-	cache	Index_Writeback_Inv_D, 0x0(v0) 	#1 way
-	beq	t7, 2, 4f
-	cache	Index_Writeback_Inv_D, 0x1(v0)	# 2 way
-	cache	Index_Writeback_Inv_D, 0x2(v0)
-	cache	Index_Writeback_Inv_D, 0x3(v0)	# 4 way
-4:	beq	$0, $0, 1b
-	addiu	v0, v0, 0x20
-1:
-cache_init_finish:
-	jr	t1
-    nop
-    .set reorder
-	.end cache_init
-
-###########################
-#  Enable CPU cache       #
-###########################
-
-LEAF(enable_cpu_cache)
-	.set noreorder
-	mfc0	t0, CP0_CONFIG
-	nop
-	and		t0, ~0x03
-	or		t0, 0x03
-	mtc0	t0, CP0_CONFIG
-	nop
-	.set reorder
-	j	ra
-END (enable_cpu_cache)
-    
-###########################
-#  disable CPU cache      #
-###########################
-
-LEAF(disable_cpu_cache)
-	.set noreorder
-	mfc0	t0, CP0_CONFIG
-	nop
-	and		t0, ~0x03
-	or 		t0, 0x2
-	mtc0	t0, CP0_CONFIG
-	nop
-	.set reorder
-	j	ra
-END (disable_cpu_cache)
-
-/**********************************/
-/* Invalidate Instruction Cache	  */
-/**********************************/
-LEAF(Clear_TagLo)
-	.set 	noreorder
-	mtc0	zero, CP0_TAGLO
-	nop
-	.set 	reorder
-	j		ra
-END(Clear_TagLo)
-
-    .set mips3
-/**********************************/
-/* Invalidate Instruction Cache	  */
-/**********************************/
-LEAF(Invalidate_Icache_Gc3210I)
-	.set	noreorder
-	cache	Index_Invalidate_I,0(a0)
-	cache	Index_Invalidate_I,1(a0)
-	cache	Index_Invalidate_I,2(a0)
-	cache	Index_Invalidate_I,3(a0)
-	.set	reorder
-	j		ra
-END(Invalidate_Icache_Gc3210I)
-
-/**********************************/
-/* Invalidate Data Cache		  */
-/**********************************/
-LEAF(Invalidate_Dcache_ClearTag_Gc3210I)
-	.set	noreorder
-	cache	Index_Store_Tag_D, 0(a0)	# BDSLOT: clear tag
-	cache	Index_Store_Tag_D, 1(a0)	# BDSLOT: clear tag
-	.set	reorder
-	j		ra
-END(Invalidate_Dcache_ClearTag_Gc3210I)
-
-LEAF(Invalidate_Dcache_Fill_Gc3210I)
-	.set	noreorder
-	cache	Index_Writeback_Inv_D, 0(a0)	# BDSLOT: clear tag
-	cache	Index_Writeback_Inv_D, 1(a0)	# BDSLOT: clear tag
-	.set	reorder
-	j		ra
-END(Invalidate_Dcache_Fill_Gc3210I)
-
-LEAF(Writeback_Invalidate_Dcache)
-	.set noreorder
-	cache	Hit_Writeback_Inv_D, (a0)
-	.set reorder
-	j	ra
-END(Writeback_Invalidate_Dcache)
-    .set mips0
diff --git a/libcpu/mips/loongson/context_gcc.S b/libcpu/mips/loongson/context_gcc.S
deleted file mode 100644
index 1bb953fe8c..0000000000
--- a/libcpu/mips/loongson/context_gcc.S
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * File      : context_gcc.S
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to Loongson SoC3210
- */
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-#include "soc3210.h"
-
-    .section ".text", "ax"
-    .set noreorder
-
-/*
- * rt_base_t rt_hw_interrupt_disable()
- */
-    .globl rt_hw_interrupt_disable
-rt_hw_interrupt_disable:
-    mfc0    v0, CP0_STATUS
-    and     v1, v0, 0xfffffffe
-    mtc0    v1, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_interrupt_enable(rt_base_t level)
- */
-    .globl rt_hw_interrupt_enable
-rt_hw_interrupt_enable:
-    mtc0    a0, CP0_STATUS
-    jr      ra
-    nop
-
-/*
- * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to)
- * a0 --> from
- * a1 --> to
- */
-    .globl rt_hw_context_switch
-rt_hw_context_switch:
-    mtc0    ra, CP0_EPC
-    SAVE_ALL
-
-    sw      sp, 0(a0)       /* store sp in preempted tasks TCB */
-    lw      sp, 0(a1)       /* get new task stack pointer */
-
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_to(rt_uint32 to)/*
- * a0 --> to
- */
-    .globl rt_hw_context_switch_to
-rt_hw_context_switch_to:
-    lw      sp, 0(a0)       /* get new task stack pointer */
-
-    RESTORE_ALL_AND_RET
-
-/*
- * void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to)/*
- */
-    .globl rt_thread_switch_interrupt_flag
-    .globl rt_interrupt_from_thread
-    .globl rt_interrupt_to_thread
-    .globl rt_hw_context_switch_interrupt
-rt_hw_context_switch_interrupt:
-    la      t0, rt_thread_switch_interrupt_flag
-    lw      t1, 0(t0)
-    nop
-    bnez    t1, _reswitch
-    nop
-    li      t1, 0x01                       /* set rt_thread_switch_interrupt_flag to 1 */
-    sw      t1, 0(t0)
-    la      t0, rt_interrupt_from_thread   /* set rt_interrupt_from_thread */
-    sw      a0, 0(t0)
-_reswitch:
-    la      t0, rt_interrupt_to_thread     /* set rt_interrupt_to_thread */
-    sw      a1, 0(t0)
-    jr      ra
-    nop
-
-/*
- * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
- */
-    .globl rt_interrupt_enter
-    .globl rt_interrupt_leave
-    .globl mips_irq_handle
-mips_irq_handle:
-    SAVE_ALL
-
-    mfc0    t0, CP0_CAUSE
-    and     t1, t0, 0xff
-	bnez	t1, spurious_interrupt		/* check exception */
-	nop
-
-	/* let k0 keep the current context sp */
-    move    k0, sp 
-    /* switch to kernel stack */
-    li      sp, SYSTEM_STACK
-
-    jal     rt_interrupt_enter
-    nop
-    jal     rt_interrupt_dispatch
-    nop
-    jal     rt_interrupt_leave
-    nop
-
-    /* switch sp back to thread's context */
-    move    sp, k0
-
-    /*
-     * if rt_thread_switch_interrupt_flag set, jump to
-     * rt_hw_context_switch_interrupt_do and don't return
-     */
-    la      k0, rt_thread_switch_interrupt_flag
-    lw      k1, 0(k0)
-    beqz    k1, spurious_interrupt
-    nop
-    sw      zero, 0(k0)                     /* clear flag */
-	nop
-
-    /*
-     * switch to the new thread
-     */
-    la      k0, rt_interrupt_from_thread
-    lw      k1, 0(k0)
-    nop
-    sw      sp, 0(k1)                       /* store sp in preempted tasks's TCB */
-
-    la      k0, rt_interrupt_to_thread
-    lw      k1, 0(k0)
-    nop
-    lw      sp, 0(k1)                       /* get new task's stack pointer */
-    j       spurious_interrupt
-    nop
-
-spurious_interrupt:
-    RESTORE_ALL_AND_RET
-
-    .set reorder
diff --git a/libcpu/mips/loongson/cpu.c b/libcpu/mips/loongson/cpu.c
deleted file mode 100644
index c459061f0a..0000000000
--- a/libcpu/mips/loongson/cpu.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * File      : cpu.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-07-09     Bernard      first version
- * 2010-09-11     Bernard      add CPU reset implementation
- */
-#include <rtthread.h>
-#include <soc3210.h>
-
-/**
- * @addtogroup Loongson SoC3210
- */
-
-/*@{*/
-
-/**
- * this function will reset CPU
- *
- */
-void rt_hw_cpu_reset(void)
-{
-	/* open the watch-dog */
-	WD_TIMER = 0x01; /* watch dog will be timeout after 1 tick */
-	WD_CTRL |= 0x01;
-
-	rt_kprintf("reboot system...\n");
-	while (1);
-}
-
-/**
- * this function will shutdown CPU
- *
- */
-void rt_hw_cpu_shutdown(void)
-{
-	rt_kprintf("shutdown...\n");
-
-	while (1);
-}
-
-/*@}*/
-
diff --git a/libcpu/mips/loongson/exception.c b/libcpu/mips/loongson/exception.c
deleted file mode 100644
index 1c6aec53ac..0000000000
--- a/libcpu/mips/loongson/exception.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * File      : exception.c
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- */
-#include <rtthread.h>
-#include <rthw.h>
-#include "../common/exception.h"
-#include "../common/mipsregs.h"
-
-/**
- * @addtogroup SoC3210
- */
-/*@{*/
-
-/**
- * exception handle table
- */
-#define RT_EXCEPTION_MAX	8
-exception_func_t sys_exception_handlers[RT_EXCEPTION_MAX];
-
-/**
- * setup the exception handle
- */
-exception_func_t rt_set_except_vector(int n, exception_func_t func)
-{
-    exception_func_t old_handler = sys_exception_handlers[n];
-
-    if ((n == 0) || (n > RT_EXCEPTION_MAX) || (!func))
-    {
-        return 0;
-    }
-
-    sys_exception_handlers[n] = func;
-
-    return old_handler;
-}
-
-void tlb_refill_handler(void)
-{
-	rt_kprintf("tlb-miss happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-void cache_error_handler(void)
-{
-	rt_kprintf("cache exception happens, epc: 0x%08x\n", read_c0_epc());
-	rt_hw_cpu_shutdown();
-}
-
-static void unhandled_exception_handle(pt_regs_t *regs)
-{
-	rt_kprintf("exception happens, epc: 0x%08x, cause: 0x%08x\n", regs->cp0_epc, read_c0_cause());
-}
-
-void install_default_execpt_handle(void)
-{
-	rt_int32_t i;
-
-	for (i=0; i<RT_EXCEPTION_MAX; i++)
-		sys_exception_handlers[i] = (exception_func_t)unhandled_exception_handle;
-}
-
-void exception_handler(pt_regs_t *regs)
-{
-	rt_uint32_t cause;
-	rt_uint32_t index;
-
-	cause = (read_c0_cause() & read_c0_config());
-	cause = (cause & 0xfc00) >> 8;
-
-	for (index = RT_EXCEPTION_MAX; index > 0; index --)
-	{
-		if (cause & (1 << index))
-		{
-			sys_exception_handlers[index](regs);
-			cause &= ~(1 << index);
-		}
-	}
-}
-
-/*@}*/
diff --git a/libcpu/mips/loongson/interrupt.c b/libcpu/mips/loongson/interrupt.c
deleted file mode 100644
index 7e59ec950d..0000000000
--- a/libcpu/mips/loongson/interrupt.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * File      : interrupt.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-10-15     Bernard      first version
- * 2013-03-29     aozima       Modify the interrupt interface implementations.
- */
-
-#include <rtthread.h>
-#include <rthw.h>
-#include "soc3210.h"
-
-#define MAX_INTR 32
-
-extern rt_uint32_t rt_interrupt_nest;
-rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
-rt_uint32_t rt_thread_switch_interrupt_flag;
-
-static struct rt_irq_desc irq_handle_table[MAX_INTR];
-void rt_interrupt_dispatch(void *ptreg);
-void rt_hw_timer_handler();
-
-/**
- * @addtogroup Loongson SoC3210
- */
-
-/*@{*/
-
-static void rt_hw_interrupt_handler(int vector, void *param)
-{
-	rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
-}
-
-/**
- * This function will initialize hardware interrupt
- */
-void rt_hw_interrupt_init(void)
-{
-	rt_int32_t idx;
-
-    rt_memset(irq_handle_table, 0x00, sizeof(irq_handle_table));
-	for (idx = 0; idx < MAX_INTR; idx ++)
-	{
-		irq_handle_table[idx].handler = rt_hw_interrupt_handler;
-	}
-
-	/* init interrupt nest, and context in thread sp */
-	rt_interrupt_nest = 0;
-	rt_interrupt_from_thread = 0;
-	rt_interrupt_to_thread = 0;
-	rt_thread_switch_interrupt_flag = 0;
-}
-
-/**
- * This function will mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_mask(int vector)
-{
-	/* mask interrupt */
-	INT_EN &= ~(1 << vector);
-}
-
-/**
- * This function will un-mask a interrupt.
- * @param vector the interrupt number
- */
-void rt_hw_interrupt_umask(int vector)
-{
-	INT_EN |= (1 << vector);
-}
-
-/**
- * This function will install a interrupt service routine to a interrupt.
- * @param vector the interrupt number
- * @param new_handler the interrupt service routine to be installed
- * @param old_handler the old interrupt service routine
- */
-rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
-        void *param, char *name)
-{
-    rt_isr_handler_t old_handler = RT_NULL;
-
-    if(vector < MAX_INTR)
-    {
-        old_handler = irq_handle_table[vector].handler;
-
-        if (handler != RT_NULL)
-        {
-#ifdef RT_USING_INTERRUPT_INFO
-		    rt_strncpy(irq_handle_table[vector].name, name, RT_NAME_MAX);
-#endif /* RT_USING_INTERRUPT_INFO */
-		    irq_handle_table[vector].handler = handler;
-            irq_handle_table[vector].param = param;
-        }
-    }
-
-    return old_handler;
-}
-
-void rt_interrupt_dispatch(void *ptreg)
-{
-    int irq;
-    void *param;
-    rt_isr_handler_t irq_func;
-    static rt_uint32_t status = 0;
-    rt_uint32_t c0_status;
-
-    /* check os timer */
-    c0_status = read_c0_status();
-    if (c0_status & 0x8000)
-    {
-        rt_hw_timer_handler();
-    }
-
-    if (c0_status & 0x0400)
-    {
-        /* the hardware interrupt */
-        status |= INT_ISR;
-        if (!status) return;
-
-        for (irq = MAX_INTR; irq > 0; --irq)
-        {
-            if ((status & (1 << irq)))
-            {
-                status &= ~(1 << irq);
-
-                irq_func = irq_handle_table[irq].handler;
-                param = irq_handle_table[irq].param;
-
-                /* do interrupt */
-                (*irq_func)(irq, param);
-
-#ifdef RT_USING_INTERRUPT_INFO
-                irq_handle_table[irq].counter++;
-#endif /* RT_USING_INTERRUPT_INFO */
-
-                /* ack interrupt */
-                INT_CLR = (1 << irq);
-            }
-        }
-    }
-}
-
-/*@}*/
diff --git a/libcpu/mips/loongson/mipscfg.c b/libcpu/mips/loongson/mipscfg.c
deleted file mode 100644
index 8a96f458ab..0000000000
--- a/libcpu/mips/loongson/mipscfg.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * File      : mipscfg.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2010, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-27     swkyer       first version
- */
-#include <rtthread.h>
-#include "../common/mipsregs.h"
-#include "../common/mipscfg.h"
-
-mips32_core_cfg_t g_mips_core =
-{
-	16,		/* icache_line_size */
-	256,	/* icache_lines_per_way */
-	4,		/* icache_ways */
-	16,		/* dcache_line_size */
-	256,	/* dcache_lines_per_way */
-	4,		/* dcache_ways */
-	16,		/* max_tlb_entries */
-};
-
-static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
-{
-	rt_uint16_t rets = 1;
-
-    while (n--)
-        rets *= b;
-
-    return rets;
-}
-
-static rt_uint16_t m_log2(rt_uint16_t b)
-{
-	rt_uint16_t rets = 0;
-
-    while (b != 1)
-    {
-        b /= 2;
-        rets++;
-    }
-
-    return rets;
-}
-
-/**
- * read core attribute
- */
-void mips32_cfg_init(void)
-{
-	rt_uint16_t val;
-	rt_uint32_t cp0_config1;
-
-	cp0_config1 = read_c0_config();
-	if (cp0_config1 & 0x80000000)
-	{
-		cp0_config1 = read_c0_config1();
-
-		val = (cp0_config1 & (7<<22))>>22;
-		g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<19))>>19;
-		g_mips_core.icache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<16))>>16;
-		g_mips_core.icache_ways = val + 1;
-
-		val = (cp0_config1 & (7<<13))>>13;
-		g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
-		val = (cp0_config1 & (7<<10))>>10;
-		g_mips_core.dcache_line_size = 2 * m_pow(2, val);
-		val = (cp0_config1 & (7<<7))>>7;
-		g_mips_core.dcache_ways = val + 1;
-
-		val = (cp0_config1 & (0x3F<<25))>>25;
-		g_mips_core.max_tlb_entries = val + 1;
-	}
-}
diff --git a/libcpu/mips/loongson/soc3210.h b/libcpu/mips/loongson/soc3210.h
deleted file mode 100644
index c4d2c3926f..0000000000
--- a/libcpu/mips/loongson/soc3210.h
+++ /dev/null
@@ -1,172 +0,0 @@
-#ifndef __SOC3210_H__
-#define __SOC3210_H__
-
-#include "../common/mipsregs.h"
-
-/* registers */
-#define __REG8(addr)		*((volatile unsigned char *)(addr))
-#define __REG16(addr)		*((volatile unsigned short *)(addr))
-#define __REG32(addr)		*((volatile unsigned int *)(addr))
-
-#define EMI_BASE			0xBF000000
-#define NN_BASE				0xBF000040
-#define LCD_BASE			0xBF001000
-#define HSB_MISC_BASE		0xBF003200
-#define SPI_BASE			0xBF004000
-#define PS2_BASE			0xBF004040
-#define UART0_BASE			0xBF004080
-#define UART1_BASE			0xBF004090
-#define I2C_BASE			0xBF0040D0
-#define LPB_MISC_BASE		0xBF004100
-#define AC97_BASE			0xBF004200
-#define AC97_DMA_BASE		0xBF004280
-#define CAN1_BASE			0xBF004300
-#define CAN0_BASE			0xBF004400
-#define MAC0_BASE			0xBF005200
-#define MAC1_BASE			0xBF005300
-
-/* LCD registers */
-#define LCD_CTRL			__REG32(LCD_BASE + 0x000)
-#define LCD_STAT			__REG32(LCD_BASE + 0x004)
-#define LCD_HTIM			__REG32(LCD_BASE + 0x008)
-#define LCD_VTIM			__REG32(LCD_BASE + 0x00C)
-#define LCD_HVLEN			__REG32(LCD_BASE + 0x010)
-#define LCD_VBARA			__REG32(LCD_BASE + 0x014)
-#define LCD_VBARB			__REG32(LCD_BASE + 0x018)
-#define LCD_PCLT			__REG32(LCD_BASE + 0x800)
-
-/* HSB misc registers */
-#define HSB_MISC_REG		__REG32(HSB_MISC_BASE + 0x00)
-#define INT_EDGE			__REG32(HSB_MISC_BASE + 0x04)
-#define INT_STEER			__REG32(HSB_MISC_BASE + 0x08)
-#define INT_POL				__REG32(HSB_MISC_BASE + 0x0C)
-#define INT_SET				__REG32(HSB_MISC_BASE + 0x10)
-#define INT_CLR				__REG32(HSB_MISC_BASE + 0x14)
-#define INT_EN				__REG32(HSB_MISC_BASE + 0x18)
-#define INT_ISR				__REG32(HSB_MISC_BASE + 0x1C)
-#define GPIO_OE_60_29		__REG32(HSB_MISC_BASE + 0x20)
-#define GPIO_I_60_29		__REG32(HSB_MISC_BASE + 0x24)
-#define GPIO_O_60_29		__REG32(HSB_MISC_BASE + 0x28)
-#define HSB_ARB_CFG			__REG32(HSB_MISC_BASE + 0x2C)
-#define WD_TIMER			__REG32(HSB_MISC_BASE + 0x30)
-#define WD_CTRL				__REG32(HSB_MISC_BASE + 0x34)
-
-/* SPI registers */
-#define SPI_SPCR			__REG8(SPI_BASE + 0x00)
-#define SPI_SPSR			__REG8(SPI_BASE + 0x01)
-#define SPI_TX_FIFO			__REG8(SPI_BASE + 0x02)
-#define SPI_SPER			__REG8(SPI_BASE + 0x03)
-
-/* PS/2 registers */
-#define PS2_RIBUF			__REG8(PS2_BASE + 0x00)
-#define PS2_WOBUF			__REG8(PS2_BASE + 0x00)
-#define PS2_RSR				__REG8(PS2_BASE + 0x04)
-#define PS2_WSC				__REG8(PS2_BASE + 0x04)
-#define PS2_DLL				__REG8(PS2_BASE + 0x08)
-#define PS2_DLH				__REG8(PS2_BASE + 0x09)
-#define PS2_DL_KBD			__REG8(PS2_BASE + 0x0A)
-#define PS2_DL_AUX			__REG8(PS2_BASE + 0x0B)
-
-/* UART registers */
-#define UART_DAT(base)		__REG8(base + 0x00)
-#define UART_IER(base)		__REG8(base + 0x01)
-#define UART_IIR(base)		__REG8(base + 0x02)
-#define UART_FCR(base)		__REG8(base + 0x02)
-#define UART_LCR(base)		__REG8(base + 0x03)
-#define UART_MCR(base)		__REG8(base + 0x04)
-#define UART_LSR(base)		__REG8(base + 0x05)
-#define UART_MSR(base)		__REG8(base + 0x06)
-
-#define UART_LSB(base)		__REG8(base + 0x00)
-#define UART_MSB(base)		__REG8(base + 0x01)
-
-/* UART0 registers */
-#define UART0_DAT			__REG8(UART0_BASE + 0x00)
-#define UART0_IER			__REG8(UART0_BASE + 0x01)
-#define UART0_IIR			__REG8(UART0_BASE + 0x02)
-#define UART0_FCR			__REG8(UART0_BASE + 0x02)
-#define UART0_LCR			__REG8(UART0_BASE + 0x03)
-#define UART0_MCR			__REG8(UART0_BASE + 0x04)
-#define UART0_LSR			__REG8(UART0_BASE + 0x05)
-#define UART0_MSR			__REG8(UART0_BASE + 0x06)
-
-#define UART0_LSB			__REG8(UART0_BASE + 0x00)
-#define UART0_MSB			__REG8(UART0_BASE + 0x01)
-
-/* UART1 registers */
-#define UART1_DAT			__REG8(UART1_BASE + 0x00)
-#define UART1_IER			__REG8(UART1_BASE + 0x01)
-#define UART1_IIR			__REG8(UART1_BASE + 0x02)
-#define UART1_FCR			__REG8(UART1_BASE + 0x02)
-#define UART1_LCR			__REG8(UART1_BASE + 0x03)
-#define UART1_MCR			__REG8(UART1_BASE + 0x04)
-#define UART1_LSR			__REG8(UART1_BASE + 0x05)
-#define UART1_MSR			__REG8(UART1_BASE + 0x06)
-
-#define UART1_LSB			__REG8(UART1_BASE + 0x00)
-#define UART1_MSB			__REG8(UART1_BASE + 0x01)
-
-/* LPB misc registers */
-#define GPIO_OE_7_0			__REG8(LPB_MISC_BASE + 0x00)
-#define GPIO_OE_15_8		__REG8(LPB_MISC_BASE + 0x01)
-#define GPIO_OE_23_16		__REG8(LPB_MISC_BASE + 0x02)
-#define GPIO_OE_28_24		__REG8(LPB_MISC_BASE + 0x03)
-#define GPIO_I_7_0			__REG8(LPB_MISC_BASE + 0x10)
-#define GPIO_I_15_8			__REG8(LPB_MISC_BASE + 0x11)
-#define GPIO_I_23_16		__REG8(LPB_MISC_BASE + 0x12)
-#define GPIO_I_28_24		__REG8(LPB_MISC_BASE + 0x13)
-#define GPIO_O_7_0			__REG8(LPB_MISC_BASE + 0x20)
-#define GPIO_O_15_8			__REG8(LPB_MISC_BASE + 0x21)
-#define GPIO_O_23_16		__REG8(LPB_MISC_BASE + 0x22)
-#define GPIO_O_28_24		__REG8(LPB_MISC_BASE + 0x23)
-#define LPB_MISC_CFG		__REG8(LPB_MISC_BASE + 0x40)
-
-/* MAC0 registers */
-#define MAC0_BUS_MODE		__REG32(MAC0_BASE + 0x00)
-#define MAC0_TX_POLL_REQ	__REG32(MAC0_BASE + 0x08)
-#define MAC0_RX_POLL_REQ	__REG32(MAC0_BASE + 0x10)
-#define MAC0_RX_LIST_BASE_ADDR	__REG32(MAC0_BASE + 0x18)
-#define MAC0_TX_LIST_BASE_ADDR	__REG32(MAC0_BASE + 0x20)
-#define MAC0_STATUS			__REG32(MAC0_BASE + 0x28)
-#define MAC0_OP_MODE		__REG32(MAC0_BASE + 0x30)
-#define MAC0_INTERRUPT_EN	__REG32(MAC0_BASE + 0x38)
-#define MAC0_MISSED_FRAME_STATISTIC	__REG32(MAC0_BASE + 0x40)
-#define MAC0_SMI_EEPROM_CTL	__REG32(MAC0_BASE + 0x48)
-#define MAC0_BYTE_ALIGN		__REG32(MAC0_BASE + 0x50)
-#define MAC0_GPT_IM_CTL		__REG32(MAC0_BASE + 0x58)
-
-/* MAC1 registers */
-#define MAC1_BUS_MODE		__REG32(MAC1_BASE + 0x00)
-#define MAC1_TX_POLL_REQ	__REG32(MAC1_BASE + 0x08)
-#define MAC1_RX_POLL_REQ	__REG32(MAC1_BASE + 0x10)
-#define MAC1_RX_LIST_BASE_ADDR	__REG32(MAC1_BASE + 0x18)
-#define MAC1_TX_LIST_BASE_ADDR	__REG32(MAC1_BASE + 0x20)
-#define MAC1_STATUS			__REG32(MAC1_BASE + 0x28)
-#define MAC1_OP_MODE		__REG32(MAC1_BASE + 0x30)
-#define MAC1_INTERRUPT_EN	__REG32(MAC1_BASE + 0x38)
-#define MAC1_MISSED_FRAME_STATISTIC	__REG32(MAC1_BASE + 0x40)
-#define MAC1_SMI_EEPROM_CTL	__REG32(MAC1_BASE + 0x48)
-#define MAC1_BYTE_ALIGN		__REG32(MAC1_BASE + 0x50)
-#define MAC1_GPT_IM_CTL		__REG32(MAC1_BASE + 0x58)
-
-/* Peripheral Interrupt Number */
-#define IRQ_LCD				0
-#define IRQ_MAC1			1
-#define IRQ_MAC2			2
-#define IRQ_AC97			3
-#define IRQ_SPI				8
-#define IRQ_KEY				9
-#define IRQ_MOUSE			10
-#define IRQ_UART0			11
-#define IRQ_UART1			12
-#define IRQ_I2C				13
-#define IRQ_CAN0			14
-#define IRQ_CAN1			15
-#define IRQ_GPIO15			20
-#define IRQ_GPIO14			21
-#define IRQ_GPIO13			22
-#define IRQ_GPIO12			23
-
-#define SYSTEM_STACK		0x80003fe8		/* the kernel system stack address */
-
-#endif
diff --git a/libcpu/mips/loongson/stack.c b/libcpu/mips/loongson/stack.c
deleted file mode 100644
index dbfcf7ea91..0000000000
--- a/libcpu/mips/loongson/stack.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * File      : stack.c
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006, RT-Thread Development Team
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
- *
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-07-07     Bernard      porting to Jz47xx
- */
- 
-#include <rtthread.h>
-
-/**
- * @addtogroup Loongson SoC3210
- */
-
-/*@{*/
-
-extern rt_uint32_t cp0_get_cause(void);
-extern rt_uint32_t cp0_get_status(void);
-extern rt_uint32_t cp0_get_hi(void);
-extern rt_uint32_t cp0_get_lo(void);
-
-/**
- * This function will initialize thread stack
- *
- * @param tentry the entry of thread
- * @param parameter the parameter of entry
- * @param stack_addr the beginning stack address
- * @param texit the function will be called when thread exit
- *
- * @return stack address
- */
-rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit)
-{
-	rt_uint32_t *stk;
-    static rt_uint32_t g_sr = 0;
-
-    if (g_sr == 0)
-    {
-    	g_sr = cp0_get_status();
-    	g_sr &= 0xfffffffe;
-    	g_sr |= 0x8401;
-    }
-
-    /** Start at stack top */
-    stk = (rt_uint32_t *)stack_addr;
-	*(stk)   = (rt_uint32_t) tentry;        /* pc: Entry Point */
-	*(--stk) = (rt_uint32_t) 0xeeee; 		/* c0_cause */
-	*(--stk) = (rt_uint32_t) 0xffff;		/* c0_badvaddr */
-	*(--stk) = (rt_uint32_t) cp0_get_lo();	/* lo */
-	*(--stk) = (rt_uint32_t) cp0_get_hi();	/* hi */
-	*(--stk) = (rt_uint32_t) g_sr; 			/* C0_SR: HW2 = En, IE = En */
-	*(--stk) = (rt_uint32_t) texit;	        /* ra */
-	*(--stk) = (rt_uint32_t) 0x0000001e;	/* s8 */
-	*(--stk) = (rt_uint32_t) stack_addr;	/* sp */
-	*(--stk) = (rt_uint32_t) 0x0000001c;	/* gp */
-	*(--stk) = (rt_uint32_t) 0x0000001b;	/* k1 */
-	*(--stk) = (rt_uint32_t) 0x0000001a;	/* k0 */
-	*(--stk) = (rt_uint32_t) 0x00000019;	/* t9 */
-	*(--stk) = (rt_uint32_t) 0x00000018;	/* t8 */
-	*(--stk) = (rt_uint32_t) 0x00000017;	/* s7 */
-	*(--stk) = (rt_uint32_t) 0x00000016;	/* s6 */
-	*(--stk) = (rt_uint32_t) 0x00000015;	/* s5 */
-	*(--stk) = (rt_uint32_t) 0x00000014;	/* s4 */
-	*(--stk) = (rt_uint32_t) 0x00000013;	/* s3 */
-	*(--stk) = (rt_uint32_t) 0x00000012;	/* s2 */
-	*(--stk) = (rt_uint32_t) 0x00000011;	/* s1 */
-	*(--stk) = (rt_uint32_t) 0x00000010;	/* s0 */
-	*(--stk) = (rt_uint32_t) 0x0000000f;	/* t7 */
-	*(--stk) = (rt_uint32_t) 0x0000000e;	/* t6 */
-	*(--stk) = (rt_uint32_t) 0x0000000d;	/* t5 */
-	*(--stk) = (rt_uint32_t) 0x0000000c;	/* t4 */
-	*(--stk) = (rt_uint32_t) 0x0000000b;	/* t3 */
-	*(--stk) = (rt_uint32_t) 0x0000000a; 	/* t2 */
-	*(--stk) = (rt_uint32_t) 0x00000009;	/* t1 */
-	*(--stk) = (rt_uint32_t) 0x00000008;	/* t0 */
-	*(--stk) = (rt_uint32_t) 0x00000007;	/* a3 */
-	*(--stk) = (rt_uint32_t) 0x00000006;	/* a2 */
-	*(--stk) = (rt_uint32_t) 0x00000005;	/* a1 */
-	*(--stk) = (rt_uint32_t) parameter;	    /* a0 */
-	*(--stk) = (rt_uint32_t) 0x00000003;	/* v1 */
-	*(--stk) = (rt_uint32_t) 0x00000002;	/* v0 */
-	*(--stk) = (rt_uint32_t) 0x00000001;	/* at */
-	*(--stk) = (rt_uint32_t) 0x00000000;	/* zero */
-
-	/* return task's current stack address */
-	return (rt_uint8_t *)stk;
-}
-
-/*@}*/
diff --git a/libcpu/mips/loongson/start_gcc.S b/libcpu/mips/loongson/start_gcc.S
deleted file mode 100644
index 2b0ef3a39b..0000000000
--- a/libcpu/mips/loongson/start_gcc.S
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * File      : start_gcc.S
- * Change Logs:
- * Date           Author       Notes
- * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      porting to Jz47xx
- */
-
-#include "../common/mips.inc"
-#include "../common/stackframe.h"
-#include "soc3210.h"
-
-    .section ".start", "ax"
-    .set noreorder
-
-    /* the program entry */
-    .globl  _start
-_start:
-    .set    noreorder
-    la      ra, _start
-
-	/* disable interrupt */
-	mfc0	t0, CP0_STATUS
-	and 	t0, 0xfffffffe	# By default it will be disabled.
-	mtc0	t0, CP0_STATUS	# Set CPU to disable interrupt.
-	nop
-
-	/* disable cache */
-	mfc0	t0, CP0_CONFIG
-	and		t0, 0xfffffff8
-	or		t0, 0x2			# disable,!default value is not it!
-	mtc0	t0, CP0_CONFIG	# Set CPU to disable cache.
-	nop
-
-    /* setup stack pointer */
-    li      sp, SYSTEM_STACK
-    la      gp, _gp
-
-    /* clear bss */
-    la      t0, __bss_start
-    la      t1, __bss_end
-_clr_bss_loop:
-    sw      zero, 0(t0)
-    bne     t0, t1, _clr_bss_loop
-    addiu   t0, t0, 4
-
-    /* jump to RT-Thread RTOS */
-    jal     rtthread_startup
-    nop
-
-    /* restart, never die */
-    j       _start
-    nop
-    .set    reorder
-
-    .globl  cp0_get_cause
-cp0_get_cause:
-    mfc0    v0, CP0_CAUSE
-    jr      ra
-    nop
-
-    .globl  cp0_get_status
-cp0_get_status:
-    mfc0    v0, CP0_STATUS
-    jr      ra
-    nop
-
-    .globl  cp0_get_hi
-cp0_get_hi:
-    mfhi    v0
-    jr      ra
-    nop
-
-    .globl  cp0_get_lo
-cp0_get_lo:
-    mflo    v0
-    jr      ra
-    nop
-
-	.extern tlb_refill_handler
-	.extern cache_error_handler
-
-	/* Exception Handler */
-	/* 0x0 - TLB refill handler */
-    .section .vectors.1, "ax", %progbits
-	.global tlb_refill_exception
-	.type	tlb_refill_exception,@function
-tlb_refill_exception:
-    j      tlb_refill_handler
-    nop
-	
-	/* 0x100 - Cache error handler */
-    .section .vectors.2, "ax", %progbits
-    j      cache_error_handler
-    nop
-    
-	/* 0x180 - Exception/Interrupt handler */
-    .section .vectors.3, "ax", %progbits
-	.global general_exception
-	.type	general_exception,@function
-general_exception:
-    j      _general_exception_handler
-    nop
-    
-	/* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
-    .section .vectors.4, "ax", %progbits
-	.global irq_exception
-	.type	irq_exception,@function
-irq_exception:
-    j      _irq_handler
-    nop
-	
-    .section .vectors, "ax", %progbits
-	.extern mips_irq_handle
-
-    /* general exception handler */
-_general_exception_handler:
-    .set    noreorder
-    la      k0, mips_irq_handle
-    jr      k0
-    nop
-    .set    reorder
-
-    /* interrupt handler */
-_irq_handler:
-    .set    noreorder
-    la      k0, mips_irq_handle
-    jr      k0
-    nop
-    .set    reorder