diff options
| author | bigmagic <[email protected]> | 2020-02-26 15:32:44 +0800 |
|---|---|---|
| committer | bigmagic <[email protected]> | 2020-02-26 15:35:07 +0800 |
| commit | 773f7cdf52f3ca8c778186699560bcfe7fffc9e3 (patch) | |
| tree | e688a6fb521ee6ba5ccf7d55dad8ea7efb6cd82a /libcpu | |
| parent | b6031497b9c6cb0b0b6aec8dd465e92dea1ee430 (diff) | |
[bsp/raspi3-64]add core timer driver
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/aarch64/cortex-a53/context_gcc.S | 25 | ||||
| -rw-r--r-- | libcpu/aarch64/cortex-a53/trap.c | 49 |
2 files changed, 38 insertions, 36 deletions
diff --git a/libcpu/aarch64/cortex-a53/context_gcc.S b/libcpu/aarch64/cortex-a53/context_gcc.S index f58ea1b15d..f9052d2201 100644 --- a/libcpu/aarch64/cortex-a53/context_gcc.S +++ b/libcpu/aarch64/cortex-a53/context_gcc.S @@ -8,6 +8,31 @@ * 2018-10-06 ZhaoXiaowei the first version */ + /* + *enable gtimer + */ +.globl rt_hw_gtimer_enable +rt_hw_gtimer_enable: + MOV X0,#1 + MSR CNTP_CTL_EL0,X0 + RET + +/* + *set gtimer CNTP_TVAL_EL0 value + */ +.globl rt_hw_set_gtimer_val +rt_hw_set_gtimer_val: + MSR CNTP_TVAL_EL0,X0 + RET + +/* + *get gtimer frq value + */ +.globl rt_hw_get_gtimer_frq +rt_hw_get_gtimer_frq: + MRS X0,CNTFRQ_EL0 + RET + .macro SAVE_CONTEXT /* Switch to use the EL0 stack pointer. */ diff --git a/libcpu/aarch64/cortex-a53/trap.c b/libcpu/aarch64/cortex-a53/trap.c index 1c99970d8f..41d4d620f6 100644 --- a/libcpu/aarch64/cortex-a53/trap.c +++ b/libcpu/aarch64/cortex-a53/trap.c @@ -56,7 +56,8 @@ void rt_hw_trap_error(struct rt_hw_exp_stack *regs) rt_hw_cpu_shutdown(); } -#define GIC_ACK_INTID_MASK 0x000003ff +#define GIC_ACK_INTID_MASK (0x000003ff) +#define CORE0_IRQ_SOURCE (0x40000060) void rt_hw_trap_irq(void) { @@ -66,43 +67,19 @@ void rt_hw_trap_irq(void) extern struct rt_irq_desc isr_table[]; uint32_t value = 0; value = IRQ_PEND_BASIC & 0x3ff; -#ifdef RT_USING_SMP - uint32_t mailbox_data; - uint32_t cpu_id = rt_hw_cpu_id(); - uint32_t int_source = CORE_IRQSOURCE(cpu_id); - mailbox_data = IPI_MAILBOX_CLEAR(cpu_id); - if (int_source & 0x0f) +#ifdef BSP_USING_CORETIMER + uint32_t int_source = HWREG32(CORE0_IRQ_SOURCE) & 0x3ff; + if (int_source & 0x02) { - if (int_source & 0x08){ - isr_func = isr_table[IRQ_ARM_TIMER].handler; -#ifdef RT_USING_INTERRUPT_INFO - isr_table[IRQ_ARM_TIMER].counter++; -#endif - if (isr_func) - { - param = isr_table[IRQ_ARM_TIMER].param; - isr_func(IRQ_ARM_TIMER, param); - } - } - } - if (int_source & 0xf0) - { - /*it's a ipi interrupt*/ - if (mailbox_data & 0x1){ - /* clear mailbox */ - IPI_MAILBOX_CLEAR(cpu_id) = mailbox_data; - isr_func = isr_table[IRQ_ARM_MAILBOX].handler; -#ifdef RT_USING_INTERRUPT_INFO - isr_table[IRQ_ARM_MAILBOX].counter++; -#endif - if (isr_func) - { - param = isr_table[IRQ_ARM_MAILBOX].param; - isr_func(IRQ_ARM_MAILBOX, param); - } + isr_func = isr_table[IRQ_ARM_TIMER].handler; + #ifdef RT_USING_INTERRUPT_INFO + isr_table[IRQ_ARM_TIMER].counter++; + #endif + if (isr_func) + { + param = isr_table[IRQ_ARM_TIMER].param; + isr_func(IRQ_ARM_TIMER, param); } - else - CORE_MAILBOX3_CLEAR(cpu_id) = mailbox_data; } #endif /* local interrupt*/ |