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author勤为本 <[email protected]>2017-08-23 15:46:51 +0800
committer勤为本 <[email protected]>2017-08-23 15:46:51 +0800
commit838c63f3651c2dab2f90e3f30e09c86faeccb9fd (patch)
treecd642009b1460699629d66b9c9c4f449a5ad7563 /libcpu
parent7129d77bee6e1016f849290dbd5aa33874548486 (diff)
添加龙芯1C片内网卡的驱动(原创作者是chinesebear,https://github.com/chinesebear/rtt-net)
Diffstat (limited to 'libcpu')
-rw-r--r--libcpu/mips/loongson_1c/cpuport.c36
1 files changed, 36 insertions, 0 deletions
diff --git a/libcpu/mips/loongson_1c/cpuport.c b/libcpu/mips/loongson_1c/cpuport.c
index 6cdae024c4..f4914dfec4 100644
--- a/libcpu/mips/loongson_1c/cpuport.c
+++ b/libcpu/mips/loongson_1c/cpuport.c
@@ -121,5 +121,41 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_ad
return (rt_uint8_t *)stk;
}
+#define cache_op(op,addr) \
+ __asm__ __volatile__( \
+ " .set push \n" \
+ " .set noreorder \n" \
+ " .set mips3\n\t \n" \
+ " cache %0, %1 \n" \
+ " .set pop \n" \
+ : \
+ : "i" (op), "R" (*(unsigned char *)(addr)))
+
+#if defined(CONFIG_CPU_LOONGSON2)
+#define Hit_Invalidate_I 0x00
+#else
+#define Hit_Invalidate_I 0x10
+#endif
+#define Hit_Invalidate_D 0x11
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#define Hit_Writeback_Inv_D 0x15
+
+
+void flush_cache(unsigned long start_addr, unsigned long size)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(Hit_Invalidate_I, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+
/*@}*/