Merge pull request #7 from RT-Thread/master

sync

25 files changed, 380 insertions, 180 deletions

diff --git a/libcpu/arm/cortex-a/cache.c b/libcpu/arm/cortex-a/cache.c
index 6d28d9e9f9..30af86baa1 100644
--- a/libcpu/arm/cortex-a/cache.c
+++ b/libcpu/arm/cortex-a/cache.c
@@ -30,6 +30,7 @@ void rt_hw_cpu_icache_invalidate(void *addr, int size)
     rt_uint32_t start_addr = (rt_uint32_t)addr;
     rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
 
+    asm volatile ("dmb":::"memory");
     start_addr &= ~(line_size-1);
     end_addr &= ~(line_size-1);
     while (start_addr < end_addr)
@@ -37,6 +38,7 @@ void rt_hw_cpu_icache_invalidate(void *addr, int size)
         asm volatile ("mcr p15, 0, %0, c7, c5, 1" :: "r"(start_addr));  /* icimvau */
         start_addr += line_size;
     }
+    asm volatile ("dsb\n\tisb":::"memory");
 }
 
 void rt_hw_cpu_dcache_invalidate(void *addr, int size)
@@ -45,6 +47,7 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size)
     rt_uint32_t start_addr = (rt_uint32_t)addr;
     rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
 
+    asm volatile ("dmb":::"memory");
     start_addr &= ~(line_size-1);
     end_addr &= ~(line_size-1);
     while (start_addr < end_addr)
@@ -52,6 +55,7 @@ void rt_hw_cpu_dcache_invalidate(void *addr, int size)
         asm volatile ("mcr p15, 0, %0, c7, c6, 1" :: "r"(start_addr));  /* dcimvac */
         start_addr += line_size;
     }
+    asm volatile ("dsb":::"memory");
 }
 
 void rt_hw_cpu_dcache_clean(void *addr, int size)
@@ -60,6 +64,7 @@ void rt_hw_cpu_dcache_clean(void *addr, int size)
     rt_uint32_t start_addr = (rt_uint32_t)addr;
     rt_uint32_t end_addr = (rt_uint32_t) addr + size + line_size - 1;
 
+    asm volatile ("dmb":::"memory");
     start_addr &= ~(line_size-1);
     end_addr &= ~(line_size-1);
     while (start_addr < end_addr)
@@ -67,6 +72,7 @@ void rt_hw_cpu_dcache_clean(void *addr, int size)
         asm volatile ("mcr p15, 0, %0, c7, c10, 1" :: "r"(start_addr)); /* dccmvac */
         start_addr += line_size;
     }
+    asm volatile ("dsb":::"memory");
 }
 
 void rt_hw_cpu_icache_ops(int ops, void *addr, int size)
diff --git a/libcpu/arm/cortex-m3/cpuport.c b/libcpu/arm/cortex-m3/cpuport.c
index a386747750..0a948c528b 100644
--- a/libcpu/arm/cortex-m3/cpuport.c
+++ b/libcpu/arm/cortex-m3/cpuport.c
@@ -11,6 +11,7 @@
  * 2012-12-23   aozima      stack addr align to 8byte.
  * 2012-12-29   Bernard     Add exception hook.
  * 2013-07-09   aozima      enhancement hard fault exception handler.
+ * 2019-07-03   yangjie     add __rt_ffs() for armclang.
  */
 
 #include <rtthread.h>
@@ -382,6 +383,25 @@ __asm int __rt_ffs(int value)
 exit
     BX      lr
 }
+#elif defined(__CLANG_ARM)
+int __rt_ffs(int value)
+{
+    __asm volatile(
+        "CMP     r0, #0x00            \n"
+        "BEQ     exit                 \n"
+
+        "RBIT    r0, r0               \n"
+        "CLZ     r0, r0               \n"
+        "ADDS    r0, r0, #0x01        \n"
+
+        "exit:                        \n"
+        "BX      lr                   \n"
+
+        : "=r"(value)
+        : "r"(value)
+    );
+    return value;
+}
 #elif defined(__IAR_SYSTEMS_ICC__)
 int __rt_ffs(int value)
 {
diff --git a/libcpu/arm/cortex-m4/cpuport.c b/libcpu/arm/cortex-m4/cpuport.c
index 18f027895b..71a7fb16f9 100644
--- a/libcpu/arm/cortex-m4/cpuport.c
+++ b/libcpu/arm/cortex-m4/cpuport.c
@@ -14,6 +14,7 @@
  * 2012-12-29     Bernard      Add exception hook.
  * 2013-06-23     aozima       support lazy stack optimized.
  * 2018-07-24     aozima       enhancement hard fault exception handler.
+ * 2019-07-03     yangjie      add __rt_ffs() for armclang.
  */
 
 #include <rtthread.h>
@@ -453,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void)
  * @return return the index of the first bit set. If value is 0, then this function
  * shall return 0.
  */
-#if defined(__CC_ARM) || defined(__CLANG_ARM)
+#if defined(__CC_ARM) 
 __asm int __rt_ffs(int value)
 {
     CMP     r0, #0x00
@@ -466,6 +467,25 @@ __asm int __rt_ffs(int value)
 exit
     BX      lr
 }
+#elif defined(__CLANG_ARM)
+int __rt_ffs(int value)
+{
+    __asm volatile(
+        "CMP     r0, #0x00            \n"
+        "BEQ     exit                 \n"
+
+        "RBIT    r0, r0               \n"
+        "CLZ     r0, r0               \n"
+        "ADDS    r0, r0, #0x01        \n"
+
+        "exit:                        \n"
+        "BX      lr                   \n"
+
+        : "=r"(value)
+        : "r"(value)
+    );
+    return value;
+}
 #elif defined(__IAR_SYSTEMS_ICC__)
 int __rt_ffs(int value)
 {
diff --git a/libcpu/arm/cortex-m7/cpuport.c b/libcpu/arm/cortex-m7/cpuport.c
index 18f027895b..85960baede 100644
--- a/libcpu/arm/cortex-m7/cpuport.c
+++ b/libcpu/arm/cortex-m7/cpuport.c
@@ -14,6 +14,7 @@
  * 2012-12-29     Bernard      Add exception hook.
  * 2013-06-23     aozima       support lazy stack optimized.
  * 2018-07-24     aozima       enhancement hard fault exception handler.
+ * 2019-07-03     yangjie      add __rt_ffs() for armclang.
  */
 
 #include <rtthread.h>
@@ -453,7 +454,7 @@ RT_WEAK void rt_hw_cpu_reset(void)
  * @return return the index of the first bit set. If value is 0, then this function
  * shall return 0.
  */
-#if defined(__CC_ARM) || defined(__CLANG_ARM)
+#if defined(__CC_ARM)
 __asm int __rt_ffs(int value)
 {
     CMP     r0, #0x00
@@ -466,6 +467,25 @@ __asm int __rt_ffs(int value)
 exit
     BX      lr
 }
+#elif defined(__CLANG_ARM)
+int __rt_ffs(int value)
+{
+    __asm volatile(
+        "CMP     r0, #0x00            \n"
+        "BEQ     exit                 \n"
+
+        "RBIT    r0, r0               \n"
+        "CLZ     r0, r0               \n"
+        "ADDS    r0, r0, #0x01        \n"
+
+        "exit:                        \n"
+        "BX      lr                   \n"
+
+        : "=r"(value)
+        : "r"(value)
+    );
+    return value;
+}
 #elif defined(__IAR_SYSTEMS_ICC__)
 int __rt_ffs(int value)
 {
diff --git a/libcpu/mips/common/mips.h b/libcpu/mips/common/mips.h
index 6a9811ae7e..a4bc74a050 100644
--- a/libcpu/mips/common/mips.h
+++ b/libcpu/mips/common/mips.h
@@ -1,25 +1,11 @@
 /*
- * File      : mips.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
+ * 2016-09-07     Urey         first version
  */
 
 #ifndef _COMMON_MIPS_H_
diff --git a/libcpu/mips/common/mips_def.h b/libcpu/mips/common/mips_def.h
index 70da2deccf..1727684f50 100644
--- a/libcpu/mips/common/mips_def.h
+++ b/libcpu/mips/common/mips_def.h
@@ -1,25 +1,11 @@
 /*
- * File      : mips_def.h
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
+ * 2016-09-07     Urey         first version
  */
 
 #ifndef _COMMON_MIPS_DEF_H_
diff --git a/libcpu/mips/loongson_1b/cache_gcc.S b/libcpu/mips/loongson_1b/cache_gcc.S
index bb6f46de4c..1e718c9883 100644
--- a/libcpu/mips/loongson_1b/cache_gcc.S
+++ b/libcpu/mips/loongson_1b/cache_gcc.S
@@ -1,20 +1,22 @@
 /*
- * File      : cache_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
  * 2010-09-11     bernard      port to Loongson SoC3210
  * 2011-08-08     lgnq         port to Loongson LS1B
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
 #include "../common/mipsregs.h"
-#include "../common/mips.inc"
+#include "../common/mips_def.h"
 #include "../common/asm.h"
 #include "cache.h"
 
diff --git a/libcpu/mips/loongson_1b/context_gcc.S b/libcpu/mips/loongson_1b/context_gcc.S
index ce004dc716..bed2c13252 100644
--- a/libcpu/mips/loongson_1b/context_gcc.S
+++ b/libcpu/mips/loongson_1b/context_gcc.S
@@ -1,20 +1,21 @@
 /*
- * File      : context_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
  * 2010-09-11     bernard      port to Loongson SoC3210
  * 2011-08-08     lgnq         port to Loongson LS1B
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
-#include "../common/mips.inc"
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 
     .section ".text", "ax"
diff --git a/libcpu/mips/loongson_1b/start_gcc.S b/libcpu/mips/loongson_1b/start_gcc.S
index fd98335671..f54fbb9a1d 100644
--- a/libcpu/mips/loongson_1b/start_gcc.S
+++ b/libcpu/mips/loongson_1b/start_gcc.S
@@ -1,19 +1,20 @@
 /*
- * File      : start_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
  * 2010-09-04     bernard      porting to Jz47xx
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
-#include "../common/mips.inc"
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 
 	.section ".start", "ax"
diff --git a/libcpu/mips/loongson_1c/cache_gcc.S b/libcpu/mips/loongson_1c/cache_gcc.S
index af25c31ded..649a88b67b 100644
--- a/libcpu/mips/loongson_1c/cache_gcc.S
+++ b/libcpu/mips/loongson_1c/cache_gcc.S
@@ -1,11 +1,7 @@
 /*
- * File      : cache_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
@@ -13,9 +9,15 @@
  * 2010-09-11     bernard      port to Loongson SoC3210
  * 2011-08-08     lgnq         port to Loongson LS1B
  * 2015-07-08     chinesebear  port to Loongson LS1C
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
 #include "../common/mipsregs.h"
-#include "../common/mips.inc"
+#include "../common/mips_def.h"
 #include "../common/asm.h"
 #include "cache.h"
 
diff --git a/libcpu/mips/loongson_1c/context_gcc.S b/libcpu/mips/loongson_1c/context_gcc.S
index fbffd34866..53bce723e7 100644
--- a/libcpu/mips/loongson_1c/context_gcc.S
+++ b/libcpu/mips/loongson_1c/context_gcc.S
@@ -1,20 +1,21 @@
 /*
- * File      : context_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
  * 2010-09-11     bernard      port to Loongson SoC3210
  * 2011-08-08     lgnq         port to Loongson LS1B
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
-#include "../common/mips.inc"
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 #include "stackframe_fpu.h"
 
diff --git a/libcpu/mips/loongson_1c/start_gcc.S b/libcpu/mips/loongson_1c/start_gcc.S
index 4e71bc0524..1d13ef7f0f 100644
--- a/libcpu/mips/loongson_1c/start_gcc.S
+++ b/libcpu/mips/loongson_1c/start_gcc.S
@@ -1,19 +1,20 @@
 /*
- * File      : start_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2006 - 2011, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rt-thread.org/license/LICENSE
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      porting to Jz47xx
+ * 2010-09-04     bernard      porting to JZ47xx
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
-#include "../common/mips.inc"
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 #include "sdram_cfg.h"
 #include "cache.h"
diff --git a/libcpu/mips/pic32/context_gcc.S b/libcpu/mips/pic32/context_gcc.S
index 3e820fb9d8..bd46dffdc7 100644
--- a/libcpu/mips/pic32/context_gcc.S
+++ b/libcpu/mips/pic32/context_gcc.S
@@ -1,5 +1,20 @@
+/*
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-05-24     aozima       first version
+ * 2019-07-19     Zhou Yanjie  clean up code
+ */
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
 #include <p32xxxx.h>
-#include "../common/mips.inc"
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 
     .section ".text", "ax"
diff --git a/libcpu/mips/x1000/mips_cache_gcc.S b/libcpu/mips/x1000/mips_cache_gcc.S
index 671f193af0..cc69cba1a6 100644
--- a/libcpu/mips/x1000/mips_cache_gcc.S
+++ b/libcpu/mips/x1000/mips_cache_gcc.S
@@ -1,29 +1,15 @@
 /*
- * File      : mips_cache_gcc.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��19��     Urey         the first version
+ * 2016-09-19     Urey         first version
  */
 
 #ifndef __ASSEMBLY__
-#	define	__ASSEMBLY__
+#define	__ASSEMBLY__
 #endif
 
 #include "../common/mips.h"
diff --git a/libcpu/mips/x1000/mips_context_gcc.S b/libcpu/mips/x1000/mips_context_gcc.S
index d4c314ab65..5cb473a72a 100644
--- a/libcpu/mips/x1000/mips_context_gcc.S
+++ b/libcpu/mips/x1000/mips_context_gcc.S
@@ -1,29 +1,15 @@
 /*
- * File      : mips_context_asm.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
+ * 2016-09-07     Urey         first version
  */
 
 #ifndef __ASSEMBLY__
-#	define __ASSEMBLY__
+#define __ASSEMBLY__
 #endif
 
 #include "../common/mips.h"
diff --git a/libcpu/mips/x1000/mips_excpt_gcc.S b/libcpu/mips/x1000/mips_excpt_gcc.S
index c403adf93b..bca6fd1956 100644
--- a/libcpu/mips/x1000/mips_excpt_gcc.S
+++ b/libcpu/mips/x1000/mips_excpt_gcc.S
@@ -1,29 +1,15 @@
 /*
- * File      : mips_excpt_asm.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
+ * 2016-09-07     Urey         first version
  */
 
 #ifndef __ASSEMBLY__
-#	define __ASSEMBLY__
+#define __ASSEMBLY__
 #endif
 
 #include "../common/mips.h"
diff --git a/libcpu/mips/x1000/mips_fp_gcc.S b/libcpu/mips/x1000/mips_fp_gcc.S
index b219084065..303519afe4 100644
--- a/libcpu/mips/x1000/mips_fp_gcc.S
+++ b/libcpu/mips/x1000/mips_fp_gcc.S
@@ -1,29 +1,15 @@
 /*
- * File      : mips_vfp32_asm.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��9��     Urey         the first version
+ * 2016-09-09     Urey         first version
  */
 
 #ifndef __ASSEMBLY__
-#	define __ASSEMBLY__
+#define __ASSEMBLY__
 #endif
 
 #ifdef __mips_hard_float
diff --git a/libcpu/mips/x1000/startup_gcc.S b/libcpu/mips/x1000/startup_gcc.S
index 1376cb7dd4..c5112614fc 100644
--- a/libcpu/mips/x1000/startup_gcc.S
+++ b/libcpu/mips/x1000/startup_gcc.S
@@ -1,29 +1,15 @@
 /*
- * File      : startup.S
- * This file is part of RT-Thread RTOS
- * COPYRIGHT (C) 2008 - 2012, RT-Thread Development Team
+ * Copyright (c) 2006-2019, RT-Thread Development Team
  *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * SPDX-License-Identifier: Apache-2.0
  *
  * Change Logs:
  * Date           Author       Notes
- * 2016��9��7��     Urey         the first version
+ * 2016-09-07     Urey         first version
  */
 
 #ifndef __ASSEMBLY__
-#	define __ASSEMBLY__
+#define __ASSEMBLY__
 #endif
 
 #include "../common/mips.h"
diff --git a/libcpu/mips/xburst/cache_gcc.S b/libcpu/mips/xburst/cache_gcc.S
index 76552698d0..a8d215764c 100644
--- a/libcpu/mips/xburst/cache_gcc.S
+++ b/libcpu/mips/xburst/cache_gcc.S
@@ -1,10 +1,19 @@
 /*
- * File      : cache_init.S
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
-#include "../common/mips.inc"
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/mipsregs.h"
 #include "../common/stackframe.h"
 
diff --git a/libcpu/mips/xburst/context_gcc.S b/libcpu/mips/xburst/context_gcc.S
index d018de3da8..a44d3bdcc7 100644
--- a/libcpu/mips/xburst/context_gcc.S
+++ b/libcpu/mips/xburst/context_gcc.S
@@ -1,11 +1,20 @@
 /*
- * File      : context_gcc.S
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
- * 2010-09-11     bernard      port to Jz4755
+ * 2010-09-11     bernard      port to JZ4755
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
-#include "../common/mips.inc"
+
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 #include "stack.h"
 
diff --git a/libcpu/mips/xburst/start_gcc.S b/libcpu/mips/xburst/start_gcc.S
index 322c2beae8..da8bfa9251 100644
--- a/libcpu/mips/xburst/start_gcc.S
+++ b/libcpu/mips/xburst/start_gcc.S
@@ -1,12 +1,20 @@
 /*
- * File      : start_gcc.S
+ * Copyright (c) 2006-2019, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
  * Change Logs:
  * Date           Author       Notes
  * 2010-05-17     swkyer       first version
- * 2010-09-04     bernard      porting to Jz47xx
+ * 2010-09-04     bernard      porting to JZ47xx
+ * 2019-07-19     Zhou Yanjie  clean up code
  */
 
-#include "../common/mips.inc"
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__
+#endif
+
+#include "../common/mips_def.h"
 #include "../common/stackframe.h"
 #include "stack.h"
 
diff --git a/libcpu/risc-v/bumblebee/SConscript b/libcpu/risc-v/bumblebee/SConscript
new file mode 100644
index 0000000000..b0ae20ba02
--- /dev/null
+++ b/libcpu/risc-v/bumblebee/SConscript
@@ -0,0 +1,14 @@
+# RT-Thread building script for component
+
+from building import *
+
+Import('rtconfig')
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
+CPPPATH = [cwd]
+ASFLAGS = ''
+
+group = DefineGroup('cpu', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
+
+Return('group')
diff --git a/libcpu/risc-v/bumblebee/interrupt_gcc.S b/libcpu/risc-v/bumblebee/interrupt_gcc.S
new file mode 100644
index 0000000000..5a86e7d748
--- /dev/null
+++ b/libcpu/risc-v/bumblebee/interrupt_gcc.S
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2006-2018, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ */
+ 
+#include "cpuport.h"
+
+ .section      .text.entry
+  .align 6     /* In ECLIC mode, the trap entry must be 64bytes aligned */
+  .global irq_entry
+irq_entry:
+
+    /* save all from thread context */
+    addi sp, sp, -32 * REGBYTES
+
+    STORE x1,   1 * REGBYTES(sp)
+    li    t0,   0x80
+    STORE t0,   2 * REGBYTES(sp)
+
+    STORE x4,   4 * REGBYTES(sp)
+    STORE x5,   5 * REGBYTES(sp)
+    STORE x6,   6 * REGBYTES(sp)
+    STORE x7,   7 * REGBYTES(sp)
+    STORE x8,   8 * REGBYTES(sp)
+    STORE x9,   9 * REGBYTES(sp)
+    STORE x10, 10 * REGBYTES(sp)
+    STORE x11, 11 * REGBYTES(sp)
+    STORE x12, 12 * REGBYTES(sp)
+    STORE x13, 13 * REGBYTES(sp)
+    STORE x14, 14 * REGBYTES(sp)
+    STORE x15, 15 * REGBYTES(sp)
+    STORE x16, 16 * REGBYTES(sp)
+    STORE x17, 17 * REGBYTES(sp)
+    STORE x18, 18 * REGBYTES(sp)
+    STORE x19, 19 * REGBYTES(sp)
+    STORE x20, 20 * REGBYTES(sp)
+    STORE x21, 21 * REGBYTES(sp)
+    STORE x22, 22 * REGBYTES(sp)
+    STORE x23, 23 * REGBYTES(sp)
+    STORE x24, 24 * REGBYTES(sp)
+    STORE x25, 25 * REGBYTES(sp)
+    STORE x26, 26 * REGBYTES(sp)
+    STORE x27, 27 * REGBYTES(sp)
+    STORE x28, 28 * REGBYTES(sp)
+    STORE x29, 29 * REGBYTES(sp)
+    STORE x30, 30 * REGBYTES(sp)
+    STORE x31, 31 * REGBYTES(sp)
+
+    move  s0, sp
+
+    /* switch to interrupt stack */
+    la    sp, _sp
+
+    /* interrupt handle */
+    call  rt_interrupt_enter
+    csrr  a0, mcause
+    csrr  a1, mepc
+    mv    a2, sp
+    csrrw ra, 0x07ED, ra
+    call  rt_interrupt_leave
+
+    /* switch to from thread stack */
+    move  sp, s0
+
+    /* need to switch new thread */
+    la    s0, rt_thread_switch_interrupt_flag
+    lw    s2, 0(s0)
+    beqz  s2, spurious_interrupt
+    /* clear switch interrupt flag */
+    sw    zero, 0(s0)
+
+    csrr  a0, mepc
+    STORE a0, 0 * REGBYTES(sp)
+
+    la    s0, rt_interrupt_from_thread
+    LOAD  s1, 0(s0)
+    STORE sp, 0(s1)
+
+    la    s0, rt_interrupt_to_thread
+    LOAD  s1, 0(s0)
+    LOAD  sp, 0(s1)
+
+    LOAD  a0,  0 * REGBYTES(sp)
+    csrw  mepc, a0
+
+spurious_interrupt:
+    LOAD  x1,   1 * REGBYTES(sp)
+
+    /* Remain in M-mode after mret */
+    li    t0, 0x00001800
+    csrs  mstatus, t0
+    LOAD  t0,   2 * REGBYTES(sp)
+    csrs  mstatus, t0
+
+    LOAD  x4,   4 * REGBYTES(sp)
+    LOAD  x5,   5 * REGBYTES(sp)
+    LOAD  x6,   6 * REGBYTES(sp)
+    LOAD  x7,   7 * REGBYTES(sp)
+    LOAD  x8,   8 * REGBYTES(sp)
+    LOAD  x9,   9 * REGBYTES(sp)
+    LOAD  x10, 10 * REGBYTES(sp)
+    LOAD  x11, 11 * REGBYTES(sp)
+    LOAD  x12, 12 * REGBYTES(sp)
+    LOAD  x13, 13 * REGBYTES(sp)
+    LOAD  x14, 14 * REGBYTES(sp)
+    LOAD  x15, 15 * REGBYTES(sp)
+    LOAD  x16, 16 * REGBYTES(sp)
+    LOAD  x17, 17 * REGBYTES(sp)
+    LOAD  x18, 18 * REGBYTES(sp)
+    LOAD  x19, 19 * REGBYTES(sp)
+    LOAD  x20, 20 * REGBYTES(sp)
+    LOAD  x21, 21 * REGBYTES(sp)
+    LOAD  x22, 22 * REGBYTES(sp)
+    LOAD  x23, 23 * REGBYTES(sp)
+    LOAD  x24, 24 * REGBYTES(sp)
+    LOAD  x25, 25 * REGBYTES(sp)
+    LOAD  x26, 26 * REGBYTES(sp)
+    LOAD  x27, 27 * REGBYTES(sp)
+    LOAD  x28, 28 * REGBYTES(sp)
+    LOAD  x29, 29 * REGBYTES(sp)
+    LOAD  x30, 30 * REGBYTES(sp)
+    LOAD  x31, 31 * REGBYTES(sp)
+
+    addi  sp, sp, 32 * REGBYTES
+    mret
diff --git a/libcpu/ti-dsp/c28x/context.s b/libcpu/ti-dsp/c28x/context.s
index 2b853a0075..f21e0ddb6e 100644
--- a/libcpu/ti-dsp/c28x/context.s
+++ b/libcpu/ti-dsp/c28x/context.s
@@ -6,6 +6,8 @@
 ; Change Logs:
 ; Date           Author       Notes
 ; 2018-09-01     xuzhuoyi     the first version.
+; 2019-06-17     zhaoxiaowei  fix bugs of old c28x interrupt api.
+; 2019-07-03     zhaoxiaowei  add _rt_hw_calc_csb function to support __rt_ffs.
 ;
 
     .ref   _rt_interrupt_to_thread
@@ -15,6 +17,7 @@
     .def   _RTOSINT_Handler
     .def   _rt_hw_get_st0
     .def   _rt_hw_get_st1
+    .def   _rt_hw_calc_csb
     .def   _rt_hw_context_switch_interrupt
     .def   _rt_hw_context_switch
     .def   _rt_hw_context_switch_to
@@ -73,7 +76,9 @@ RT_CTX_RESTORE  .macro
 ;
     .asmfunc
 _rt_hw_interrupt_disable:
-    DINT
+    PUSH  ST1
+    SETC  INTM,DBGM
+    MOV   AL, *--SP
     LRETR
     .endasmfunc
 
@@ -82,7 +87,8 @@ _rt_hw_interrupt_disable:
 ;
     .asmfunc
 _rt_hw_interrupt_enable:
-    EINT
+    MOV   *SP++, AL
+    POP   ST1
     LRETR
     .endasmfunc
     
@@ -226,6 +232,25 @@ _rt_hw_get_st1:
     LRETR
     .endasmfunc
 
+; C28x do not have a build-in "__ffs" func in its C compiler.
+; We can use the "Count Sign Bits" (CSB) instruction to make one.
+; CSB will return the number of 0's minus 1 above the highest set bit.
+; The count is placed in T. For example:
+;    ACC        T     maxbit
+; 0x00000001    30      0
+; 0x00000010    26      4
+; 0x000001FF    22      8
+; 0x000001F0    22      8
+    .asmfunc
+_rt_hw_calc_csb:
+    MOV     AH, #0
+    CSB     ACC                   ; T = no. of sign bits - 1
+    MOVU    ACC, T                ; ACC = no. of sign bits - 1
+    SUBB    ACC, #30              ; ACC = ACC - 30
+    ABS     ACC                   ; ACC = |ACC|
+    lretr
+    .endasmfunc
+
 ;
 ; * void rt_hw_context_switch_to(rt_uint32 to);
 ; * r0 --> to
diff --git a/libcpu/ti-dsp/c28x/cpuport.c b/libcpu/ti-dsp/c28x/cpuport.c
index 2d42884bed..e34556c524 100644
--- a/libcpu/ti-dsp/c28x/cpuport.c
+++ b/libcpu/ti-dsp/c28x/cpuport.c
@@ -6,6 +6,7 @@
  * Change Logs:
  * Date           Author       Notes
  * 2018-09-01     xuzhuoyi     the first version.
+ * 2019-07-03     zhaoxiaowei  add support for __rt_ffs.
  */
 
 #include <rtthread.h>
@@ -19,6 +20,7 @@ static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
 
 extern rt_uint16_t rt_hw_get_st0(void);
 extern rt_uint16_t rt_hw_get_st1(void);
+extern int rt_hw_calc_csb(int value);
 
 struct exception_stack_frame
 {
@@ -102,6 +104,19 @@ struct exception_info
     struct stack_frame stack_frame;
 };
 
+#ifdef RT_USING_CPU_FFS
+/*
+ * This function called rt_hw_calc_csb to finds the first bit set in value.
+ * rt_hw_calc_csb is a native assembly program that use "CSB" instruction in C28x.
+ * When you use this function, remember that "int" is only 16-bit in C28x's C compiler.
+ * If value is a number bigger that 0xFFFF, trouble may be caused.
+ * Maybe change "int __rt_ffs(int value)" to "rt_int32_t __rt_ffs(rt_int32_t value)" will be better.
+ */
+int __rt_ffs(int value)
+{
+    return rt_hw_calc_csb(value);
+}
+#endif
 
 /**
  * shutdown CPU