diff options
| author | zhangjun <[email protected]> | 2017-07-31 10:59:59 +0800 |
|---|---|---|
| committer | zhangjun <[email protected]> | 2017-07-31 10:59:59 +0800 |
| commit | a5305c05df3e97cd60c621bec87926765ba31228 (patch) | |
| tree | 253bbec417bf23c06b5aa8e85788998dd2ec5f48 /libcpu | |
| parent | d9c0bdc70e6c4f2b1a091fe442e4bcc58a7fe361 (diff) | |
fix bug in context_gcc.s and start_gcc.s:
save mie into stack
msh running normaly
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/risc-v/e310/context_gcc.S | 6 | ||||
| -rw-r--r-- | libcpu/risc-v/e310/stack.c | 3 | ||||
| -rw-r--r-- | libcpu/risc-v/e310/start_gcc.S | 20 |
3 files changed, 21 insertions, 8 deletions
diff --git a/libcpu/risc-v/e310/context_gcc.S b/libcpu/risc-v/e310/context_gcc.S index eee3cc128d..c727396736 100644 --- a/libcpu/risc-v/e310/context_gcc.S +++ b/libcpu/risc-v/e310/context_gcc.S @@ -106,9 +106,11 @@ rt_hw_context_switch: STORE x26, 26*REGBYTES(sp) STORE x27, 27*REGBYTES(sp) STORE x28, 28*REGBYTES(sp) - STORE x1, 31*REGBYTES(sp) STORE x10, 29*REGBYTES(sp) STORE x1, 30*REGBYTES(sp) + STORE x1, 31*REGBYTES(sp) + csrr x10, mie + STORE x10, 0*REGBYTES(sp) /* *Remain in M-mode after mret *enable interrupt in M-mode @@ -147,6 +149,8 @@ rt_hw_context_switch: LOAD x28, 28*REGBYTES(sp) LOAD x10, 31*REGBYTES(sp) csrw mepc,x10 + LOAD x10, 0*REGBYTES(sp) + csrw mie, x10 LOAD x10, 29*REGBYTES(sp) LOAD x1, 30*REGBYTES(sp) diff --git a/libcpu/risc-v/e310/stack.c b/libcpu/risc-v/e310/stack.c index 666a2d5bbd..eab608c753 100644 --- a/libcpu/risc-v/e310/stack.c +++ b/libcpu/risc-v/e310/stack.c @@ -86,7 +86,8 @@ rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, *(--stk) = 0xffffffff; /* t6 */ *(--stk) = 0xffffffff; /* tp */ *(--stk) = 0xffffffff; /* gp */ + *(--stk) = 0x880; /* mie */ // *(--stk) = (rt_uint32_t)parameter; /* r0 : argument */ /* return task's current stack address */ - return (rt_uint8_t *)--stk; + return (rt_uint8_t *)stk; } diff --git a/libcpu/risc-v/e310/start_gcc.S b/libcpu/risc-v/e310/start_gcc.S index e7aaddcae9..8ed2a03d37 100644 --- a/libcpu/risc-v/e310/start_gcc.S +++ b/libcpu/risc-v/e310/start_gcc.S @@ -176,8 +176,17 @@ trap_entry: STORE x1, 30*REGBYTES(sp) csrr x10, mepc STORE x10, 31*REGBYTES(sp) + csrr x10, mie + STORE x10, 0*REGBYTES(sp) +/* + *Remain in M-mode after mret + *enable interrupt in M-mode + */ + li t0, MSTATUS_MPP + csrrs t0, mstatus, t0 + call rt_interrupt_enter csrr a0, mcause lui a5, 0x80000 @@ -189,17 +198,13 @@ trap_entry: bne a5, a4, 1f call rt_hw_trap_irq 1: - /*Machine software interrupt*/ + /*Machine timer interrupt*/ li a4, 7 bne a5, a4, 2f call rt_systick_handler 2: call rt_interrupt_leave - # Remain in M-mode after mret - li t0, 136 - csrrs t0, mstatus, t0 - la a0, rt_thread_switch_interrupt_flag lw a1, (a0) bnez a1, rt_hw_context_switch_interrupt_do @@ -235,9 +240,10 @@ trap_entry: LOAD x28, 28*REGBYTES(sp) LOAD x10, 31*REGBYTES(sp) csrw mepc,x10 + LOAD x10, 0*REGBYTES(sp) + csrw mie, x10 LOAD x10, 29*REGBYTES(sp) LOAD x1, 30*REGBYTES(sp) - addi sp, sp, 32*REGBYTES mret @@ -282,6 +288,8 @@ rt_hw_context_switch_interrupt_do: LOAD x28, 28*REGBYTES(sp) LOAD x10, 31*REGBYTES(sp) csrw mepc,x10 + LOAD x10, 0*REGBYTES(sp) + csrw mie, x10 LOAD x10, 29*REGBYTES(sp) LOAD x1, 30*REGBYTES(sp) |
