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authorCYFS <[email protected]>2025-03-18 22:55:13 +0800
committerGitHub <[email protected]>2025-03-18 22:55:13 +0800
commitb0e7cba9fddd45a4a51e228fc2f8721714bd7be9 (patch)
treec9ccc7174dfcd36a1f444ed38966ded6d0ec7556 /libcpu
parentbf60f3152628d3437e4e589742bf7ef37b71d8c9 (diff)
[bsp][stm32][artpi]:fix artpi nano (#10122)
Diffstat (limited to 'libcpu')
-rw-r--r--libcpu/arm/cortex-m7/cpu_cache.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/libcpu/arm/cortex-m7/cpu_cache.c b/libcpu/arm/cortex-m7/cpu_cache.c
index 6ec4c826d5..058abe49c2 100644
--- a/libcpu/arm/cortex-m7/cpu_cache.c
+++ b/libcpu/arm/cortex-m7/cpu_cache.c
@@ -76,15 +76,15 @@ void rt_hw_cpu_dcache_ops(int ops, void* addr, int size)
if ((ops & clean_invalid) == clean_invalid)
{
- SCB_CleanInvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte);
+ SCB_CleanInvalidateDCache_by_Addr((void *)startAddr, size_byte);
}
else if (ops & RT_HW_CACHE_FLUSH)
{
- SCB_CleanDCache_by_Addr((rt_uint32_t *)startAddr, size_byte);
+ SCB_CleanDCache_by_Addr((void *)startAddr, size_byte);
}
else if (ops & RT_HW_CACHE_INVALIDATE)
{
- SCB_InvalidateDCache_by_Addr((rt_uint32_t *)startAddr, size_byte);
+ SCB_InvalidateDCache_by_Addr((void *)startAddr, size_byte);
}
else
{