diff options
| author | zhangjun <[email protected]> | 2017-07-26 16:27:54 +0800 |
|---|---|---|
| committer | zhangjun <[email protected]> | 2017-07-26 16:27:54 +0800 |
| commit | b80f83f360261156af3d502db659e9c53a6222a0 (patch) | |
| tree | d776ac75eb8c94840a274850964e3f5eda8b4267 /libcpu | |
| parent | 98a6896cfa5b577503139363ffc141418d55412f (diff) | |
modified: ../../libcpu/risc-v/e310/context_gcc.S
fix open timer intrrupt
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/risc-v/e310/context_gcc.S | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/libcpu/risc-v/e310/context_gcc.S b/libcpu/risc-v/e310/context_gcc.S index 390e3033c0..57a929eb09 100644 --- a/libcpu/risc-v/e310/context_gcc.S +++ b/libcpu/risc-v/e310/context_gcc.S @@ -32,7 +32,8 @@ rt_hw_interrupt_disable: addi sp, sp, -12 sw a5, (sp) - csrrc a5, mie, MIP_MEIP|MIP_MTIP|MIP_MSIP + li a5, MIP_MEIP|MIP_MTIP|MIP_MSIP + csrrc a5, mie, a5 /* csrrc a5, mstatus, MSTATUS_MIE*/ lw a5, (sp) addi sp, sp, 12 @@ -45,7 +46,8 @@ rt_hw_interrupt_disable: rt_hw_interrupt_enable: addi sp, sp, -12 sw a5, (sp) - csrrs a5, mie, MIP_MEIP|MIP_MTIP|MIP_MSIP + li a5, MIP_MEIP|MIP_MTIP|MIP_MSIP + csrrs a5, mie, a5 /* csrrsi a5, mstatus, MSTATUS_MIE*/ lw a5, (sp) addi sp, sp, 12 |