diff options
| author | Fan Yang <[email protected]> | 2024-04-30 20:11:47 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2024-04-30 20:11:47 +0800 |
| commit | c21ba6985d5a9d6f6926799ada4faa92c20cb8a0 (patch) | |
| tree | 56925ef9e80afb228561cb273204c4efab48c0f5 /libcpu | |
| parent | 0ccc315bced299555e478a7ee6b886341a1c227e (diff) | |
Fix compiling eror in hpmicro bsp (#8889)
- added 'DEVICE' to rtconfig.py
- fixed compiling error cuased by change in interrupt_gcc.S
Signed-off-by: Fan YANG <[email protected]>
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/risc-v/common/interrupt_gcc.S | 1 | ||||
| -rw-r--r-- | libcpu/risc-v/common/trap_common.c | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/libcpu/risc-v/common/interrupt_gcc.S b/libcpu/risc-v/common/interrupt_gcc.S index 6204e4be44..fc916dd821 100644 --- a/libcpu/risc-v/common/interrupt_gcc.S +++ b/libcpu/risc-v/common/interrupt_gcc.S @@ -214,6 +214,7 @@ SW_handler: .section .text.trap_entry .align 2 + .weak trap_entry .global trap_entry trap_entry: #ifdef ARCH_RISCV_FPU diff --git a/libcpu/risc-v/common/trap_common.c b/libcpu/risc-v/common/trap_common.c index 6f7352cd56..3cbbfeb008 100644 --- a/libcpu/risc-v/common/trap_common.c +++ b/libcpu/risc-v/common/trap_common.c @@ -109,3 +109,10 @@ rt_weak void rt_show_stack_frame(void) rt_kprintf("t6 : 0x%08x\r\n", s_stack_frame->t6); #endif } + +/** + * Trap Handler + */ +rt_weak void handle_trap(rt_uint32_t mcause, rt_uint32_t mepc, rt_uint32_t sp) +{ +}
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