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authorxieyangrun <[email protected]>2017-09-04 10:12:34 +0800
committerxieyangrun <[email protected]>2017-09-04 10:12:34 +0800
commitd1d81c158f22d74dd900bc045c92be5079f74cd0 (patch)
treeec56ebee659e4ffe53ef22f2567104faeb45a153 /libcpu
parent80a21100b367f5175fdf27c395051c53b23976e8 (diff)
parentbc225a5ef05a9b14dd72286402093cbb7dba8305 (diff)
Merge branch 'master' of https://github.com/RT-Thread/rt-thread into samd21
Diffstat (limited to 'libcpu')
-rw-r--r--libcpu/arm/cortex-m0/context_gcc.S1
-rw-r--r--libcpu/arm/cortex-m0/context_iar.S1
2 files changed, 0 insertions, 2 deletions
diff --git a/libcpu/arm/cortex-m0/context_gcc.S b/libcpu/arm/cortex-m0/context_gcc.S
index c95582630a..227a9aac2d 100644
--- a/libcpu/arm/cortex-m0/context_gcc.S
+++ b/libcpu/arm/cortex-m0/context_gcc.S
@@ -182,7 +182,6 @@ rt_hw_context_switch_to:
MSR MSP, R0
/* enable interrupts at processor level */
- CPSIE F
CPSIE I
/* never reach here! */
diff --git a/libcpu/arm/cortex-m0/context_iar.S b/libcpu/arm/cortex-m0/context_iar.S
index e7d680867a..67ea808d8c 100644
--- a/libcpu/arm/cortex-m0/context_iar.S
+++ b/libcpu/arm/cortex-m0/context_iar.S
@@ -188,7 +188,6 @@ rt_hw_context_switch_to:
MSR msp, r0
; enable interrupts at processor level
- CPSIE F
CPSIE I
; never reach here!