diff options
| author | Bernard Xiong <[email protected]> | 2020-05-26 10:40:44 +0800 |
|---|---|---|
| committer | GitHub <[email protected]> | 2020-05-26 10:40:44 +0800 |
| commit | fbd8303375516b275f8f5edc846d108e1792e4d6 (patch) | |
| tree | cd83d79ac9e41d00d1a8d3f333564f1362f26579 /libcpu | |
| parent | 8e3e0edcc5ba3d441788270ac2e61558ede14028 (diff) | |
| parent | c4faf6dfdf4b4e4ca9218a2ab65132d789854069 (diff) | |
Merge pull request #3626 from bigmagic123/add-raspi4-32bit
Add raspi4 32bit
Diffstat (limited to 'libcpu')
| -rw-r--r-- | libcpu/Kconfig | 3 | ||||
| -rw-r--r-- | libcpu/aarch64/common/gic/gic_pl400.c | 1 | ||||
| -rw-r--r-- | libcpu/aarch64/cortex-a72/interrupt.c | 1 | ||||
| -rw-r--r-- | libcpu/arm/cortex-a/start_gcc.S | 20 |
4 files changed, 23 insertions, 2 deletions
diff --git a/libcpu/Kconfig b/libcpu/Kconfig index 95d3dd5228..e355664de2 100644 --- a/libcpu/Kconfig +++ b/libcpu/Kconfig @@ -74,6 +74,9 @@ config ARCH_ARM_CORTEX_A9 bool select ARCH_ARM_CORTEX_A +config ARCH_ARMV8 + bool + config ARCH_MIPS bool diff --git a/libcpu/aarch64/common/gic/gic_pl400.c b/libcpu/aarch64/common/gic/gic_pl400.c index 4d003a9dcd..1f4d868636 100644 --- a/libcpu/aarch64/common/gic/gic_pl400.c +++ b/libcpu/aarch64/common/gic/gic_pl400.c @@ -14,7 +14,6 @@ #include "gic_pl400.h" #include "cp15.h" -#include "iomap.h" #define ARM_GIC_MAX_NR 1 struct arm_gic diff --git a/libcpu/aarch64/cortex-a72/interrupt.c b/libcpu/aarch64/cortex-a72/interrupt.c index 6fec968dc2..3b689dceb3 100644 --- a/libcpu/aarch64/cortex-a72/interrupt.c +++ b/libcpu/aarch64/cortex-a72/interrupt.c @@ -13,7 +13,6 @@ #include <gic_pl400.h> #include <board.h> #include <armv8.h> -#include "iomap.h" #define MAX_HANDLERS 256 #define GIC_ACK_INTID_MASK 0x000003ff diff --git a/libcpu/arm/cortex-a/start_gcc.S b/libcpu/arm/cortex-a/start_gcc.S index 268cc7ef56..a8f3a36630 100644 --- a/libcpu/arm/cortex-a/start_gcc.S +++ b/libcpu/arm/cortex-a/start_gcc.S @@ -52,6 +52,26 @@ stack_top: /* reset entry */ .globl _reset _reset: +#ifdef ARCH_ARMV8 + /* Check for HYP mode */ + mrs r0, cpsr_all + and r0, r0, #0x1F + mov r8, #0x1A + cmp r0, r8 + beq overHyped + b continue + +overHyped: /* Get out of HYP mode */ + ldr r1, =continue + msr ELR_hyp, r1 + mrs r1, cpsr_all + and r1, r1, #0x1f ;@ CPSR_MODE_MASK + orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR + msr SPSR_hyp, r1 + eret + +continue: +#endif /* set the cpu to SVC32 mode and disable interrupt */ cps #Mode_SVC |