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-rw-r--r--bsp/stm32/libraries/HAL_Drivers/SConscript3
-rw-r--r--bsp/stm32/libraries/HAL_Drivers/drv_soft_spi.c230
-rw-r--r--bsp/stm32/libraries/HAL_Drivers/drv_soft_spi.h56
-rw-r--r--bsp/stm32/stm32f407-atk-explorer/board/Kconfig52
-rw-r--r--bsp/stm32/stm32f407-atk-explorer/board/SConscript3
-rw-r--r--bsp/stm32/stm32f407-atk-explorer/board/ports/soft_spi_flash_init.c32
-rw-r--r--components/drivers/spi/spi-bit-ops.h3
7 files changed, 378 insertions, 1 deletions
diff --git a/bsp/stm32/libraries/HAL_Drivers/SConscript b/bsp/stm32/libraries/HAL_Drivers/SConscript
index 1422c9d559..de3b27a872 100644
--- a/bsp/stm32/libraries/HAL_Drivers/SConscript
+++ b/bsp/stm32/libraries/HAL_Drivers/SConscript
@@ -28,6 +28,9 @@ if GetDepend(['RT_USING_SPI']):
if GetDepend(['RT_USING_QSPI']):
src += ['drv_qspi.c']
+if GetDepend('RT_USING_SPI_BITOPS'):
+ src += ['drv_soft_spi.c']
+
if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
if GetDepend('BSP_USING_I2C1') or GetDepend('BSP_USING_I2C2') or GetDepend('BSP_USING_I2C3') or GetDepend('BSP_USING_I2C4'):
src += ['drv_soft_i2c.c']
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_soft_spi.c b/bsp/stm32/libraries/HAL_Drivers/drv_soft_spi.c
new file mode 100644
index 0000000000..c829e0ff95
--- /dev/null
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_soft_spi.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2022-6-14 solar first version
+ */
+#include <board.h>
+#include "drv_soft_spi.h"
+#include "drv_config.h"
+
+#if defined(RT_USING_SPI) && defined(RT_USING_SPI_BITOPS) && defined(RT_USING_PIN)
+
+//#define DRV_DEBUG
+#define LOG_TAG "drv.soft_spi"
+#include <drv_log.h>
+
+static struct stm32_soft_spi_config soft_spi_config[] =
+{
+#ifdef BSP_USING_SOFT_SPI1
+ SOFT_SPI1_BUS_CONFIG,
+#endif
+#ifdef BSP_USING_SOFT_SPI2
+ SOFT_SPI2_BUS_CONFIG,
+#endif
+};
+
+/**
+ * Attach the spi device to soft SPI bus, this function must be used after initialization.
+ */
+rt_err_t rt_hw_soft_spi_device_attach(const char *bus_name, const char *device_name, const char *pin_name)
+{
+
+ rt_err_t result;
+ struct rt_spi_device *spi_device;
+
+ /* initialize the cs pin && select the slave*/
+ rt_base_t cs_pin = rt_pin_get(pin_name);
+
+ rt_pin_mode(cs_pin,PIN_MODE_OUTPUT);
+ rt_pin_write(cs_pin,PIN_HIGH);
+
+ /* attach the device to soft spi bus*/
+ spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
+ RT_ASSERT(spi_device != RT_NULL);
+
+ result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
+ return result;
+}
+
+static void stm32_spi_gpio_init(struct stm32_soft_spi *spi)
+{
+ struct stm32_soft_spi_config *cfg = (struct stm32_soft_spi_config *)spi->cfg;
+ rt_pin_mode(cfg->sck, PIN_MODE_OUTPUT);
+ rt_pin_mode(cfg->miso, PIN_MODE_INPUT);
+ rt_pin_mode(cfg->mosi, PIN_MODE_OUTPUT);
+
+ rt_pin_write(cfg->miso, PIN_HIGH);
+ rt_pin_write(cfg->sck, PIN_HIGH);
+ rt_pin_write(cfg->mosi, PIN_HIGH);
+}
+
+void stm32_tog_sclk(void *data)
+{
+ struct stm32_soft_spi_config* cfg = (struct stm32_soft_spi_config*)data;
+ if(rt_pin_read(cfg->sck) == PIN_HIGH)
+ {
+ rt_pin_write(cfg->sck, PIN_LOW);
+ }
+ else
+ {
+ rt_pin_write(cfg->sck, PIN_HIGH);
+ }
+}
+
+void stm32_set_sclk(void *data, rt_int32_t state)
+{
+
+ struct stm32_soft_spi_config* cfg = (struct stm32_soft_spi_config*)data;
+ if (state)
+ {
+ rt_pin_write(cfg->sck, PIN_HIGH);
+ }
+ else
+ {
+ rt_pin_write(cfg->sck, PIN_LOW);
+ }
+}
+
+void stm32_set_mosi(void *data, rt_int32_t state)
+{
+ struct stm32_soft_spi_config* cfg = (struct stm32_soft_spi_config*)data;
+ if (state)
+ {
+ rt_pin_write(cfg->mosi, PIN_HIGH);
+ }
+ else
+ {
+ rt_pin_write(cfg->mosi, PIN_LOW);
+ }
+}
+
+void stm32_set_miso(void *data, rt_int32_t state)
+{
+ struct stm32_soft_spi_config* cfg = (struct stm32_soft_spi_config*)data;
+ if (state)
+ {
+ rt_pin_write(cfg->miso, PIN_HIGH);
+ }
+ else
+ {
+ rt_pin_write(cfg->miso, PIN_LOW);
+ }
+}
+
+rt_int32_t stm32_get_sclk(void *data)
+{
+ struct stm32_soft_spi_config* cfg = (struct stm32_soft_spi_config*)data;
+ return rt_pin_read(cfg->sck);
+}
+
+rt_int32_t stm32_get_mosi(void *data)
+{
+ struct stm32_soft_spi_config* cfg = (struct stm32_soft_spi_config*)data;
+ return rt_pin_read(cfg->mosi);
+}
+
+rt_int32_t stm32_get_miso(void *data)
+{
+ struct stm32_soft_spi_config* cfg = (struct stm32_soft_spi_config*)data;
+ return rt_pin_read(cfg->miso);
+}
+
+void stm32_dir_mosi(void *data, rt_int32_t state)
+{
+ struct stm32_soft_spi_config* cfg = (struct stm32_soft_spi_config*)data;
+ if (state)
+ {
+ rt_pin_mode(cfg->mosi, PIN_MODE_INPUT);
+ }
+ else
+ {
+ rt_pin_mode(cfg->mosi, PIN_MODE_OUTPUT);
+ }
+}
+
+void stm32_dir_miso(void *data, rt_int32_t state)
+{
+ struct stm32_soft_spi_config* cfg = (struct stm32_soft_spi_config*)data;
+ if (state)
+ {
+ rt_pin_mode(cfg->miso, PIN_MODE_INPUT);
+ }
+ else
+ {
+ rt_pin_mode(cfg->miso, PIN_MODE_OUTPUT);
+ }
+}
+
+static void stm32_udelay(rt_uint32_t us)
+{
+ rt_uint32_t ticks;
+ rt_uint32_t told, tnow, tcnt = 0;
+ rt_uint32_t reload = SysTick->LOAD;
+
+ ticks = us * reload / (1000000UL / RT_TICK_PER_SECOND);
+ told = SysTick->VAL;
+ while (1)
+ {
+ tnow = SysTick->VAL;
+ if (tnow != told)
+ {
+ if (tnow < told)
+ {
+ tcnt += told - tnow;
+ }
+ else
+ {
+ tcnt += reload - tnow + told;
+ }
+ told = tnow;
+ if (tcnt >= ticks)
+ {
+ break;
+ }
+ }
+ }
+}
+
+static struct rt_spi_bit_ops stm32_soft_spi_ops =
+ {
+ .data = RT_NULL,
+ .tog_sclk = stm32_tog_sclk,
+ .set_sclk = stm32_set_sclk,
+ .set_mosi = stm32_set_mosi,
+ .set_miso = stm32_set_miso,
+ .get_sclk = stm32_get_sclk,
+ .get_mosi = stm32_get_mosi,
+ .get_miso = stm32_get_miso,
+ .dir_mosi = stm32_dir_mosi,
+ .dir_miso = stm32_dir_miso,
+ .udelay = stm32_udelay,
+ .delay_us = 1,
+};
+
+static struct stm32_soft_spi spi_obj[sizeof(soft_spi_config) / sizeof(soft_spi_config[0])];
+
+/* Soft SPI initialization function */
+int rt_soft_spi_init(void)
+{
+ rt_size_t obj_num = sizeof(spi_obj) / sizeof(struct stm32_soft_spi);
+ rt_err_t result;
+
+ for (int i = 0; i < obj_num; i++)
+ {
+ stm32_soft_spi_ops.data = (void *)&soft_spi_config[i];
+ spi_obj[i].spi.ops = &stm32_soft_spi_ops;
+ spi_obj[i].cfg = (void *)&soft_spi_config[i];
+ stm32_spi_gpio_init(&spi_obj[i]);
+ result = rt_spi_bit_add_bus(&spi_obj[i].spi, soft_spi_config[i].bus_name, &stm32_soft_spi_ops);
+ RT_ASSERT(result == RT_EOK);
+ }
+
+ return RT_EOK;
+}
+INIT_BOARD_EXPORT(rt_soft_spi_init);
+
+#endif /* defined(RT_USING_SPI) && defined(RT_USING_SPI_BITOPS) && defined(RT_USING_PIN) */
diff --git a/bsp/stm32/libraries/HAL_Drivers/drv_soft_spi.h b/bsp/stm32/libraries/HAL_Drivers/drv_soft_spi.h
new file mode 100644
index 0000000000..9dbd659833
--- /dev/null
+++ b/bsp/stm32/libraries/HAL_Drivers/drv_soft_spi.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2022-6-14 solar first version
+ */
+
+#ifndef __DRV_SOFT_SPI__
+#define __DRV_SOFT_SPI__
+
+#include <rthw.h>
+#include <rtdevice.h>
+#include <spi-bit-ops.h>
+
+/* stm32 soft spi config */
+struct stm32_soft_spi_config
+{
+ rt_uint8_t sck;
+ rt_uint8_t mosi;
+ rt_uint8_t miso;
+ const char *bus_name;
+};
+
+/* stm32 soft spi dirver */
+struct stm32_soft_spi
+{
+ struct rt_spi_bit_obj spi;
+ struct stm32_soft_spi_config *cfg;
+};
+
+#ifdef BSP_USING_SOFT_SPI1
+#define SOFT_SPI1_BUS_CONFIG \
+ { \
+ .sck = BSP_S_SPI1_SCK_PIN, \
+ .mosi = BSP_S_SPI1_MOSI_PIN, \
+ .miso = BSP_S_SPI1_MISO_PIN, \
+ .bus_name = "sspi1", \
+ }
+#endif /* BSP_USING_SOFT_SPI1 */
+#ifdef BSP_USING_SOFT_SPI2
+#define SOFT_SPI2_BUS_CONFIG \
+ { \
+ .sck = BSP_S_SPI2_SCK_PIN, \
+ .mosi = BSP_S_SPI2_MOSI_PIN, \
+ .miso = BSP_S_SPI2_MISO_PIN, \
+ .bus_name = "sspi2", \
+ }
+#endif /* BSP_USING_SOFT_SPI2 */
+
+rt_err_t rt_hw_soft_spi_device_attach(const char *bus_name, const char *device_name, const char *pin_name);
+int rt_soft_spi_init(void);
+
+#endif /* __DRV_SOFT_SPI__ */
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig
index dd81f6af4c..626f87648a 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/Kconfig
+++ b/bsp/stm32/stm32f407-atk-explorer/board/Kconfig
@@ -79,6 +79,14 @@ menu "Onboard Peripheral Drivers"
select RT_SFUD_USING_SFDP
default n
+ config BSP_USING_SOFT_SPI_FLASH
+ bool "Enable soft SPI FLASH (W25Q128 sspi2)"
+ select BSP_USING_SOFT_SPI
+ select BSP_USING_SOFT_SPI2
+ select RT_USING_SFUD
+ select RT_SFUD_USING_SFDP
+ default n
+
config BSP_USING_EEPROM
bool "Enable I2C EEPROM (i2c1)"
select BSP_USING_I2C1
@@ -274,6 +282,50 @@ menu "On-chip Peripheral Drivers"
bool "Enable on-chip FLASH"
default n
+ menuconfig BSP_USING_SOFT_SPI
+ bool "Enable soft SPI BUS"
+ default n
+ select RT_USING_SPI
+ select RT_USING_SPI_BITOPS
+ select RT_USING_PIN
+ if BSP_USING_SOFT_SPI
+ menuconfig BSP_USING_SOFT_SPI1
+ bool "Enable soft SPI1 BUS (software simulation)"
+ default n
+ if BSP_USING_SOFT_SPI1
+ config BSP_S_SPI1_SCK_PIN
+ int "soft spi1 sck pin number"
+ range 1 176
+ default 16
+ config BSP_S_SPI1_MISO_PIN
+ int "soft spi1 miso pin number"
+ range 1 176
+ default 18
+ config BSP_S_SPI1_MOSI_PIN
+ int "soft spi1 mosi pin number"
+ range 1 176
+ default 91
+ endif
+
+ menuconfig BSP_USING_SOFT_SPI2
+ bool "Enable soft SPI2 BUS (software simulation)"
+ default n
+ if BSP_USING_SOFT_SPI2
+ config BSP_S_SPI2_SCK_PIN
+ int "soft spi2 sck pin number"
+ range 1 176
+ default 19
+ config BSP_S_SPI2_MISO_PIN
+ int "soft spi2 miso pin number"
+ range 1 176
+ default 20
+ config BSP_S_SPI2_MOSI_PIN
+ int "soft spi2 mosi pin number"
+ range 1 176
+ default 21
+ endif
+ endif
+
menuconfig BSP_USING_SPI
bool "Enable SPI BUS"
default n
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/SConscript b/bsp/stm32/stm32f407-atk-explorer/board/SConscript
index 78b961dc11..3e55e4abba 100644
--- a/bsp/stm32/stm32f407-atk-explorer/board/SConscript
+++ b/bsp/stm32/stm32f407-atk-explorer/board/SConscript
@@ -18,6 +18,9 @@ path += [cwd + '/ports']
if GetDepend(['BSP_USING_ETH']):
src += Glob('ports/phy_reset.c')
+if GetDepend(['BSP_USING_SOFT_SPI_FLASH']):
+ src += Glob('ports/soft_spi_flash_init.c')
+
if GetDepend(['BSP_USING_SPI_FLASH']):
src += Glob('ports/spi_flash_init.c')
diff --git a/bsp/stm32/stm32f407-atk-explorer/board/ports/soft_spi_flash_init.c b/bsp/stm32/stm32f407-atk-explorer/board/ports/soft_spi_flash_init.c
new file mode 100644
index 0000000000..3221c84cc0
--- /dev/null
+++ b/bsp/stm32/stm32f407-atk-explorer/board/ports/soft_spi_flash_init.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2006-2022, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date Author Notes
+ * 2022-6-14 solar first version
+ */
+
+#include <rtthread.h>
+#include "spi_flash.h"
+#include "spi_flash_sfud.h"
+#include "drv_spi.h"
+#include "drv_soft_spi.h"
+
+#ifdef BSP_USING_SOFT_SPI_FLASH
+
+static int rt_soft_spi_flash_init(void)
+{
+ __HAL_RCC_GPIOB_CLK_ENABLE();
+ rt_hw_soft_spi_device_attach("sspi2", "sspi20", "PB.14");
+
+ if (RT_NULL == rt_sfud_flash_probe("W25Q128", "sspi20"))
+ {
+ return -RT_ERROR;
+ }
+
+ return RT_EOK;
+}
+INIT_COMPONENT_EXPORT(rt_soft_spi_flash_init);
+#endif /* BSP_USING_SOFT_SPI_FLASH */
diff --git a/components/drivers/spi/spi-bit-ops.h b/components/drivers/spi/spi-bit-ops.h
index f6dcd0d7ca..ecbea1ad4c 100644
--- a/components/drivers/spi/spi-bit-ops.h
+++ b/components/drivers/spi/spi-bit-ops.h
@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2021-10-11 kyle first version
+ * 2022-6-14 solar Remove the const attribute of private data in ops
*/
#ifndef __SPI_BIT_OPS_H__
@@ -19,7 +20,7 @@ extern "C" {
struct rt_spi_bit_ops
{
- void *const data; /* private data for lowlevel routines */
+ void *data; /* private data for lowlevel routines */
void (*const tog_sclk)(void *data);
void (*const set_sclk)(void *data, rt_int32_t state);
void (*const set_mosi)(void *data, rt_int32_t state);
generated by cgit v1.3.1 (git 2.54.0) at 2026-10-30 10:00:58 +0000